1/* $NetBSD: tegra234-mc.h,v 1.1.1.1 2026/01/18 05:21:49 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 4/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 5 6#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H 7#define DT_BINDINGS_MEMORY_TEGRA234_MC_H 8 9/* special clients */ 10#define TEGRA234_SID_INVALID 0x00 11#define TEGRA234_SID_PASSTHROUGH 0x7f 12 13/* ISO stream IDs */ 14#define TEGRA234_SID_ISO_NVDISPLAY 0x01 15#define TEGRA234_SID_ISO_VI 0x02 16#define TEGRA234_SID_ISO_VIFALC 0x03 17#define TEGRA234_SID_ISO_VI2 0x04 18#define TEGRA234_SID_ISO_VI2FALC 0x05 19#define TEGRA234_SID_ISO_VI_VM2 0x06 20#define TEGRA234_SID_ISO_VI2_VM2 0x07 21 22/* NISO0 stream IDs */ 23#define TEGRA234_SID_AON 0x01 24#define TEGRA234_SID_APE 0x02 25#define TEGRA234_SID_HDA 0x03 26#define TEGRA234_SID_GPCDMA 0x04 27#define TEGRA234_SID_ETR 0x05 28#define TEGRA234_SID_MGBE 0x06 29#define TEGRA234_SID_NVDISPLAY 0x07 30#define TEGRA234_SID_DCE 0x08 31#define TEGRA234_SID_PSC 0x09 32#define TEGRA234_SID_RCE 0x0a 33#define TEGRA234_SID_SCE 0x0b 34#define TEGRA234_SID_UFSHC 0x0c 35#define TEGRA234_SID_APE_1 0x0d 36#define TEGRA234_SID_GPCDMA_1 0x0e 37#define TEGRA234_SID_GPCDMA_2 0x0f 38#define TEGRA234_SID_GPCDMA_3 0x10 39#define TEGRA234_SID_GPCDMA_4 0x11 40#define TEGRA234_SID_PCIE0 0x12 41#define TEGRA234_SID_PCIE4 0x13 42#define TEGRA234_SID_PCIE5 0x14 43#define TEGRA234_SID_PCIE6 0x15 44#define TEGRA234_SID_RCE_VM2 0x16 45#define TEGRA234_SID_RCE_SERVER 0x17 46#define TEGRA234_SID_SMMU_TEST 0x18 47#define TEGRA234_SID_UFS_1 0x19 48#define TEGRA234_SID_UFS_2 0x1a 49#define TEGRA234_SID_UFS_3 0x1b 50#define TEGRA234_SID_UFS_4 0x1c 51#define TEGRA234_SID_UFS_5 0x1d 52#define TEGRA234_SID_UFS_6 0x1e 53#define TEGRA234_SID_PCIE9 0x1f 54#define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 55#define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 56#define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 57#define TEGRA234_SID_NVDLA1 0x23 58#define TEGRA234_SID_NVENC 0x24 59#define TEGRA234_SID_NVJPG1 0x25 60#define TEGRA234_SID_OFA 0x26 61#define TEGRA234_SID_MGBE_VF1 0x49 62#define TEGRA234_SID_MGBE_VF2 0x4a 63#define TEGRA234_SID_MGBE_VF3 0x4b 64#define TEGRA234_SID_MGBE_VF4 0x4c 65#define TEGRA234_SID_MGBE_VF5 0x4d 66#define TEGRA234_SID_MGBE_VF6 0x4e 67#define TEGRA234_SID_MGBE_VF7 0x4f 68#define TEGRA234_SID_MGBE_VF8 0x50 69#define TEGRA234_SID_MGBE_VF9 0x51 70#define TEGRA234_SID_MGBE_VF10 0x52 71#define TEGRA234_SID_MGBE_VF11 0x53 72#define TEGRA234_SID_MGBE_VF12 0x54 73#define TEGRA234_SID_MGBE_VF13 0x55 74#define TEGRA234_SID_MGBE_VF14 0x56 75#define TEGRA234_SID_MGBE_VF15 0x57 76#define TEGRA234_SID_MGBE_VF16 0x58 77#define TEGRA234_SID_MGBE_VF17 0x59 78#define TEGRA234_SID_MGBE_VF18 0x5a 79#define TEGRA234_SID_MGBE_VF19 0x5b 80#define TEGRA234_SID_MGBE_VF20 0x5c 81#define TEGRA234_SID_APE_2 0x5e 82#define TEGRA234_SID_APE_3 0x5f 83#define TEGRA234_SID_UFS_7 0x60 84#define TEGRA234_SID_UFS_8 0x61 85#define TEGRA234_SID_UFS_9 0x62 86#define TEGRA234_SID_UFS_10 0x63 87#define TEGRA234_SID_UFS_11 0x64 88#define TEGRA234_SID_UFS_12 0x65 89#define TEGRA234_SID_UFS_13 0x66 90#define TEGRA234_SID_UFS_14 0x67 91#define TEGRA234_SID_UFS_15 0x68 92#define TEGRA234_SID_UFS_16 0x69 93#define TEGRA234_SID_UFS_17 0x6a 94#define TEGRA234_SID_UFS_18 0x6b 95#define TEGRA234_SID_UFS_19 0x6c 96#define TEGRA234_SID_UFS_20 0x6d 97#define TEGRA234_SID_GPCDMA_5 0x6e 98#define TEGRA234_SID_GPCDMA_6 0x6f 99#define TEGRA234_SID_GPCDMA_7 0x70 100#define TEGRA234_SID_GPCDMA_8 0x71 101#define TEGRA234_SID_GPCDMA_9 0x72 102 103/* NISO1 stream IDs */ 104#define TEGRA234_SID_SDMMC1A 0x01 105#define TEGRA234_SID_SDMMC4 0x02 106#define TEGRA234_SID_EQOS 0x03 107#define TEGRA234_SID_HWMP_PMA 0x04 108#define TEGRA234_SID_PCIE1 0x05 109#define TEGRA234_SID_PCIE2 0x06 110#define TEGRA234_SID_PCIE3 0x07 111#define TEGRA234_SID_PCIE7 0x08 112#define TEGRA234_SID_PCIE8 0x09 113#define TEGRA234_SID_PCIE10 0x0b 114#define TEGRA234_SID_QSPI0 0x0c 115#define TEGRA234_SID_QSPI1 0x0d 116#define TEGRA234_SID_XUSB_HOST 0x0e 117#define TEGRA234_SID_XUSB_DEV 0x0f 118#define TEGRA234_SID_BPMP 0x10 119#define TEGRA234_SID_FSI 0x11 120#define TEGRA234_SID_PVA0_VM0 0x12 121#define TEGRA234_SID_PVA0_VM1 0x13 122#define TEGRA234_SID_PVA0_VM2 0x14 123#define TEGRA234_SID_PVA0_VM3 0x15 124#define TEGRA234_SID_PVA0_VM4 0x16 125#define TEGRA234_SID_PVA0_VM5 0x17 126#define TEGRA234_SID_PVA0_VM6 0x18 127#define TEGRA234_SID_PVA0_VM7 0x19 128#define TEGRA234_SID_XUSB_VF0 0x1a 129#define TEGRA234_SID_XUSB_VF1 0x1b 130#define TEGRA234_SID_XUSB_VF2 0x1c 131#define TEGRA234_SID_XUSB_VF3 0x1d 132#define TEGRA234_SID_EQOS_VF1 0x1e 133#define TEGRA234_SID_EQOS_VF2 0x1f 134#define TEGRA234_SID_EQOS_VF3 0x20 135#define TEGRA234_SID_EQOS_VF4 0x21 136#define TEGRA234_SID_ISP_VM2 0x22 137#define TEGRA234_SID_HOST1X 0x27 138#define TEGRA234_SID_ISP 0x28 139#define TEGRA234_SID_NVDEC 0x29 140#define TEGRA234_SID_NVJPG 0x2a 141#define TEGRA234_SID_NVDLA0 0x2b 142#define TEGRA234_SID_PVA0 0x2c 143#define TEGRA234_SID_SES_SE0 0x2d 144#define TEGRA234_SID_SES_SE1 0x2e 145#define TEGRA234_SID_SES_SE2 0x2f 146#define TEGRA234_SID_SEU1_SE0 0x30 147#define TEGRA234_SID_SEU1_SE1 0x31 148#define TEGRA234_SID_SEU1_SE2 0x32 149#define TEGRA234_SID_TSEC 0x33 150#define TEGRA234_SID_VIC 0x34 151#define TEGRA234_SID_HC_VM0 0x3d 152#define TEGRA234_SID_HC_VM1 0x3e 153#define TEGRA234_SID_HC_VM2 0x3f 154#define TEGRA234_SID_HC_VM3 0x40 155#define TEGRA234_SID_HC_VM4 0x41 156#define TEGRA234_SID_HC_VM5 0x42 157#define TEGRA234_SID_HC_VM6 0x43 158#define TEGRA234_SID_HC_VM7 0x44 159#define TEGRA234_SID_SE_VM0 0x45 160#define TEGRA234_SID_SE_VM1 0x46 161#define TEGRA234_SID_SE_VM2 0x47 162#define TEGRA234_SID_ISPFALC 0x48 163#define TEGRA234_SID_NISO1_SMMU_TEST 0x49 164#define TEGRA234_SID_TSEC_VM0 0x4a 165 166/* Shared stream IDs */ 167#define TEGRA234_SID_HOST1X_CTX0 0x35 168#define TEGRA234_SID_HOST1X_CTX1 0x36 169#define TEGRA234_SID_HOST1X_CTX2 0x37 170#define TEGRA234_SID_HOST1X_CTX3 0x38 171#define TEGRA234_SID_HOST1X_CTX4 0x39 172#define TEGRA234_SID_HOST1X_CTX5 0x3a 173#define TEGRA234_SID_HOST1X_CTX6 0x3b 174#define TEGRA234_SID_HOST1X_CTX7 0x3c 175 176/* 177 * memory client IDs 178 */ 179 180/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 181#define TEGRA234_MEMORY_CLIENT_PTCR 0x00 182/* MSS internal memqual MIU7 read clients */ 183#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 184/* MSS internal memqual MIU7 write clients */ 185#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 186/* MSS internal memqual MIU8 read clients */ 187#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 188/* MSS internal memqual MIU8 write clients */ 189#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 190/* MSS internal memqual MIU9 read clients */ 191#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 192/* MSS internal memqual MIU9 write clients */ 193#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 194/* MSS internal memqual MIU10 read clients */ 195#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 196/* MSS internal memqual MIU10 write clients */ 197#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 198/* MSS internal memqual MIU11 read clients */ 199#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 200/* MSS internal memqual MIU11 write clients */ 201#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a 202/* MSS internal memqual MIU12 read clients */ 203#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b 204/* MSS internal memqual MIU12 write clients */ 205#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c 206/* MSS internal memqual MIU13 read clients */ 207#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d 208/* MSS internal memqual MIU13 write clients */ 209#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e 210#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 211#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 212/* High-definition audio (HDA) read clients */ 213#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 214/* Host channel data read clients */ 215#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 216#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 217#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 218#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 219#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a 220#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b 221#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c 222#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d 223#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e 224#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 225#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 226#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 227#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 228#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 229#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 230/* PCIE6 read clients */ 231#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 232/* PCIE6 write clients */ 233#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 234/* PCIE7 read clients */ 235#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 236#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b 237/* DLA0ARDB read clients */ 238#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c 239/* DLA0ARDB1 read clients */ 240#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d 241/* DLA0 writes */ 242#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e 243/* DLA1ARDB read clients */ 244#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f 245/* PCIE7 write clients */ 246#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 247/* PCIE8 read clients */ 248#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 249/* High-definition audio (HDA) write clients */ 250#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 251/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 252#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 253/* OFAA client */ 254#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a 255/* PCIE8 write clients */ 256#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 257/* PCIE9 read clients */ 258#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c 259/* PCIE6r1 read clients */ 260#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d 261/* PCIE9 write clients */ 262#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e 263/* PCIE10 read clients */ 264#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 265/* PCIE10 write clients */ 266#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 267/* ISP read client for Crossbar A */ 268#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 269/* ISP read client 1 for Crossbar A */ 270#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 271/* ISP Write client for Crossbar A */ 272#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 273/* ISP Write client Crossbar B */ 274#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 275/* PCIE10r1 read clients */ 276#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 277/* PCIE7r1 read clients */ 278#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 279/* XUSB_HOST read clients */ 280#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a 281/* XUSB_HOST write clients */ 282#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b 283/* XUSB read clients */ 284#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c 285/* XUSB_DEV write clients */ 286#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d 287/* TSEC Memory Return Data Client Description */ 288#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 289/* TSEC Memory Write Client Description */ 290#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 291/* XSPI writes */ 292#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 293/* MGBE0 read client */ 294#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 295/* MGBEB read client */ 296#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 297/* MGBEC read client */ 298#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a 299/* MGBED read client */ 300#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b 301/* MGBE0 write client */ 302#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c 303/* OFAA client */ 304#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d 305/* OFAA writes */ 306#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e 307/* MGBEB write client */ 308#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f 309/* sdmmca memory read client */ 310#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 311/* MGBEC write client */ 312#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 313/* sdmmcd memory read client */ 314#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 315/* sdmmca memory write client */ 316#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 317/* MGBED write client */ 318#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 319/* sdmmcd memory write client */ 320#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 321/* SE Memory Return Data Client Description */ 322#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 323/* SE Memory Write Client Description */ 324#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 325#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 326#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 327/* DLA1ARDB1 read clients */ 328#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e 329/* DLA1 writes */ 330#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f 331/* VI FLACON read clients */ 332#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 333/* VI Write client */ 334#define TEGRA234_MEMORY_CLIENT_VI2W 0x70 335/* VI Write client */ 336#define TEGRA234_MEMORY_CLIENT_VIW 0x72 337/* NISO display read client */ 338#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 339/* NVDISPNISO writes */ 340#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 341/* XSPI client */ 342#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 343/* XSPI writes */ 344#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 345/* XSPI client */ 346#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 347#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 348#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 349/* Audio Processing (APE) engine read clients */ 350#define TEGRA234_MEMORY_CLIENT_APER 0x7a 351/* Audio Processing (APE) engine write clients */ 352#define TEGRA234_MEMORY_CLIENT_APEW 0x7b 353/* VI2FAL writes */ 354#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c 355#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e 356#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f 357/* SE Memory Return Data Client Description */ 358#define TEGRA234_MEMORY_CLIENT_SESRD 0x80 359/* SE Memory Write Client Description */ 360#define TEGRA234_MEMORY_CLIENT_SESWR 0x81 361/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 362#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 363/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 364#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 365/* ETR read clients */ 366#define TEGRA234_MEMORY_CLIENT_ETRR 0x84 367/* ETR write clients */ 368#define TEGRA234_MEMORY_CLIENT_ETRW 0x85 369/* AXI Switch read client */ 370#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c 371/* AXI Switch write client */ 372#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d 373/* EQOS read client */ 374#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e 375/* EQOS write client */ 376#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f 377/* UFSHC read client */ 378#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 379/* UFSHC write client */ 380#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 381/* NVDISPLAY read client */ 382#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 383/* BPMP read client */ 384#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 385/* BPMP write client */ 386#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 387/* BPMPDMA read client */ 388#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 389/* BPMPDMA write client */ 390#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 391/* AON read client */ 392#define TEGRA234_MEMORY_CLIENT_AONR 0x97 393/* AON write client */ 394#define TEGRA234_MEMORY_CLIENT_AONW 0x98 395/* AONDMA read client */ 396#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 397/* AONDMA write client */ 398#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a 399/* SCE read client */ 400#define TEGRA234_MEMORY_CLIENT_SCER 0x9b 401/* SCE write client */ 402#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c 403/* SCEDMA read client */ 404#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d 405/* SCEDMA write client */ 406#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e 407/* APEDMA read client */ 408#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 409/* APEDMA write client */ 410#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 411/* NVDISPLAY read client instance 2 */ 412#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 413#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 414/* MSS internal memqual MIU0 read clients */ 415#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 416/* MSS internal memqual MIU0 write clients */ 417#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 418/* MSS internal memqual MIU1 read clients */ 419#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 420/* MSS internal memqual MIU1 write clients */ 421#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 422/* MSS internal memqual MIU2 read clients */ 423#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae 424/* MSS internal memqual MIU2 write clients */ 425#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf 426/* MSS internal memqual MIU3 read clients */ 427#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 428/* MSS internal memqual MIU3 write clients */ 429#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 430/* MSS internal memqual MIU4 read clients */ 431#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 432/* MSS internal memqual MIU4 write clients */ 433#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 434#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 435#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 436#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 437#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 438#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 439#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 440#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba 441#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb 442/* VI FLACON read clients */ 443#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc 444/* VIFAL write clients */ 445#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd 446/* DLA0ARDA read clients */ 447#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe 448/* DLA0 Falcon read clients */ 449#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf 450/* DLA0 write clients */ 451#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 452/* DLA0 write clients */ 453#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 454/* DLA1ARDA read clients */ 455#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 456/* DLA1 Falcon read clients */ 457#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 458/* DLA1 write clients */ 459#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 460/* DLA1 write clients */ 461#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 462/* PVA0RDA read clients */ 463#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 464/* PVA0RDB read clients */ 465#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 466/* PVA0RDC read clients */ 467#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 468/* PVA0WRA write clients */ 469#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 470/* PVA0WRB write clients */ 471#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca 472/* PVA0WRC write clients */ 473#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb 474/* RCE read client */ 475#define TEGRA234_MEMORY_CLIENT_RCER 0xd2 476/* RCE write client */ 477#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 478/* RCEDMA read client */ 479#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 480/* RCEDMA write client */ 481#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 482/* PCIE0 read clients */ 483#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 484/* PCIE0 write clients */ 485#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 486/* PCIE1 read clients */ 487#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda 488/* PCIE1 write clients */ 489#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb 490/* PCIE2 read clients */ 491#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc 492/* PCIE2 write clients */ 493#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd 494/* PCIE3 read clients */ 495#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde 496/* PCIE3 write clients */ 497#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf 498/* PCIE4 read clients */ 499#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 500/* PCIE4 write clients */ 501#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 502/* PCIE5 read clients */ 503#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 504/* PCIE5 write clients */ 505#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 506/* ISP read client 1 for Crossbar A */ 507#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 508#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 509#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 510#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 511#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 512/* DLA0ARDA1 read clients */ 513#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 514/* DLA1ARDA1 read clients */ 515#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea 516/* PVA0RDA1 read clients */ 517#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb 518/* PVA0RDB1 read clients */ 519#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec 520/* PCIE5r1 read clients */ 521#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 522#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 523/* ISP read client for Crossbar A */ 524#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 525#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 526#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 527#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 528#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 529#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 530/* MSS internal memqual MIU5 read clients */ 531#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc 532/* MSS internal memqual MIU5 write clients */ 533#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd 534/* MSS internal memqual MIU6 read clients */ 535#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe 536/* MSS internal memqual MIU6 write clients */ 537#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff 538#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 539#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 540 541/* ICC ID's for dummy MC clients used to represent CPU Clusters */ 542#define TEGRA_ICC_MC_CPU_CLUSTER0 1003 543#define TEGRA_ICC_MC_CPU_CLUSTER1 1004 544#define TEGRA_ICC_MC_CPU_CLUSTER2 1005 545 546#endif 547