1 /* $NetBSD: lochnagar.h,v 1.1.1.1 2019/05/25 11:29:13 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Device Tree defines for Lochnagar pinctrl 6 * 7 * Copyright (c) 2018 Cirrus Logic, Inc. and 8 * Cirrus Logic International Semiconductor Ltd. 9 * 10 * Author: Charles Keepax <ckeepax (at) opensource.cirrus.com> 11 */ 12 13 #ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H 14 #define DT_BINDINGS_PINCTRL_LOCHNAGAR_H 15 16 #define LOCHNAGAR1_PIN_CDC_RESET 0 17 #define LOCHNAGAR1_PIN_DSP_RESET 1 18 #define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 19 #define LOCHNAGAR1_PIN_NUM_GPIOS 3 20 21 #define LOCHNAGAR2_PIN_CDC_RESET 0 22 #define LOCHNAGAR2_PIN_DSP_RESET 1 23 #define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 24 #define LOCHNAGAR2_PIN_CDC_LDOENA 3 25 #define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 26 #define LOCHNAGAR2_PIN_SPDIF_RESET 5 27 #define LOCHNAGAR2_PIN_FPGA_GPIO1 6 28 #define LOCHNAGAR2_PIN_FPGA_GPIO2 7 29 #define LOCHNAGAR2_PIN_FPGA_GPIO3 8 30 #define LOCHNAGAR2_PIN_FPGA_GPIO4 9 31 #define LOCHNAGAR2_PIN_FPGA_GPIO5 10 32 #define LOCHNAGAR2_PIN_FPGA_GPIO6 11 33 #define LOCHNAGAR2_PIN_CDC_GPIO1 12 34 #define LOCHNAGAR2_PIN_CDC_GPIO2 13 35 #define LOCHNAGAR2_PIN_CDC_GPIO3 14 36 #define LOCHNAGAR2_PIN_CDC_GPIO4 15 37 #define LOCHNAGAR2_PIN_CDC_GPIO5 16 38 #define LOCHNAGAR2_PIN_CDC_GPIO6 17 39 #define LOCHNAGAR2_PIN_CDC_GPIO7 18 40 #define LOCHNAGAR2_PIN_CDC_GPIO8 19 41 #define LOCHNAGAR2_PIN_DSP_GPIO1 20 42 #define LOCHNAGAR2_PIN_DSP_GPIO2 21 43 #define LOCHNAGAR2_PIN_DSP_GPIO3 22 44 #define LOCHNAGAR2_PIN_DSP_GPIO4 23 45 #define LOCHNAGAR2_PIN_DSP_GPIO5 24 46 #define LOCHNAGAR2_PIN_DSP_GPIO6 25 47 #define LOCHNAGAR2_PIN_GF_GPIO2 26 48 #define LOCHNAGAR2_PIN_GF_GPIO3 27 49 #define LOCHNAGAR2_PIN_GF_GPIO7 28 50 #define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 51 #define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 52 #define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 53 #define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 54 #define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 55 #define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 56 #define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 57 #define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 58 #define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 59 #define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 60 #define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 61 #define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 62 #define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 63 #define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 64 #define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 65 #define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 66 #define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 67 #define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 68 #define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 69 #define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 70 #define LOCHNAGAR2_PIN_PSIA1_BCLK 49 71 #define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 72 #define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 73 #define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 74 #define LOCHNAGAR2_PIN_PSIA2_BCLK 53 75 #define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 76 #define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 77 #define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 78 #define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 79 #define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 80 #define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 81 #define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 82 #define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 83 #define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 84 #define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 85 #define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 86 #define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 87 #define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 88 #define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 89 #define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 90 #define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 91 #define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 92 #define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 93 #define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 94 #define LOCHNAGAR2_PIN_DSP_UART1_RX 73 95 #define LOCHNAGAR2_PIN_DSP_UART1_TX 74 96 #define LOCHNAGAR2_PIN_DSP_UART2_RX 75 97 #define LOCHNAGAR2_PIN_DSP_UART2_TX 76 98 #define LOCHNAGAR2_PIN_GF_UART2_RX 77 99 #define LOCHNAGAR2_PIN_GF_UART2_TX 78 100 #define LOCHNAGAR2_PIN_USB_UART_RX 79 101 #define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 102 #define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 103 #define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 104 #define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 105 #define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 106 #define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 107 #define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 108 #define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 109 #define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 110 #define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 111 #define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 112 #define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 113 #define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 114 #define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 115 #define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 116 #define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 117 #define LOCHNAGAR2_PIN_I2C2_SCL 96 118 #define LOCHNAGAR2_PIN_I2C2_SDA 97 119 #define LOCHNAGAR2_PIN_I2C3_SCL 98 120 #define LOCHNAGAR2_PIN_I2C3_SDA 99 121 #define LOCHNAGAR2_PIN_I2C4_SCL 100 122 #define LOCHNAGAR2_PIN_I2C4_SDA 101 123 #define LOCHNAGAR2_PIN_DSP_STANDBY 102 124 #define LOCHNAGAR2_PIN_CDC_MCLK1 103 125 #define LOCHNAGAR2_PIN_CDC_MCLK2 104 126 #define LOCHNAGAR2_PIN_DSP_CLKIN 105 127 #define LOCHNAGAR2_PIN_PSIA1_MCLK 106 128 #define LOCHNAGAR2_PIN_PSIA2_MCLK 107 129 #define LOCHNAGAR2_PIN_GF_GPIO1 108 130 #define LOCHNAGAR2_PIN_GF_GPIO5 109 131 #define LOCHNAGAR2_PIN_DSP_GPIO20 110 132 #define LOCHNAGAR2_PIN_NUM_GPIOS 111 133 134 #endif 135
Indexes created Sun Sep 28 12:09:53 GMT 2025