1/*	$NetBSD: mt8195-power.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
4/*
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
7 */
8
9#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
10#define _DT_BINDINGS_POWER_MT8195_POWER_H
11
12#define MT8195_POWER_DOMAIN_PCIE_MAC_P0		0
13#define MT8195_POWER_DOMAIN_PCIE_MAC_P1		1
14#define MT8195_POWER_DOMAIN_PCIE_PHY		2
15#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY	3
16#define MT8195_POWER_DOMAIN_CSI_RX_TOP		4
17#define MT8195_POWER_DOMAIN_ETHER		5
18#define MT8195_POWER_DOMAIN_ADSP		6
19#define MT8195_POWER_DOMAIN_AUDIO		7
20#define MT8195_POWER_DOMAIN_MFG0		8
21#define MT8195_POWER_DOMAIN_MFG1		9
22#define MT8195_POWER_DOMAIN_MFG2		10
23#define MT8195_POWER_DOMAIN_MFG3		11
24#define MT8195_POWER_DOMAIN_MFG4		12
25#define MT8195_POWER_DOMAIN_MFG5		13
26#define MT8195_POWER_DOMAIN_MFG6		14
27#define MT8195_POWER_DOMAIN_VPPSYS0		15
28#define MT8195_POWER_DOMAIN_VDOSYS0		16
29#define MT8195_POWER_DOMAIN_VPPSYS1		17
30#define MT8195_POWER_DOMAIN_VDOSYS1		18
31#define MT8195_POWER_DOMAIN_DP_TX		19
32#define MT8195_POWER_DOMAIN_EPD_TX		20
33#define MT8195_POWER_DOMAIN_HDMI_TX		21
34#define MT8195_POWER_DOMAIN_WPESYS		22
35#define MT8195_POWER_DOMAIN_VDEC0		23
36#define MT8195_POWER_DOMAIN_VDEC1		24
37#define MT8195_POWER_DOMAIN_VDEC2		25
38#define MT8195_POWER_DOMAIN_VENC		26
39#define MT8195_POWER_DOMAIN_VENC_CORE1		27
40#define MT8195_POWER_DOMAIN_IMG			28
41#define MT8195_POWER_DOMAIN_DIP			29
42#define MT8195_POWER_DOMAIN_IPE			30
43#define MT8195_POWER_DOMAIN_CAM			31
44#define MT8195_POWER_DOMAIN_CAM_RAWA		32
45#define MT8195_POWER_DOMAIN_CAM_RAWB		33
46#define MT8195_POWER_DOMAIN_CAM_MRAW		34
47
48#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
49