1 1.1 jmcneill /* $NetBSD: r8a77980-sysc.h,v 1.1.1.2 2019/05/25 11:29:13 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0 4 1.1 jmcneill * 5 1.1 jmcneill * Copyright (C) 2018 Renesas Electronics Corp. 6 1.1 jmcneill * Copyright (C) 2018 Cogent Embedded, Inc. 7 1.1 jmcneill */ 8 1.1 jmcneill #ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__ 9 1.1 jmcneill #define __DT_BINDINGS_POWER_R8A77980_SYSC_H__ 10 1.1 jmcneill 11 1.1 jmcneill /* 12 1.1 jmcneill * These power domain indices match the numbers of the interrupt bits 13 1.1 jmcneill * representing the power areas in the various Interrupt Registers 14 1.1 jmcneill * (e.g. SYSCISR, Interrupt Status Register) 15 1.1 jmcneill */ 16 1.1 jmcneill 17 1.1 jmcneill #define R8A77980_PD_A2SC2 0 18 1.1 jmcneill #define R8A77980_PD_A2SC3 1 19 1.1 jmcneill #define R8A77980_PD_A2SC4 2 20 1.1.1.2 jmcneill #define R8A77980_PD_A2DP0 3 21 1.1.1.2 jmcneill #define R8A77980_PD_A2DP1 4 22 1.1 jmcneill #define R8A77980_PD_CA53_CPU0 5 23 1.1 jmcneill #define R8A77980_PD_CA53_CPU1 6 24 1.1 jmcneill #define R8A77980_PD_CA53_CPU2 7 25 1.1 jmcneill #define R8A77980_PD_CA53_CPU3 8 26 1.1 jmcneill #define R8A77980_PD_A2CN 10 27 1.1.1.2 jmcneill #define R8A77980_PD_A3VIP0 11 28 1.1 jmcneill #define R8A77980_PD_A2IR5 12 29 1.1 jmcneill #define R8A77980_PD_CR7 13 30 1.1 jmcneill #define R8A77980_PD_A2IR4 15 31 1.1 jmcneill #define R8A77980_PD_CA53_SCU 21 32 1.1 jmcneill #define R8A77980_PD_A2IR0 23 33 1.1 jmcneill #define R8A77980_PD_A3IR 24 34 1.1 jmcneill #define R8A77980_PD_A3VIP1 25 35 1.1 jmcneill #define R8A77980_PD_A3VIP2 26 36 1.1 jmcneill #define R8A77980_PD_A2IR1 27 37 1.1 jmcneill #define R8A77980_PD_A2IR2 28 38 1.1 jmcneill #define R8A77980_PD_A2IR3 29 39 1.1 jmcneill #define R8A77980_PD_A2SC0 30 40 1.1 jmcneill #define R8A77980_PD_A2SC1 31 41 1.1 jmcneill 42 1.1 jmcneill /* Always-on power area */ 43 1.1 jmcneill #define R8A77980_PD_ALWAYS_ON 32 44 1.1 jmcneill 45 1.1 jmcneill #endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */ 46