11.1Sskrll/*	$NetBSD: airoha,en7581-reset.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $	*/
21.1Sskrll
31.1Sskrll// SPDX-License-Identifier: GPL-2.0-only
41.1Sskrll/*
51.1Sskrll * Copyright (c) 2024 AIROHA Inc
61.1Sskrll * Author: Lorenzo Bianconi <lorenzo@kernel.org>
71.1Sskrll */
81.1Sskrll
91.1Sskrll#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
101.1Sskrll#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
111.1Sskrll
121.1Sskrll/* RST_CTRL2 */
131.1Sskrll#define EN7581_XPON_PHY_RST		 0
141.1Sskrll#define EN7581_CPU_TIMER2_RST		 1
151.1Sskrll#define EN7581_HSUART_RST		 2
161.1Sskrll#define EN7581_UART4_RST		 3
171.1Sskrll#define EN7581_UART5_RST		 4
181.1Sskrll#define EN7581_I2C2_RST			 5
191.1Sskrll#define EN7581_XSI_MAC_RST		 6
201.1Sskrll#define EN7581_XSI_PHY_RST		 7
211.1Sskrll#define EN7581_NPU_RST			 8
221.1Sskrll#define EN7581_I2S_RST			 9
231.1Sskrll#define EN7581_TRNG_RST			10
241.1Sskrll#define EN7581_TRNG_MSTART_RST		11
251.1Sskrll#define EN7581_DUAL_HSI0_RST		12
261.1Sskrll#define EN7581_DUAL_HSI1_RST		13
271.1Sskrll#define EN7581_HSI_RST			14
281.1Sskrll#define EN7581_DUAL_HSI0_MAC_RST	15
291.1Sskrll#define EN7581_DUAL_HSI1_MAC_RST	16
301.1Sskrll#define EN7581_HSI_MAC_RST		17
311.1Sskrll#define EN7581_WDMA_RST			18
321.1Sskrll#define EN7581_WOE0_RST			19
331.1Sskrll#define EN7581_WOE1_RST			20
341.1Sskrll#define EN7581_HSDMA_RST		21
351.1Sskrll#define EN7581_TDMA_RST			22
361.1Sskrll#define EN7581_EMMC_RST			23
371.1Sskrll#define EN7581_SOE_RST			24
381.1Sskrll#define EN7581_PCIE2_RST		25
391.1Sskrll#define EN7581_XFP_MAC_RST		26
401.1Sskrll#define EN7581_USB_HOST_P1_RST		27
411.1Sskrll#define EN7581_USB_HOST_P1_U3_PHY_RST	28
421.1Sskrll/* RST_CTRL1 */
431.1Sskrll#define EN7581_PCM1_ZSI_ISI_RST		29
441.1Sskrll#define EN7581_FE_PDMA_RST		30
451.1Sskrll#define EN7581_FE_QDMA_RST		31
461.1Sskrll#define EN7581_PCM_SPIWP_RST		32
471.1Sskrll#define EN7581_CRYPTO_RST		33
481.1Sskrll#define EN7581_TIMER_RST		34
491.1Sskrll#define EN7581_PCM1_RST			35
501.1Sskrll#define EN7581_UART_RST			36
511.1Sskrll#define EN7581_GPIO_RST			37
521.1Sskrll#define EN7581_GDMA_RST			38
531.1Sskrll#define EN7581_I2C_MASTER_RST		39
541.1Sskrll#define EN7581_PCM2_ZSI_ISI_RST		40
551.1Sskrll#define EN7581_SFC_RST			41
561.1Sskrll#define EN7581_UART2_RST		42
571.1Sskrll#define EN7581_GDMP_RST			43
581.1Sskrll#define EN7581_FE_RST			44
591.1Sskrll#define EN7581_USB_HOST_P0_RST		45
601.1Sskrll#define EN7581_GSW_RST			46
611.1Sskrll#define EN7581_SFC2_PCM_RST		47
621.1Sskrll#define EN7581_PCIE0_RST		48
631.1Sskrll#define EN7581_PCIE1_RST		49
641.1Sskrll#define EN7581_CPU_TIMER_RST		50
651.1Sskrll#define EN7581_PCIE_HB_RST		51
661.1Sskrll#define EN7581_XPON_MAC_RST		52
671.1Sskrll
681.1Sskrll#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */
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