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      1 /*	$NetBSD: amlogic,meson-gxbb-reset.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      4 /*
      5  * Copyright (c) 2016 BayLibre, SAS.
      6  * Author: Neil Armstrong <narmstrong (at) baylibre.com>
      7  */
      8 #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
      9 #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
     10 
     11 /*	RESET0					*/
     12 #define RESET_HIU			0
     13 /*					1	*/
     14 #define RESET_DOS_RESET			2
     15 #define RESET_DDR_TOP			3
     16 #define RESET_DCU_RESET			4
     17 #define RESET_VIU			5
     18 #define RESET_AIU			6
     19 #define RESET_VID_PLL_DIV		7
     20 /*					8	*/
     21 #define RESET_PMUX			9
     22 #define RESET_VENC			10
     23 #define RESET_ASSIST			11
     24 #define RESET_AFIFO2			12
     25 #define RESET_VCBUS			13
     26 /*					14	*/
     27 /*					15	*/
     28 #define RESET_GIC			16
     29 #define RESET_CAPB3_DECODE		17
     30 #define RESET_NAND_CAPB3		18
     31 #define RESET_HDMITX_CAPB3		19
     32 #define RESET_MALI_CAPB3		20
     33 #define RESET_DOS_CAPB3			21
     34 #define RESET_SYS_CPU_CAPB3		22
     35 #define RESET_CBUS_CAPB3		23
     36 #define RESET_AHB_CNTL			24
     37 #define RESET_AHB_DATA			25
     38 #define RESET_VCBUS_CLK81		26
     39 #define RESET_MMC			27
     40 #define RESET_MIPI_0			28
     41 #define RESET_MIPI_1			29
     42 #define RESET_MIPI_2			30
     43 #define RESET_MIPI_3			31
     44 /*	RESET1					*/
     45 #define RESET_CPPM			32
     46 #define RESET_DEMUX			33
     47 #define RESET_USB_OTG			34
     48 #define RESET_DDR			35
     49 #define RESET_AO_RESET			36
     50 #define RESET_BT656			37
     51 #define RESET_AHB_SRAM			38
     52 /*					39	*/
     53 #define RESET_PARSER			40
     54 #define RESET_BLKMV			41
     55 #define RESET_ISA			42
     56 #define RESET_ETHERNET			43
     57 #define RESET_SD_EMMC_A			44
     58 #define RESET_SD_EMMC_B			45
     59 #define RESET_SD_EMMC_C			46
     60 #define RESET_ROM_BOOT			47
     61 #define RESET_SYS_CPU_0			48
     62 #define RESET_SYS_CPU_1			49
     63 #define RESET_SYS_CPU_2			50
     64 #define RESET_SYS_CPU_3			51
     65 #define RESET_SYS_CPU_CORE_0		52
     66 #define RESET_SYS_CPU_CORE_1		53
     67 #define RESET_SYS_CPU_CORE_2		54
     68 #define RESET_SYS_CPU_CORE_3		55
     69 #define RESET_SYS_PLL_DIV		56
     70 #define RESET_SYS_CPU_AXI		57
     71 #define RESET_SYS_CPU_L2		58
     72 #define RESET_SYS_CPU_P			59
     73 #define RESET_SYS_CPU_MBIST		60
     74 #define RESET_ACODEC			61
     75 /*					62	*/
     76 /*					63	*/
     77 /*	RESET2					*/
     78 #define RESET_VD_RMEM			64
     79 #define RESET_AUDIN			65
     80 #define RESET_HDMI_TX			66
     81 /*					67	*/
     82 /*					68	*/
     83 /*					69	*/
     84 #define RESET_GE2D			70
     85 #define RESET_PARSER_REG		71
     86 #define RESET_PARSER_FETCH		72
     87 #define RESET_PARSER_CTL		73
     88 #define RESET_PARSER_TOP		74
     89 /*					75	*/
     90 /*					76	*/
     91 #define RESET_AO_CPU_RESET		77
     92 #define RESET_MALI			78
     93 #define RESET_HDMI_SYSTEM_RESET		79
     94 /*					80-95	*/
     95 /*	RESET3					*/
     96 #define RESET_RING_OSCILLATOR		96
     97 #define RESET_SYS_CPU			97
     98 #define RESET_EFUSE			98
     99 #define RESET_SYS_CPU_BVCI		99
    100 #define RESET_AIFIFO			100
    101 #define RESET_TVFE			101
    102 #define RESET_AHB_BRIDGE_CNTL		102
    103 /*					103	*/
    104 #define RESET_AUDIO_DAC			104
    105 #define RESET_DEMUX_TOP			105
    106 #define RESET_DEMUX_DES			106
    107 #define RESET_DEMUX_S2P_0		107
    108 #define RESET_DEMUX_S2P_1		108
    109 #define RESET_DEMUX_RESET_0		109
    110 #define RESET_DEMUX_RESET_1		110
    111 #define RESET_DEMUX_RESET_2		111
    112 /*					112-127	*/
    113 /*	RESET4					*/
    114 /*					128	*/
    115 /*					129	*/
    116 /*					130	*/
    117 /*					131	*/
    118 #define RESET_DVIN_RESET		132
    119 #define RESET_RDMA			133
    120 #define RESET_VENCI			134
    121 #define RESET_VENCP			135
    122 /*					136	*/
    123 #define RESET_VDAC			137
    124 #define RESET_RTC			138
    125 /*					139	*/
    126 #define RESET_VDI6			140
    127 #define RESET_VENCL			141
    128 #define RESET_I2C_MASTER_2		142
    129 #define RESET_I2C_MASTER_1		143
    130 /*					144-159	*/
    131 /*	RESET5					*/
    132 /*					160-191	*/
    133 /*	RESET6					*/
    134 #define RESET_PERIPHS_GENERAL		192
    135 #define RESET_PERIPHS_SPICC		193
    136 #define RESET_PERIPHS_SMART_CARD	194
    137 #define RESET_PERIPHS_SAR_ADC		195
    138 #define RESET_PERIPHS_I2C_MASTER_0	196
    139 #define RESET_SANA			197
    140 /*					198	*/
    141 #define RESET_PERIPHS_STREAM_INTERFACE	199
    142 #define RESET_PERIPHS_SDIO		200
    143 #define RESET_PERIPHS_UART_0		201
    144 #define RESET_PERIPHS_UART_1_2		202
    145 #define RESET_PERIPHS_ASYNC_0		203
    146 #define RESET_PERIPHS_ASYNC_1		204
    147 #define RESET_PERIPHS_SPI_0		205
    148 #define RESET_PERIPHS_SDHC		206
    149 #define RESET_UART_SLIP			207
    150 /*					208-223	*/
    151 /*	RESET7					*/
    152 #define RESET_USB_DDR_0			224
    153 #define RESET_USB_DDR_1			225
    154 #define RESET_USB_DDR_2			226
    155 #define RESET_USB_DDR_3			227
    156 /*					228	*/
    157 #define RESET_DEVICE_MMC_ARB		229
    158 /*					230	*/
    159 #define RESET_VID_LOCK			231
    160 #define RESET_A9_DMC_PIPEL		232
    161 /*					233-255	*/
    162 
    163 #endif
    164