amlogic,meson-gxbb-reset.h revision 1.1.1.1.4.2
1 /* $NetBSD: amlogic,meson-gxbb-reset.h,v 1.1.1.1.4.2 2017/07/18 16:08:59 snj Exp $ */ 2 3 /* 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright (c) 2016 BayLibre, SAS. 10 * Author: Neil Armstrong <narmstrong (at) baylibre.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 * The full GNU General Public License is included in this distribution 24 * in the file called COPYING. 25 * 26 * BSD LICENSE 27 * 28 * Copyright (c) 2016 BayLibre, SAS. 29 * Author: Neil Armstrong <narmstrong (at) baylibre.com> 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * * Neither the name of Intel Corporation nor the names of its 42 * contributors may be used to endorse or promote products derived 43 * from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 46 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 47 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 48 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 49 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 */ 57 #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 58 #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H 59 60 /* RESET0 */ 61 #define RESET_HIU 0 62 /* 1 */ 63 #define RESET_DOS_RESET 2 64 #define RESET_DDR_TOP 3 65 #define RESET_DCU_RESET 4 66 #define RESET_VIU 5 67 #define RESET_AIU 6 68 #define RESET_VID_PLL_DIV 7 69 /* 8 */ 70 #define RESET_PMUX 9 71 #define RESET_VENC 10 72 #define RESET_ASSIST 11 73 #define RESET_AFIFO2 12 74 #define RESET_VCBUS 13 75 /* 14 */ 76 /* 15 */ 77 #define RESET_GIC 16 78 #define RESET_CAPB3_DECODE 17 79 #define RESET_NAND_CAPB3 18 80 #define RESET_HDMITX_CAPB3 19 81 #define RESET_MALI_CAPB3 20 82 #define RESET_DOS_CAPB3 21 83 #define RESET_SYS_CPU_CAPB3 22 84 #define RESET_CBUS_CAPB3 23 85 #define RESET_AHB_CNTL 24 86 #define RESET_AHB_DATA 25 87 #define RESET_VCBUS_CLK81 26 88 #define RESET_MMC 27 89 #define RESET_MIPI_0 28 90 #define RESET_MIPI_1 29 91 #define RESET_MIPI_2 30 92 #define RESET_MIPI_3 31 93 /* RESET1 */ 94 #define RESET_CPPM 32 95 #define RESET_DEMUX 33 96 #define RESET_USB_OTG 34 97 #define RESET_DDR 35 98 #define RESET_AO_RESET 36 99 #define RESET_BT656 37 100 #define RESET_AHB_SRAM 38 101 /* 39 */ 102 #define RESET_PARSER 40 103 #define RESET_BLKMV 41 104 #define RESET_ISA 42 105 #define RESET_ETHERNET 43 106 #define RESET_SD_EMMC_A 44 107 #define RESET_SD_EMMC_B 45 108 #define RESET_SD_EMMC_C 46 109 #define RESET_ROM_BOOT 47 110 #define RESET_SYS_CPU_0 48 111 #define RESET_SYS_CPU_1 49 112 #define RESET_SYS_CPU_2 50 113 #define RESET_SYS_CPU_3 51 114 #define RESET_SYS_CPU_CORE_0 52 115 #define RESET_SYS_CPU_CORE_1 53 116 #define RESET_SYS_CPU_CORE_2 54 117 #define RESET_SYS_CPU_CORE_3 55 118 #define RESET_SYS_PLL_DIV 56 119 #define RESET_SYS_CPU_AXI 57 120 #define RESET_SYS_CPU_L2 58 121 #define RESET_SYS_CPU_P 59 122 #define RESET_SYS_CPU_MBIST 60 123 /* 61 */ 124 /* 62 */ 125 /* 63 */ 126 /* RESET2 */ 127 #define RESET_VD_RMEM 64 128 #define RESET_AUDIN 65 129 #define RESET_HDMI_TX 66 130 /* 67 */ 131 /* 68 */ 132 /* 69 */ 133 #define RESET_GE2D 70 134 #define RESET_PARSER_REG 71 135 #define RESET_PARSER_FETCH 72 136 #define RESET_PARSER_CTL 73 137 #define RESET_PARSER_TOP 74 138 /* 75 */ 139 /* 76 */ 140 #define RESET_AO_CPU_RESET 77 141 #define RESET_MALI 78 142 #define RESET_HDMI_SYSTEM_RESET 79 143 /* 80-95 */ 144 /* RESET3 */ 145 #define RESET_RING_OSCILLATOR 96 146 #define RESET_SYS_CPU 97 147 #define RESET_EFUSE 98 148 #define RESET_SYS_CPU_BVCI 99 149 #define RESET_AIFIFO 100 150 #define RESET_TVFE 101 151 #define RESET_AHB_BRIDGE_CNTL 102 152 /* 103 */ 153 #define RESET_AUDIO_DAC 104 154 #define RESET_DEMUX_TOP 105 155 #define RESET_DEMUX_DES 106 156 #define RESET_DEMUX_S2P_0 107 157 #define RESET_DEMUX_S2P_1 108 158 #define RESET_DEMUX_RESET_0 109 159 #define RESET_DEMUX_RESET_1 110 160 #define RESET_DEMUX_RESET_2 111 161 /* 112-127 */ 162 /* RESET4 */ 163 /* 128 */ 164 /* 129 */ 165 /* 130 */ 166 /* 131 */ 167 #define RESET_DVIN_RESET 132 168 #define RESET_RDMA 133 169 #define RESET_VENCI 134 170 #define RESET_VENCP 135 171 /* 136 */ 172 #define RESET_VDAC 137 173 #define RESET_RTC 138 174 /* 139 */ 175 #define RESET_VDI6 140 176 #define RESET_VENCL 141 177 #define RESET_I2C_MASTER_2 142 178 #define RESET_I2C_MASTER_1 143 179 /* 144-159 */ 180 /* RESET5 */ 181 /* 160-191 */ 182 /* RESET6 */ 183 #define RESET_PERIPHS_GENERAL 192 184 #define RESET_PERIPHS_SPICC 193 185 #define RESET_PERIPHS_SMART_CARD 194 186 #define RESET_PERIPHS_SAR_ADC 195 187 #define RESET_PERIPHS_I2C_MASTER_0 196 188 #define RESET_SANA 197 189 /* 198 */ 190 #define RESET_PERIPHS_STREAM_INTERFACE 199 191 #define RESET_PERIPHS_SDIO 200 192 #define RESET_PERIPHS_UART_0 201 193 #define RESET_PERIPHS_UART_1_2 202 194 #define RESET_PERIPHS_ASYNC_0 203 195 #define RESET_PERIPHS_ASYNC_1 204 196 #define RESET_PERIPHS_SPI_0 205 197 #define RESET_PERIPHS_SDHC 206 198 #define RESET_UART_SLIP 207 199 /* 208-223 */ 200 /* RESET7 */ 201 #define RESET_USB_DDR_0 224 202 #define RESET_USB_DDR_1 225 203 #define RESET_USB_DDR_2 226 204 #define RESET_USB_DDR_3 227 205 /* 228 */ 206 #define RESET_DEVICE_MMC_ARB 229 207 /* 230 */ 208 #define RESET_VID_LOCK 231 209 #define RESET_A9_DMC_PIPEL 232 210 /* 233-255 */ 211 212 #endif 213
Indexes created Wed Oct 15 16:09:53 GMT 2025