Home | History | Annotate | Line # | Download | only in reset 
      1 /*	$NetBSD: amlogic,meson8b-reset.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
      4 /*
      5  * Copyright (c) 2016 BayLibre, SAS.
      6  * Author: Neil Armstrong <narmstrong (at) baylibre.com>
      7  */
      8 #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
      9 #define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
     10 
     11 /*	RESET0					*/
     12 #define RESET_HIU			0
     13 #define RESET_VLD			1
     14 #define RESET_IQIDCT			2
     15 #define RESET_MC			3
     16 /*					8	*/
     17 #define RESET_VIU			5
     18 #define RESET_AIU			6
     19 #define RESET_MCPU			7
     20 #define RESET_CCPU			8
     21 #define RESET_PMUX			9
     22 #define RESET_VENC			10
     23 #define RESET_ASSIST			11
     24 #define RESET_AFIFO2			12
     25 #define RESET_MDEC			13
     26 #define RESET_VLD_PART			14
     27 #define RESET_VIFIFO			15
     28 /*					16-31	*/
     29 /*	RESET1					*/
     30 /*					32	*/
     31 #define RESET_DEMUX			33
     32 #define RESET_USB_OTG			34
     33 #define RESET_DDR			35
     34 #define RESET_VDAC_1			36
     35 #define RESET_BT656			37
     36 #define RESET_AHB_SRAM			38
     37 #define RESET_AHB_BRIDGE		39
     38 #define RESET_PARSER			40
     39 #define RESET_BLKMV			41
     40 #define RESET_ISA			42
     41 #define RESET_ETHERNET			43
     42 #define RESET_ABUF			44
     43 #define RESET_AHB_DATA			45
     44 #define RESET_AHB_CNTL			46
     45 #define RESET_ROM_BOOT			47
     46 /*					48-63	*/
     47 /*	RESET2					*/
     48 #define RESET_VD_RMEM			64
     49 #define RESET_AUDIN			65
     50 #define RESET_DBLK			66
     51 #define RESET_PIC_DC			67
     52 #define RESET_PSC			68
     53 #define RESET_NAND			69
     54 #define RESET_GE2D			70
     55 #define RESET_PARSER_REG		71
     56 #define RESET_PARSER_FETCH		72
     57 #define RESET_PARSER_CTL		73
     58 #define RESET_PARSER_TOP		74
     59 #define RESET_HDMI_APB			75
     60 #define RESET_AUDIO_APB			76
     61 #define RESET_MEDIA_CPU			77
     62 #define RESET_MALI			78
     63 #define RESET_HDMI_SYSTEM_RESET		79
     64 /*					80-95	*/
     65 /*	RESET3					*/
     66 #define RESET_RING_OSCILLATOR		96
     67 #define RESET_SYS_CPU_0			97
     68 #define RESET_EFUSE			98
     69 #define RESET_SYS_CPU_BVCI		99
     70 #define RESET_AIFIFO			100
     71 #define RESET_AUDIO_PLL_MODULATOR	101
     72 #define RESET_AHB_BRIDGE_CNTL		102
     73 #define RESET_SYS_CPU_1			103
     74 #define RESET_AUDIO_DAC			104
     75 #define RESET_DEMUX_TOP			105
     76 #define RESET_DEMUX_DES			106
     77 #define RESET_DEMUX_S2P_0		107
     78 #define RESET_DEMUX_S2P_1		108
     79 #define RESET_DEMUX_RESET_0		109
     80 #define RESET_DEMUX_RESET_1		110
     81 #define RESET_DEMUX_RESET_2		111
     82 /*					112-127	*/
     83 /*	RESET4					*/
     84 #define RESET_PL310			128
     85 #define RESET_A5_APB			129
     86 #define RESET_A5_AXI			130
     87 #define RESET_A5			131
     88 #define RESET_DVIN			132
     89 #define RESET_RDMA			133
     90 #define RESET_VENCI			134
     91 #define RESET_VENCP			135
     92 #define RESET_VENCT			136
     93 #define RESET_VDAC_4			137
     94 #define RESET_RTC			138
     95 #define RESET_A5_DEBUG			139
     96 #define RESET_VDI6			140
     97 #define RESET_VENCL			141
     98 /*					142-159	*/
     99 /*	RESET5					*/
    100 #define RESET_DDR_PLL			160
    101 #define RESET_MISC_PLL			161
    102 #define RESET_SYS_PLL			162
    103 #define RESET_HPLL_PLL			163
    104 #define RESET_AUDIO_PLL			164
    105 #define RESET_VID2_PLL			165
    106 /*					166-191	*/
    107 /*	RESET6					*/
    108 #define RESET_PERIPHS_GENERAL		192
    109 #define RESET_PERIPHS_IR_REMOTE		193
    110 #define RESET_PERIPHS_SMART_CARD	194
    111 #define RESET_PERIPHS_SAR_ADC		195
    112 #define RESET_PERIPHS_I2C_MASTER_0	196
    113 #define RESET_PERIPHS_I2C_MASTER_1	197
    114 #define RESET_PERIPHS_I2C_SLAVE		198
    115 #define RESET_PERIPHS_STREAM_INTERFACE	199
    116 #define RESET_PERIPHS_SDIO		200
    117 #define RESET_PERIPHS_UART_0		201
    118 #define RESET_PERIPHS_UART_1		202
    119 #define RESET_PERIPHS_ASYNC_0		203
    120 #define RESET_PERIPHS_ASYNC_1		204
    121 #define RESET_PERIPHS_SPI_0		205
    122 #define RESET_PERIPHS_SPI_1		206
    123 #define RESET_PERIPHS_LED_PWM		207
    124 /*					208-223	*/
    125 /*	RESET7					*/
    126 /*					224-255	*/
    127 
    128 #endif
    129