1 /* $NetBSD: imx7-reset.h,v 1.1.1.3 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (C) 2017 Impinj, Inc. 6 * 7 * Author: Andrey Smirnov <andrew.smirnov (at) gmail.com> 8 */ 9 10 #ifndef DT_BINDING_RESET_IMX7_H 11 #define DT_BINDING_RESET_IMX7_H 12 13 #define IMX7_RESET_A7_CORE_POR_RESET0 0 14 #define IMX7_RESET_A7_CORE_POR_RESET1 1 15 #define IMX7_RESET_A7_CORE_RESET0 2 16 #define IMX7_RESET_A7_CORE_RESET1 3 17 #define IMX7_RESET_A7_DBG_RESET0 4 18 #define IMX7_RESET_A7_DBG_RESET1 5 19 #define IMX7_RESET_A7_ETM_RESET0 6 20 #define IMX7_RESET_A7_ETM_RESET1 7 21 #define IMX7_RESET_A7_SOC_DBG_RESET 8 22 #define IMX7_RESET_A7_L2RESET 9 23 #define IMX7_RESET_SW_M4C_RST 10 24 #define IMX7_RESET_SW_M4P_RST 11 25 #define IMX7_RESET_EIM_RST 12 26 #define IMX7_RESET_HSICPHY_PORT_RST 13 27 #define IMX7_RESET_USBPHY1_POR 14 28 #define IMX7_RESET_USBPHY1_PORT_RST 15 29 #define IMX7_RESET_USBPHY2_POR 16 30 #define IMX7_RESET_USBPHY2_PORT_RST 17 31 #define IMX7_RESET_MIPI_PHY_MRST 18 32 #define IMX7_RESET_MIPI_PHY_SRST 19 33 34 /* 35 * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 36 * and PCIEPHY_G_RST 37 */ 38 #define IMX7_RESET_PCIEPHY 20 39 #define IMX7_RESET_PCIEPHY_PERST 21 40 41 /* 42 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 43 * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 44 * of as one 45 */ 46 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 47 #define IMX7_RESET_DDRC_PRST 23 48 #define IMX7_RESET_DDRC_CORE_RST 24 49 50 #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 51 52 #define IMX7_RESET_NUM 26 53 54 #endif 55 56
Indexes created Thu Sep 25 08:09:54 GMT 2025