1/*	$NetBSD: imx8ulp-pcc-reset.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0-only */
4/*
5 * Copyright 2021 NXP
6 */
7
8#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
9#define DT_BINDING_PCC_RESET_IMX8ULP_H
10
11/* PCC3 */
12#define PCC3_WDOG3_SWRST	0
13#define PCC3_WDOG4_SWRST	1
14#define PCC3_LPIT1_SWRST	2
15#define PCC3_TPM4_SWRST		3
16#define PCC3_TPM5_SWRST		4
17#define PCC3_FLEXIO1_SWRST	5
18#define PCC3_I3C2_SWRST		6
19#define PCC3_LPI2C4_SWRST	7
20#define PCC3_LPI2C5_SWRST	8
21#define PCC3_LPUART4_SWRST	9
22#define PCC3_LPUART5_SWRST	10
23#define PCC3_LPSPI4_SWRST	11
24#define PCC3_LPSPI5_SWRST	12
25
26/* PCC4 */
27#define PCC4_FLEXSPI2_SWRST	0
28#define PCC4_TPM6_SWRST		1
29#define PCC4_TPM7_SWRST		2
30#define PCC4_LPI2C6_SWRST	3
31#define PCC4_LPI2C7_SWRST	4
32#define PCC4_LPUART6_SWRST	5
33#define PCC4_LPUART7_SWRST	6
34#define PCC4_SAI4_SWRST		7
35#define PCC4_SAI5_SWRST		8
36#define PCC4_USDHC0_SWRST	9
37#define PCC4_USDHC1_SWRST	10
38#define PCC4_USDHC2_SWRST	11
39#define PCC4_USB0_SWRST		12
40#define PCC4_USB0_PHY_SWRST	13
41#define PCC4_USB1_SWRST		14
42#define PCC4_USB1_PHY_SWRST	15
43#define PCC4_ENET_SWRST		16
44
45/* PCC5 */
46#define PCC5_TPM8_SWRST		0
47#define PCC5_SAI6_SWRST		1
48#define PCC5_SAI7_SWRST		2
49#define PCC5_SPDIF_SWRST	3
50#define PCC5_ISI_SWRST		4
51#define PCC5_CSI_REGS_SWRST	5
52#define PCC5_CSI_SWRST		6
53#define PCC5_DSI_SWRST		7
54#define PCC5_WDOG5_SWRST	8
55#define PCC5_EPDC_SWRST		9
56#define PCC5_PXP_SWRST		10
57#define PCC5_GPU2D_SWRST	11
58#define PCC5_GPU3D_SWRST	12
59#define PCC5_DC_NANO_SWRST	13
60
61#endif /*DT_BINDING_RESET_IMX8ULP_H */
62