1/* $NetBSD: mediatek,mt6795-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2022 Collabora Ltd. 6 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7 */ 8 9#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 10#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 11 12/* INFRACFG resets */ 13#define MT6795_INFRA_RST0_SCPSYS_RST 0 14#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1 15#define MT6795_INFRA_RST1_MIPI_DSI_RST 2 16#define MT6795_INFRA_RST1_MIPI_CSI_RST 3 17#define MT6795_INFRA_RST1_MM_IOMMU_RST 4 18 19/* MMSYS resets */ 20#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 21#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 22#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 23#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 24#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 25#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 26#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 27#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 28#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 29#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 30#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 31#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 32#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 33#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 34 35/* PERICFG resets */ 36#define MT6795_PERI_NFI_SW_RST 0 37#define MT6795_PERI_THERM_SW_RST 1 38#define MT6795_PERI_MSDC1_SW_RST 2 39 40/* TOPRGU resets */ 41#define MT6795_TOPRGU_INFRA_SW_RST 0 42#define MT6795_TOPRGU_MM_SW_RST 1 43#define MT6795_TOPRGU_MFG_SW_RST 2 44#define MT6795_TOPRGU_VENC_SW_RST 3 45#define MT6795_TOPRGU_VDEC_SW_RST 4 46#define MT6795_TOPRGU_IMG_SW_RST 5 47#define MT6795_TOPRGU_DDRPHY_SW_RST 6 48#define MT6795_TOPRGU_MD_SW_RST 7 49#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 50#define MT6795_TOPRGU_MD_LITE_SW_RST 9 51#define MT6795_TOPRGU_APMIXED_SW_RST 10 52#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 53#define MT6795_TOPRGU_SW_RST_NUM 12 54 55#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */ 56