1/* $NetBSD: mt7986-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 4/* 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Sam Shih <sam.shih@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 10#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 11 12/* INFRACFG resets */ 13#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 14#define MT7986_INFRACFG_SSUSB_SW_RST 7 15#define MT7986_INFRACFG_EIP97_SW_RST 8 16#define MT7986_INFRACFG_AUDIO_SW_RST 13 17#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 18 19#define MT7986_INFRACFG_TRNG_SW_RST 17 20#define MT7986_INFRACFG_AP_DMA_SW_RST 32 21#define MT7986_INFRACFG_I2C_SW_RST 33 22#define MT7986_INFRACFG_NFI_SW_RST 34 23#define MT7986_INFRACFG_SPI0_SW_RST 35 24#define MT7986_INFRACFG_SPI1_SW_RST 36 25#define MT7986_INFRACFG_UART0_SW_RST 37 26#define MT7986_INFRACFG_UART1_SW_RST 38 27#define MT7986_INFRACFG_UART2_SW_RST 39 28#define MT7986_INFRACFG_AUXADC_SW_RST 43 29 30#define MT7986_INFRACFG_APXGPT_SW_RST 66 31#define MT7986_INFRACFG_PWM_SW_RST 68 32 33#define MT7986_INFRACFG_SW_RST_NUM 69 34 35/* TOPRGU resets */ 36#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 37#define MT7986_TOPRGU_SGMII0_SW_RST 1 38#define MT7986_TOPRGU_SGMII1_SW_RST 2 39#define MT7986_TOPRGU_INFRA_SW_RST 3 40#define MT7986_TOPRGU_U2PHY_SW_RST 5 41#define MT7986_TOPRGU_PCIE_SW_RST 6 42#define MT7986_TOPRGU_SSUSB_SW_RST 7 43#define MT7986_TOPRGU_ETHDMA_SW_RST 20 44#define MT7986_TOPRGU_CONSYS_SW_RST 23 45 46#define MT7986_TOPRGU_SW_RST_NUM 24 47 48/* ETHSYS Subsystem resets */ 49#define MT7986_ETHSYS_FE_SW_RST 6 50#define MT7986_ETHSYS_PMTR_SW_RST 8 51#define MT7986_ETHSYS_GMAC_SW_RST 23 52#define MT7986_ETHSYS_PPE0_SW_RST 30 53#define MT7986_ETHSYS_PPE1_SW_RST 31 54 55#define MT7986_ETHSYS_SW_RST_NUM 32 56 57#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ 58