1/* $NetBSD: nuvoton,ma35d1-reset.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (C) 2023 Nuvoton Technologies. 6 * Author: Chi-Fen Li <cfli0@nuvoton.com> 7 * 8 * Device Tree binding constants for MA35D1 reset controller. 9 */ 10 11#ifndef __DT_BINDINGS_RESET_MA35D1_H 12#define __DT_BINDINGS_RESET_MA35D1_H 13 14#define MA35D1_RESET_CHIP 0 15#define MA35D1_RESET_CA35CR0 1 16#define MA35D1_RESET_CA35CR1 2 17#define MA35D1_RESET_CM4 3 18#define MA35D1_RESET_PDMA0 4 19#define MA35D1_RESET_PDMA1 5 20#define MA35D1_RESET_PDMA2 6 21#define MA35D1_RESET_PDMA3 7 22#define MA35D1_RESET_DISP 8 23#define MA35D1_RESET_VCAP0 9 24#define MA35D1_RESET_VCAP1 10 25#define MA35D1_RESET_GFX 11 26#define MA35D1_RESET_VDEC 12 27#define MA35D1_RESET_WHC0 13 28#define MA35D1_RESET_WHC1 14 29#define MA35D1_RESET_GMAC0 15 30#define MA35D1_RESET_GMAC1 16 31#define MA35D1_RESET_HWSEM 17 32#define MA35D1_RESET_EBI 18 33#define MA35D1_RESET_HSUSBH0 19 34#define MA35D1_RESET_HSUSBH1 20 35#define MA35D1_RESET_HSUSBD 21 36#define MA35D1_RESET_USBHL 22 37#define MA35D1_RESET_SDH0 23 38#define MA35D1_RESET_SDH1 24 39#define MA35D1_RESET_NAND 25 40#define MA35D1_RESET_GPIO 26 41#define MA35D1_RESET_MCTLP 27 42#define MA35D1_RESET_MCTLC 28 43#define MA35D1_RESET_DDRPUB 29 44#define MA35D1_RESET_TMR0 30 45#define MA35D1_RESET_TMR1 31 46#define MA35D1_RESET_TMR2 32 47#define MA35D1_RESET_TMR3 33 48#define MA35D1_RESET_I2C0 34 49#define MA35D1_RESET_I2C1 35 50#define MA35D1_RESET_I2C2 36 51#define MA35D1_RESET_I2C3 37 52#define MA35D1_RESET_QSPI0 38 53#define MA35D1_RESET_SPI0 39 54#define MA35D1_RESET_SPI1 40 55#define MA35D1_RESET_SPI2 41 56#define MA35D1_RESET_UART0 42 57#define MA35D1_RESET_UART1 43 58#define MA35D1_RESET_UART2 44 59#define MA35D1_RESET_UART3 45 60#define MA35D1_RESET_UART4 46 61#define MA35D1_RESET_UART5 47 62#define MA35D1_RESET_UART6 48 63#define MA35D1_RESET_UART7 49 64#define MA35D1_RESET_CANFD0 50 65#define MA35D1_RESET_CANFD1 51 66#define MA35D1_RESET_EADC0 52 67#define MA35D1_RESET_I2S0 53 68#define MA35D1_RESET_SC0 54 69#define MA35D1_RESET_SC1 55 70#define MA35D1_RESET_QSPI1 56 71#define MA35D1_RESET_SPI3 57 72#define MA35D1_RESET_EPWM0 58 73#define MA35D1_RESET_EPWM1 59 74#define MA35D1_RESET_QEI0 60 75#define MA35D1_RESET_QEI1 61 76#define MA35D1_RESET_ECAP0 62 77#define MA35D1_RESET_ECAP1 63 78#define MA35D1_RESET_CANFD2 64 79#define MA35D1_RESET_ADC0 65 80#define MA35D1_RESET_TMR4 66 81#define MA35D1_RESET_TMR5 67 82#define MA35D1_RESET_TMR6 68 83#define MA35D1_RESET_TMR7 69 84#define MA35D1_RESET_TMR8 70 85#define MA35D1_RESET_TMR9 71 86#define MA35D1_RESET_TMR10 72 87#define MA35D1_RESET_TMR11 73 88#define MA35D1_RESET_UART8 74 89#define MA35D1_RESET_UART9 75 90#define MA35D1_RESET_UART10 76 91#define MA35D1_RESET_UART11 77 92#define MA35D1_RESET_UART12 78 93#define MA35D1_RESET_UART13 79 94#define MA35D1_RESET_UART14 80 95#define MA35D1_RESET_UART15 81 96#define MA35D1_RESET_UART16 82 97#define MA35D1_RESET_I2S1 83 98#define MA35D1_RESET_I2C4 84 99#define MA35D1_RESET_I2C5 85 100#define MA35D1_RESET_EPWM2 86 101#define MA35D1_RESET_ECAP2 87 102#define MA35D1_RESET_QEI2 88 103#define MA35D1_RESET_CANFD3 89 104#define MA35D1_RESET_KPI 90 105#define MA35D1_RESET_GIC 91 106#define MA35D1_RESET_SSMCC 92 107#define MA35D1_RESET_SSPCC 93 108#define MA35D1_RESET_COUNT 94 109 110#endif 111