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      1 /*	$NetBSD: qcom,gcc-msm8974.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H
      9 #define _DT_BINDINGS_RESET_MSM_GCC_8974_H
     10 
     11 #define GCC_SYSTEM_NOC_BCR			0
     12 #define GCC_CONFIG_NOC_BCR			1
     13 #define GCC_PERIPH_NOC_BCR			2
     14 #define GCC_IMEM_BCR				3
     15 #define GCC_MMSS_BCR				4
     16 #define GCC_QDSS_BCR				5
     17 #define GCC_USB_30_BCR				6
     18 #define GCC_USB3_PHY_BCR			7
     19 #define GCC_USB_HS_HSIC_BCR			8
     20 #define GCC_USB_HS_BCR				9
     21 #define GCC_USB2A_PHY_BCR			10
     22 #define GCC_USB2B_PHY_BCR			11
     23 #define GCC_SDCC1_BCR				12
     24 #define GCC_SDCC2_BCR				13
     25 #define GCC_SDCC3_BCR				14
     26 #define GCC_SDCC4_BCR				15
     27 #define GCC_BLSP1_BCR				16
     28 #define GCC_BLSP1_QUP1_BCR			17
     29 #define GCC_BLSP1_UART1_BCR			18
     30 #define GCC_BLSP1_QUP2_BCR			19
     31 #define GCC_BLSP1_UART2_BCR			20
     32 #define GCC_BLSP1_QUP3_BCR			21
     33 #define GCC_BLSP1_UART3_BCR			22
     34 #define GCC_BLSP1_QUP4_BCR			23
     35 #define GCC_BLSP1_UART4_BCR			24
     36 #define GCC_BLSP1_QUP5_BCR			25
     37 #define GCC_BLSP1_UART5_BCR			26
     38 #define GCC_BLSP1_QUP6_BCR			27
     39 #define GCC_BLSP1_UART6_BCR			28
     40 #define GCC_BLSP2_BCR				29
     41 #define GCC_BLSP2_QUP1_BCR			30
     42 #define GCC_BLSP2_UART1_BCR			31
     43 #define GCC_BLSP2_QUP2_BCR			32
     44 #define GCC_BLSP2_UART2_BCR			33
     45 #define GCC_BLSP2_QUP3_BCR			34
     46 #define GCC_BLSP2_UART3_BCR			35
     47 #define GCC_BLSP2_QUP4_BCR			36
     48 #define GCC_BLSP2_UART4_BCR			37
     49 #define GCC_BLSP2_QUP5_BCR			38
     50 #define GCC_BLSP2_UART5_BCR			39
     51 #define GCC_BLSP2_QUP6_BCR			40
     52 #define GCC_BLSP2_UART6_BCR			41
     53 #define GCC_PDM_BCR				42
     54 #define GCC_BAM_DMA_BCR				43
     55 #define GCC_TSIF_BCR				44
     56 #define GCC_TCSR_BCR				45
     57 #define GCC_BOOT_ROM_BCR			46
     58 #define GCC_MSG_RAM_BCR				47
     59 #define GCC_TLMM_BCR				48
     60 #define GCC_MPM_BCR				49
     61 #define GCC_SEC_CTRL_BCR			50
     62 #define GCC_SPMI_BCR				51
     63 #define GCC_SPDM_BCR				52
     64 #define GCC_CE1_BCR				53
     65 #define GCC_CE2_BCR				54
     66 #define GCC_BIMC_BCR				55
     67 #define GCC_MPM_NON_AHB_RESET			56
     68 #define GCC_MPM_AHB_RESET			57
     69 #define GCC_SNOC_BUS_TIMEOUT0_BCR		58
     70 #define GCC_SNOC_BUS_TIMEOUT2_BCR		59
     71 #define GCC_PNOC_BUS_TIMEOUT0_BCR		60
     72 #define GCC_PNOC_BUS_TIMEOUT1_BCR		61
     73 #define GCC_PNOC_BUS_TIMEOUT2_BCR		62
     74 #define GCC_PNOC_BUS_TIMEOUT3_BCR		63
     75 #define GCC_PNOC_BUS_TIMEOUT4_BCR		64
     76 #define GCC_CNOC_BUS_TIMEOUT0_BCR		65
     77 #define GCC_CNOC_BUS_TIMEOUT1_BCR		66
     78 #define GCC_CNOC_BUS_TIMEOUT2_BCR		67
     79 #define GCC_CNOC_BUS_TIMEOUT3_BCR		68
     80 #define GCC_CNOC_BUS_TIMEOUT4_BCR		69
     81 #define GCC_CNOC_BUS_TIMEOUT5_BCR		70
     82 #define GCC_CNOC_BUS_TIMEOUT6_BCR		71
     83 #define GCC_DEHR_BCR				72
     84 #define GCC_RBCPR_BCR				73
     85 #define GCC_MSS_RESTART				74
     86 #define GCC_LPASS_RESTART			75
     87 #define GCC_WCSS_RESTART			76
     88 #define GCC_VENUS_RESTART			77
     89 
     90 #endif
     91