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      1  1.1  jmcneill /*	$NetBSD: realtek,rtd1195.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2  1.1  jmcneill 
      3  1.1  jmcneill /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
      4  1.1  jmcneill /*
      5  1.1  jmcneill  * Realtek RTD1195 reset controllers
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Copyright (c) 2017 Andreas Frber
      8  1.1  jmcneill  */
      9  1.1  jmcneill #ifndef DT_BINDINGS_RESET_RTD1195_H
     10  1.1  jmcneill #define DT_BINDINGS_RESET_RTD1195_H
     11  1.1  jmcneill 
     12  1.1  jmcneill /* soft reset 1 */
     13  1.1  jmcneill #define RTD1195_RSTN_MISC		0
     14  1.1  jmcneill #define RTD1195_RSTN_RNG		1
     15  1.1  jmcneill #define RTD1195_RSTN_USB3_POW		2
     16  1.1  jmcneill #define RTD1195_RSTN_GSPI		3
     17  1.1  jmcneill #define RTD1195_RSTN_USB3_P0_MDIO	4
     18  1.1  jmcneill #define RTD1195_RSTN_VE_H265		5
     19  1.1  jmcneill #define RTD1195_RSTN_USB		6
     20  1.1  jmcneill #define RTD1195_RSTN_USB_PHY0		8
     21  1.1  jmcneill #define RTD1195_RSTN_USB_PHY1		9
     22  1.1  jmcneill #define RTD1195_RSTN_HDMIRX		11
     23  1.1  jmcneill #define RTD1195_RSTN_HDMI		12
     24  1.1  jmcneill #define RTD1195_RSTN_ETN		14
     25  1.1  jmcneill #define RTD1195_RSTN_AIO		15
     26  1.1  jmcneill #define RTD1195_RSTN_GPU		16
     27  1.1  jmcneill #define RTD1195_RSTN_VE_H264		17
     28  1.1  jmcneill #define RTD1195_RSTN_VE_JPEG		18
     29  1.1  jmcneill #define RTD1195_RSTN_TVE		19
     30  1.1  jmcneill #define RTD1195_RSTN_VO			20
     31  1.1  jmcneill #define RTD1195_RSTN_LVDS		21
     32  1.1  jmcneill #define RTD1195_RSTN_SE			22
     33  1.1  jmcneill #define RTD1195_RSTN_DCU		23
     34  1.1  jmcneill #define RTD1195_RSTN_DC_PHY		24
     35  1.1  jmcneill #define RTD1195_RSTN_CP			25
     36  1.1  jmcneill #define RTD1195_RSTN_MD			26
     37  1.1  jmcneill #define RTD1195_RSTN_TP			27
     38  1.1  jmcneill #define RTD1195_RSTN_AE			28
     39  1.1  jmcneill #define RTD1195_RSTN_NF			29
     40  1.1  jmcneill #define RTD1195_RSTN_MIPI		30
     41  1.1  jmcneill 
     42  1.1  jmcneill /* soft reset 2 */
     43  1.1  jmcneill #define RTD1195_RSTN_ACPU		0
     44  1.1  jmcneill #define RTD1195_RSTN_VCPU		1
     45  1.1  jmcneill #define RTD1195_RSTN_PCR		9
     46  1.1  jmcneill #define RTD1195_RSTN_CR			10
     47  1.1  jmcneill #define RTD1195_RSTN_EMMC		11
     48  1.1  jmcneill #define RTD1195_RSTN_SDIO		12
     49  1.1  jmcneill #define RTD1195_RSTN_I2C_5		18
     50  1.1  jmcneill #define RTD1195_RSTN_RTC		20
     51  1.1  jmcneill #define RTD1195_RSTN_I2C_4		23
     52  1.1  jmcneill #define RTD1195_RSTN_I2C_3		24
     53  1.1  jmcneill #define RTD1195_RSTN_I2C_2		25
     54  1.1  jmcneill #define RTD1195_RSTN_I2C_1		26
     55  1.1  jmcneill #define RTD1195_RSTN_UR1		28
     56  1.1  jmcneill 
     57  1.1  jmcneill /* soft reset 3 */
     58  1.1  jmcneill #define RTD1195_RSTN_SB2		0
     59  1.1  jmcneill 
     60  1.1  jmcneill /* iso soft reset */
     61  1.1  jmcneill #define RTD1195_ISO_RSTN_VFD		0
     62  1.1  jmcneill #define RTD1195_ISO_RSTN_IR		1
     63  1.1  jmcneill #define RTD1195_ISO_RSTN_CEC0		2
     64  1.1  jmcneill #define RTD1195_ISO_RSTN_CEC1		3
     65  1.1  jmcneill #define RTD1195_ISO_RSTN_DP		4
     66  1.1  jmcneill #define RTD1195_ISO_RSTN_CBUSTX		5
     67  1.1  jmcneill #define RTD1195_ISO_RSTN_CBUSRX		6
     68  1.1  jmcneill #define RTD1195_ISO_RSTN_EFUSE		7
     69  1.1  jmcneill #define RTD1195_ISO_RSTN_UR0		8
     70  1.1  jmcneill #define RTD1195_ISO_RSTN_GMAC		9
     71  1.1  jmcneill #define RTD1195_ISO_RSTN_GPHY		10
     72  1.1  jmcneill #define RTD1195_ISO_RSTN_I2C_0		11
     73  1.1  jmcneill #define RTD1195_ISO_RSTN_I2C_6		12
     74  1.1  jmcneill #define RTD1195_ISO_RSTN_CBUS		13
     75  1.1  jmcneill 
     76  1.1  jmcneill #endif
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