1/* $NetBSD: rockchip,rk3576-cru.h,v 1.1.1.1 2026/01/18 05:21:55 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 4/* 5 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 6 * Copyright (c) 2024 Collabora Ltd. 7 * 8 * Author: Elaine Zhang <zhangqing@rock-chips.com> 9 * Author: Detlev Casanova <detlev.casanova@collabora.com> 10 */ 11 12#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H 13#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H 14 15#define SRST_A_TOP_BIU 0 16#define SRST_P_TOP_BIU 1 17#define SRST_A_TOP_MID_BIU 2 18#define SRST_A_SECURE_HIGH_BIU 3 19#define SRST_H_TOP_BIU 4 20 21#define SRST_H_VO0VOP_CHANNEL_BIU 5 22#define SRST_A_VO0VOP_CHANNEL_BIU 6 23 24#define SRST_BISRINTF 7 25 26#define SRST_H_AUDIO_BIU 8 27#define SRST_H_ASRC_2CH_0 9 28#define SRST_H_ASRC_2CH_1 10 29#define SRST_H_ASRC_4CH_0 11 30#define SRST_H_ASRC_4CH_1 12 31#define SRST_ASRC_2CH_0 13 32#define SRST_ASRC_2CH_1 14 33#define SRST_ASRC_4CH_0 15 34#define SRST_ASRC_4CH_1 16 35#define SRST_M_SAI0_8CH 17 36#define SRST_H_SAI0_8CH 18 37#define SRST_H_SPDIF_RX0 19 38#define SRST_M_SPDIF_RX0 20 39 40#define SRST_H_SPDIF_RX1 21 41#define SRST_M_SPDIF_RX1 22 42#define SRST_M_SAI1_8CH 23 43#define SRST_H_SAI1_8CH 24 44#define SRST_M_SAI2_2CH 25 45#define SRST_H_SAI2_2CH 26 46#define SRST_M_SAI3_2CH 27 47#define SRST_H_SAI3_2CH 28 48 49#define SRST_M_SAI4_2CH 29 50#define SRST_H_SAI4_2CH 30 51#define SRST_H_ACDCDIG_DSM 31 52#define SRST_M_ACDCDIG_DSM 32 53#define SRST_PDM1 33 54#define SRST_H_PDM1 34 55#define SRST_M_PDM1 35 56#define SRST_H_SPDIF_TX0 36 57#define SRST_M_SPDIF_TX0 37 58#define SRST_H_SPDIF_TX1 38 59#define SRST_M_SPDIF_TX1 39 60 61#define SRST_A_BUS_BIU 40 62#define SRST_P_BUS_BIU 41 63#define SRST_P_CRU 42 64#define SRST_H_CAN0 43 65#define SRST_CAN0 44 66#define SRST_H_CAN1 45 67#define SRST_CAN1 46 68#define SRST_P_INTMUX2BUS 47 69#define SRST_P_VCCIO_IOC 48 70#define SRST_H_BUS_BIU 49 71#define SRST_KEY_SHIFT 50 72 73#define SRST_P_I2C1 51 74#define SRST_P_I2C2 52 75#define SRST_P_I2C3 53 76#define SRST_P_I2C4 54 77#define SRST_P_I2C5 55 78#define SRST_P_I2C6 56 79#define SRST_P_I2C7 57 80#define SRST_P_I2C8 58 81#define SRST_P_I2C9 59 82#define SRST_P_WDT_BUSMCU 60 83#define SRST_T_WDT_BUSMCU 61 84#define SRST_A_GIC 62 85#define SRST_I2C1 63 86#define SRST_I2C2 64 87#define SRST_I2C3 65 88#define SRST_I2C4 66 89 90#define SRST_I2C5 67 91#define SRST_I2C6 68 92#define SRST_I2C7 69 93#define SRST_I2C8 70 94#define SRST_I2C9 71 95#define SRST_P_SARADC 72 96#define SRST_SARADC 73 97#define SRST_P_TSADC 74 98#define SRST_TSADC 75 99#define SRST_P_UART0 76 100#define SRST_P_UART2 77 101#define SRST_P_UART3 78 102#define SRST_P_UART4 79 103#define SRST_P_UART5 80 104#define SRST_P_UART6 81 105 106#define SRST_P_UART7 82 107#define SRST_P_UART8 83 108#define SRST_P_UART9 84 109#define SRST_P_UART10 85 110#define SRST_P_UART11 86 111#define SRST_S_UART0 87 112#define SRST_S_UART2 88 113#define SRST_S_UART3 89 114#define SRST_S_UART4 90 115#define SRST_S_UART5 91 116 117#define SRST_S_UART6 92 118#define SRST_S_UART7 93 119#define SRST_S_UART8 94 120#define SRST_S_UART9 95 121#define SRST_S_UART10 96 122#define SRST_S_UART11 97 123#define SRST_P_SPI0 98 124#define SRST_P_SPI1 99 125#define SRST_P_SPI2 100 126 127#define SRST_P_SPI3 101 128#define SRST_P_SPI4 102 129#define SRST_SPI0 103 130#define SRST_SPI1 104 131#define SRST_SPI2 105 132#define SRST_SPI3 106 133#define SRST_SPI4 107 134#define SRST_P_WDT0 108 135#define SRST_T_WDT0 109 136#define SRST_P_SYS_GRF 110 137#define SRST_P_PWM1 111 138#define SRST_PWM1 112 139 140#define SRST_P_BUSTIMER0 113 141#define SRST_P_BUSTIMER1 114 142#define SRST_TIMER0 115 143#define SRST_TIMER1 116 144#define SRST_TIMER2 117 145#define SRST_TIMER3 118 146#define SRST_TIMER4 119 147#define SRST_TIMER5 120 148#define SRST_P_BUSIOC 121 149#define SRST_P_MAILBOX0 122 150#define SRST_P_GPIO1 123 151 152#define SRST_GPIO1 124 153#define SRST_P_GPIO2 125 154#define SRST_GPIO2 126 155#define SRST_P_GPIO3 127 156#define SRST_GPIO3 128 157#define SRST_P_GPIO4 129 158#define SRST_GPIO4 130 159#define SRST_A_DECOM 131 160#define SRST_P_DECOM 132 161#define SRST_D_DECOM 133 162#define SRST_TIMER6 134 163#define SRST_TIMER7 135 164#define SRST_TIMER8 136 165#define SRST_TIMER9 137 166#define SRST_TIMER10 138 167 168#define SRST_TIMER11 139 169#define SRST_A_DMAC0 140 170#define SRST_A_DMAC1 141 171#define SRST_A_DMAC2 142 172#define SRST_A_SPINLOCK 143 173#define SRST_REF_PVTPLL_BUS 144 174#define SRST_H_I3C0 145 175#define SRST_H_I3C1 146 176#define SRST_H_BUS_CM0_BIU 147 177#define SRST_F_BUS_CM0_CORE 148 178#define SRST_T_BUS_CM0_JTAG 149 179 180#define SRST_P_INTMUX2PMU 150 181#define SRST_P_INTMUX2DDR 151 182#define SRST_P_PVTPLL_BUS 152 183#define SRST_P_PWM2 153 184#define SRST_PWM2 154 185#define SRST_FREQ_PWM1 155 186#define SRST_COUNTER_PWM1 156 187#define SRST_I3C0 157 188#define SRST_I3C1 158 189 190#define SRST_P_DDR_MON_CH0 159 191#define SRST_P_DDR_BIU 160 192#define SRST_P_DDR_UPCTL_CH0 161 193#define SRST_TM_DDR_MON_CH0 162 194#define SRST_A_DDR_BIU 163 195#define SRST_DFI_CH0 164 196#define SRST_DDR_MON_CH0 165 197#define SRST_P_DDR_HWLP_CH0 166 198#define SRST_P_DDR_MON_CH1 167 199#define SRST_P_DDR_HWLP_CH1 168 200 201#define SRST_P_DDR_UPCTL_CH1 169 202#define SRST_TM_DDR_MON_CH1 170 203#define SRST_DFI_CH1 171 204#define SRST_A_DDR01_MSCH0 172 205#define SRST_A_DDR01_MSCH1 173 206#define SRST_DDR_MON_CH1 174 207#define SRST_DDR_SCRAMBLE_CH0 175 208#define SRST_DDR_SCRAMBLE_CH1 176 209#define SRST_P_AHB2APB 177 210#define SRST_H_AHB2APB 178 211#define SRST_H_DDR_BIU 179 212#define SRST_F_DDR_CM0_CORE 180 213 214#define SRST_P_DDR01_MSCH0 181 215#define SRST_P_DDR01_MSCH1 182 216#define SRST_DDR_TIMER0 183 217#define SRST_DDR_TIMER1 184 218#define SRST_T_WDT_DDR 185 219#define SRST_P_WDT 186 220#define SRST_P_TIMER 187 221#define SRST_T_DDR_CM0_JTAG 188 222#define SRST_P_DDR_GRF 189 223 224#define SRST_DDR_UPCTL_CH0 190 225#define SRST_A_DDR_UPCTL_0_CH0 191 226#define SRST_A_DDR_UPCTL_1_CH0 192 227#define SRST_A_DDR_UPCTL_2_CH0 193 228#define SRST_A_DDR_UPCTL_3_CH0 194 229#define SRST_A_DDR_UPCTL_4_CH0 195 230 231#define SRST_DDR_UPCTL_CH1 196 232#define SRST_A_DDR_UPCTL_0_CH1 197 233#define SRST_A_DDR_UPCTL_1_CH1 198 234#define SRST_A_DDR_UPCTL_2_CH1 199 235#define SRST_A_DDR_UPCTL_3_CH1 200 236#define SRST_A_DDR_UPCTL_4_CH1 201 237 238#define SRST_REF_PVTPLL_DDR 202 239#define SRST_P_PVTPLL_DDR 203 240 241#define SRST_A_RKNN0 204 242#define SRST_A_RKNN0_BIU 205 243#define SRST_L_RKNN0_BIU 206 244 245#define SRST_A_RKNN1 207 246#define SRST_A_RKNN1_BIU 208 247#define SRST_L_RKNN1_BIU 209 248 249#define SRST_NPU_DAP 210 250#define SRST_L_NPUSUBSYS_BIU 211 251#define SRST_P_NPUTOP_BIU 212 252#define SRST_P_NPU_TIMER 213 253#define SRST_NPUTIMER0 214 254#define SRST_NPUTIMER1 215 255#define SRST_P_NPU_WDT 216 256#define SRST_T_NPU_WDT 217 257 258#define SRST_A_RKNN_CBUF 218 259#define SRST_A_RVCORE0 219 260#define SRST_P_NPU_GRF 220 261#define SRST_P_PVTPLL_NPU 221 262#define SRST_NPU_PVTPLL 222 263#define SRST_H_NPU_CM0_BIU 223 264#define SRST_F_NPU_CM0_CORE 224 265#define SRST_T_NPU_CM0_JTAG 225 266#define SRST_A_RKNNTOP_BIU 226 267#define SRST_H_RKNN_CBUF 227 268#define SRST_H_RKNNTOP_BIU 228 269 270#define SRST_H_NVM_BIU 229 271#define SRST_A_NVM_BIU 230 272#define SRST_S_FSPI 231 273#define SRST_H_FSPI 232 274#define SRST_C_EMMC 233 275#define SRST_H_EMMC 234 276#define SRST_A_EMMC 235 277#define SRST_B_EMMC 236 278#define SRST_T_EMMC 237 279 280#define SRST_P_GRF 238 281#define SRST_P_PHP_BIU 239 282#define SRST_A_PHP_BIU 240 283#define SRST_P_PCIE0 241 284#define SRST_PCIE0_POWER_UP 242 285 286#define SRST_A_USB3OTG1 243 287#define SRST_A_MMU0 244 288#define SRST_A_SLV_MMU0 245 289#define SRST_A_MMU1 246 290 291#define SRST_A_SLV_MMU1 247 292#define SRST_P_PCIE1 248 293#define SRST_PCIE1_POWER_UP 249 294 295#define SRST_RXOOB0 250 296#define SRST_RXOOB1 251 297#define SRST_PMALIVE0 252 298#define SRST_PMALIVE1 253 299#define SRST_A_SATA0 254 300#define SRST_A_SATA1 255 301#define SRST_ASIC1 256 302#define SRST_ASIC0 257 303 304#define SRST_P_CSIDPHY1 258 305#define SRST_SCAN_CSIDPHY1 259 306 307#define SRST_P_SDGMAC_GRF 260 308#define SRST_P_SDGMAC_BIU 261 309#define SRST_A_SDGMAC_BIU 262 310#define SRST_H_SDGMAC_BIU 263 311#define SRST_A_GMAC0 264 312#define SRST_A_GMAC1 265 313#define SRST_P_GMAC0 266 314#define SRST_P_GMAC1 267 315#define SRST_H_SDIO 268 316 317#define SRST_H_SDMMC0 269 318#define SRST_S_FSPI1 270 319#define SRST_H_FSPI1 271 320#define SRST_A_DSMC_BIU 272 321#define SRST_A_DSMC 273 322#define SRST_P_DSMC 274 323#define SRST_H_HSGPIO 275 324#define SRST_HSGPIO 276 325#define SRST_A_HSGPIO 277 326 327#define SRST_H_RKVDEC 278 328#define SRST_H_RKVDEC_BIU 279 329#define SRST_A_RKVDEC_BIU 280 330#define SRST_RKVDEC_HEVC_CA 281 331#define SRST_RKVDEC_CORE 282 332 333#define SRST_A_USB_BIU 283 334#define SRST_P_USBUFS_BIU 284 335#define SRST_A_USB3OTG0 285 336#define SRST_A_UFS_BIU 286 337#define SRST_A_MMU2 287 338#define SRST_A_SLV_MMU2 288 339#define SRST_A_UFS_SYS 289 340 341#define SRST_A_UFS 290 342#define SRST_P_USBUFS_GRF 291 343#define SRST_P_UFS_GRF 292 344 345#define SRST_H_VPU_BIU 293 346#define SRST_A_JPEG_BIU 294 347#define SRST_A_RGA_BIU 295 348#define SRST_A_VDPP_BIU 296 349#define SRST_A_EBC_BIU 297 350#define SRST_H_RGA2E_0 298 351#define SRST_A_RGA2E_0 299 352#define SRST_CORE_RGA2E_0 300 353 354#define SRST_A_JPEG 301 355#define SRST_H_JPEG 302 356#define SRST_H_VDPP 303 357#define SRST_A_VDPP 304 358#define SRST_CORE_VDPP 305 359#define SRST_H_RGA2E_1 306 360#define SRST_A_RGA2E_1 307 361#define SRST_CORE_RGA2E_1 308 362#define SRST_H_EBC 309 363#define SRST_A_EBC 310 364#define SRST_D_EBC 311 365 366#define SRST_H_VEPU0_BIU 312 367#define SRST_A_VEPU0_BIU 313 368#define SRST_H_VEPU0 314 369#define SRST_A_VEPU0 315 370#define SRST_VEPU0_CORE 316 371 372#define SRST_A_VI_BIU 317 373#define SRST_H_VI_BIU 318 374#define SRST_P_VI_BIU 319 375#define SRST_D_VICAP 320 376#define SRST_A_VICAP 321 377#define SRST_H_VICAP 322 378#define SRST_ISP0 323 379#define SRST_ISP0_VICAP 324 380 381#define SRST_CORE_VPSS 325 382#define SRST_P_CSI_HOST_0 326 383#define SRST_P_CSI_HOST_1 327 384#define SRST_P_CSI_HOST_2 328 385#define SRST_P_CSI_HOST_3 329 386#define SRST_P_CSI_HOST_4 330 387 388#define SRST_CIFIN 331 389#define SRST_VICAP_I0CLK 332 390#define SRST_VICAP_I1CLK 333 391#define SRST_VICAP_I2CLK 334 392#define SRST_VICAP_I3CLK 335 393#define SRST_VICAP_I4CLK 336 394 395#define SRST_A_VOP_BIU 337 396#define SRST_A_VOP2_BIU 338 397#define SRST_H_VOP_BIU 339 398#define SRST_P_VOP_BIU 340 399#define SRST_H_VOP 341 400#define SRST_A_VOP 342 401#define SRST_D_VP0 343 402 403#define SRST_D_VP1 344 404#define SRST_D_VP2 345 405#define SRST_P_VOP2_BIU 346 406#define SRST_P_VOPGRF 347 407 408#define SRST_H_VO0_BIU 348 409#define SRST_P_VO0_BIU 349 410#define SRST_A_HDCP0_BIU 350 411#define SRST_P_VO0_GRF 351 412#define SRST_A_HDCP0 352 413#define SRST_H_HDCP0 353 414#define SRST_HDCP0 354 415 416#define SRST_P_DSIHOST0 355 417#define SRST_DSIHOST0 356 418#define SRST_P_HDMITX0 357 419#define SRST_HDMITX0_REF 358 420#define SRST_P_EDP0 359 421#define SRST_EDP0_24M 360 422 423#define SRST_M_SAI5_8CH 361 424#define SRST_H_SAI5_8CH 362 425#define SRST_M_SAI6_8CH 363 426#define SRST_H_SAI6_8CH 364 427#define SRST_H_SPDIF_TX2 365 428#define SRST_M_SPDIF_TX2 366 429#define SRST_H_SPDIF_RX2 367 430#define SRST_M_SPDIF_RX2 368 431 432#define SRST_H_SAI8_8CH 369 433#define SRST_M_SAI8_8CH 370 434 435#define SRST_H_VO1_BIU 371 436#define SRST_P_VO1_BIU 372 437#define SRST_M_SAI7_8CH 373 438#define SRST_H_SAI7_8CH 374 439#define SRST_H_SPDIF_TX3 375 440#define SRST_H_SPDIF_TX4 376 441#define SRST_H_SPDIF_TX5 377 442#define SRST_M_SPDIF_TX3 378 443 444#define SRST_DP0 379 445#define SRST_P_VO1_GRF 380 446#define SRST_A_HDCP1_BIU 381 447#define SRST_A_HDCP1 382 448#define SRST_H_HDCP1 383 449#define SRST_HDCP1 384 450#define SRST_H_SAI9_8CH 385 451#define SRST_M_SAI9_8CH 386 452#define SRST_M_SPDIF_TX4 387 453#define SRST_M_SPDIF_TX5 388 454 455#define SRST_GPU 389 456#define SRST_A_S_GPU_BIU 390 457#define SRST_A_M0_GPU_BIU 391 458#define SRST_P_GPU_BIU 392 459#define SRST_P_GPU_GRF 393 460#define SRST_GPU_PVTPLL 394 461#define SRST_P_PVTPLL_GPU 395 462 463#define SRST_A_CENTER_BIU 396 464#define SRST_A_DMA2DDR 397 465#define SRST_A_DDR_SHAREMEM 398 466#define SRST_A_DDR_SHAREMEM_BIU 399 467#define SRST_H_CENTER_BIU 400 468#define SRST_P_CENTER_GRF 401 469#define SRST_P_DMA2DDR 402 470#define SRST_P_SHAREMEM 403 471#define SRST_P_CENTER_BIU 404 472 473#define SRST_LINKSYM_HDMITXPHY0 405 474 475#define SRST_DP0_PIXELCLK 406 476#define SRST_PHY_DP0_TX 407 477#define SRST_DP1_PIXELCLK 408 478#define SRST_DP2_PIXELCLK 409 479 480#define SRST_H_VEPU1_BIU 410 481#define SRST_A_VEPU1_BIU 411 482#define SRST_H_VEPU1 412 483#define SRST_A_VEPU1 413 484#define SRST_VEPU1_CORE 414 485 486#define SRST_P_PHPPHY_CRU 415 487#define SRST_P_APB2ASB_SLV_CHIP_TOP 416 488#define SRST_P_PCIE2_COMBOPHY0 417 489#define SRST_P_PCIE2_COMBOPHY0_GRF 418 490#define SRST_P_PCIE2_COMBOPHY1 419 491#define SRST_P_PCIE2_COMBOPHY1_GRF 420 492 493#define SRST_PCIE0_PIPE_PHY 421 494#define SRST_PCIE1_PIPE_PHY 422 495 496#define SRST_H_CRYPTO_NS 423 497#define SRST_H_TRNG_NS 424 498#define SRST_P_OTPC_NS 425 499#define SRST_OTPC_NS 426 500 501#define SRST_P_HDPTX_GRF 427 502#define SRST_P_HDPTX_APB 428 503#define SRST_P_MIPI_DCPHY 429 504#define SRST_P_DCPHY_GRF 430 505#define SRST_P_BOT0_APB2ASB 431 506#define SRST_P_BOT1_APB2ASB 432 507#define SRST_USB2DEBUG 433 508#define SRST_P_CSIPHY_GRF 434 509#define SRST_P_CSIPHY 435 510#define SRST_P_USBPHY_GRF_0 436 511#define SRST_P_USBPHY_GRF_1 437 512#define SRST_P_USBDP_GRF 438 513#define SRST_P_USBDPPHY 439 514#define SRST_USBDP_COMBO_PHY_INIT 440 515 516#define SRST_USBDP_COMBO_PHY_CMN 441 517#define SRST_USBDP_COMBO_PHY_LANE 442 518#define SRST_USBDP_COMBO_PHY_PCS 443 519#define SRST_M_MIPI_DCPHY 444 520#define SRST_S_MIPI_DCPHY 445 521#define SRST_SCAN_CSIPHY 446 522#define SRST_P_VCCIO6_IOC 447 523#define SRST_OTGPHY_0 448 524#define SRST_OTGPHY_1 449 525#define SRST_HDPTX_INIT 450 526#define SRST_HDPTX_CMN 451 527#define SRST_HDPTX_LANE 452 528#define SRST_HDMITXHDP 453 529 530#define SRST_MPHY_INIT 454 531#define SRST_P_MPHY_GRF 455 532#define SRST_P_VCCIO7_IOC 456 533 534#define SRST_H_PMU1_BIU 457 535#define SRST_P_PMU1_NIU 458 536#define SRST_H_PMU_CM0_BIU 459 537#define SRST_PMU_CM0_CORE 460 538#define SRST_PMU_CM0_JTAG 461 539 540#define SRST_P_CRU_PMU1 462 541#define SRST_P_PMU1_GRF 463 542#define SRST_P_PMU1_IOC 464 543#define SRST_P_PMU1WDT 465 544#define SRST_T_PMU1WDT 466 545#define SRST_P_PMUTIMER 467 546#define SRST_PMUTIMER0 468 547#define SRST_PMUTIMER1 469 548#define SRST_P_PMU1PWM 470 549#define SRST_PMU1PWM 471 550 551#define SRST_P_I2C0 472 552#define SRST_I2C0 473 553#define SRST_S_UART1 474 554#define SRST_P_UART1 475 555#define SRST_PDM0 476 556#define SRST_H_PDM0 477 557 558#define SRST_M_PDM0 478 559#define SRST_H_VAD 479 560 561#define SRST_P_PMU0GRF 480 562#define SRST_P_PMU0IOC 481 563#define SRST_P_GPIO0 482 564#define SRST_DB_GPIO0 483 565 566#endif 567