1/* $NetBSD: st,stm32mp25-rcc.h,v 1.1.1.1 2026/01/18 05:21:56 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 4/* 5 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 6 * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> 7 */ 8 9#ifndef _DT_BINDINGS_STM32MP25_RESET_H_ 10#define _DT_BINDINGS_STM32MP25_RESET_H_ 11 12#define TIM1_R 0 13#define TIM2_R 1 14#define TIM3_R 2 15#define TIM4_R 3 16#define TIM5_R 4 17#define TIM6_R 5 18#define TIM7_R 6 19#define TIM8_R 7 20#define TIM10_R 8 21#define TIM11_R 9 22#define TIM12_R 10 23#define TIM13_R 11 24#define TIM14_R 12 25#define TIM15_R 13 26#define TIM16_R 14 27#define TIM17_R 15 28#define TIM20_R 16 29#define LPTIM1_R 17 30#define LPTIM2_R 18 31#define LPTIM3_R 19 32#define LPTIM4_R 20 33#define LPTIM5_R 21 34#define SPI1_R 22 35#define SPI2_R 23 36#define SPI3_R 24 37#define SPI4_R 25 38#define SPI5_R 26 39#define SPI6_R 27 40#define SPI7_R 28 41#define SPI8_R 29 42#define SPDIFRX_R 30 43#define USART1_R 31 44#define USART2_R 32 45#define USART3_R 33 46#define UART4_R 34 47#define UART5_R 35 48#define USART6_R 36 49#define UART7_R 37 50#define UART8_R 38 51#define UART9_R 39 52#define LPUART1_R 40 53#define IS2M_R 41 54#define I2C1_R 42 55#define I2C2_R 43 56#define I2C3_R 44 57#define I2C4_R 45 58#define I2C5_R 46 59#define I2C6_R 47 60#define I2C7_R 48 61#define I2C8_R 49 62#define SAI1_R 50 63#define SAI2_R 51 64#define SAI3_R 52 65#define SAI4_R 53 66#define MDF1_R 54 67#define MDF2_R 55 68#define FDCAN_R 56 69#define HDP_R 57 70#define ADC12_R 58 71#define ADC3_R 59 72#define ETH1_R 60 73#define ETH2_R 61 74#define USBH_R 62 75#define USB2PHY1_R 63 76#define USB2PHY2_R 64 77#define USB3DR_R 65 78#define USB3PCIEPHY_R 66 79#define USBTC_R 67 80#define ETHSW_R 68 81#define SDMMC1_R 69 82#define SDMMC1DLL_R 70 83#define SDMMC2_R 71 84#define SDMMC2DLL_R 72 85#define SDMMC3_R 73 86#define SDMMC3DLL_R 74 87#define GPU_R 75 88#define LTDC_R 76 89#define DSI_R 77 90#define LVDS_R 78 91#define CSI_R 79 92#define DCMIPP_R 80 93#define CCI_R 81 94#define VDEC_R 82 95#define VENC_R 83 96#define WWDG1_R 84 97#define WWDG2_R 85 98#define VREF_R 86 99#define DTS_R 87 100#define CRC_R 88 101#define SERC_R 89 102#define OSPIIOM_R 90 103#define I3C1_R 91 104#define I3C2_R 92 105#define I3C3_R 93 106#define I3C4_R 94 107#define IWDG2_KER_R 95 108#define IWDG4_KER_R 96 109#define RNG_R 97 110#define PKA_R 98 111#define SAES_R 99 112#define HASH_R 100 113#define CRYP1_R 101 114#define CRYP2_R 102 115#define PCIE_R 103 116#define OSPI1_R 104 117#define OSPI1DLL_R 105 118#define OSPI2_R 106 119#define OSPI2DLL_R 107 120#define FMC_R 108 121#define DBG_R 109 122#define GPIOA_R 110 123#define GPIOB_R 111 124#define GPIOC_R 112 125#define GPIOD_R 113 126#define GPIOE_R 114 127#define GPIOF_R 115 128#define GPIOG_R 116 129#define GPIOH_R 117 130#define GPIOI_R 118 131#define GPIOJ_R 119 132#define GPIOK_R 120 133#define GPIOZ_R 121 134#define HPDMA1_R 122 135#define HPDMA2_R 123 136#define HPDMA3_R 124 137#define LPDMA_R 125 138#define HSEM_R 126 139#define IPCC1_R 127 140#define IPCC2_R 128 141#define C2_HOLDBOOT_R 129 142#define C1_HOLDBOOT_R 130 143#define C1_R 131 144#define C1P1POR_R 132 145#define C1P1_R 133 146#define C2_R 134 147#define C3_R 135 148#define SYS_R 136 149#define VSW_R 137 150#define C1MS_R 138 151#define DDRCP_R 139 152#define DDRCAPB_R 140 153#define DDRPHYCAPB_R 141 154#define DDRCFG_R 142 155#define DDR_R 143 156 157#define STM32MP25_LAST_RESET 144 158 159#define RST_SCMI_C1_R 0 160#define RST_SCMI_C2_R 1 161#define RST_SCMI_C1_HOLDBOOT_R 2 162#define RST_SCMI_C2_HOLDBOOT_R 3 163#define RST_SCMI_FMC 4 164#define RST_SCMI_OSPI1 5 165#define RST_SCMI_OSPI1DLL 6 166#define RST_SCMI_OSPI2 7 167#define RST_SCMI_OSPI2DLL 8 168 169#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */ 170