1/* $NetBSD: stm32mp13-resets.h,v 1.1.1.1 2026/01/18 05:21:56 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 4/* 5 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 6 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. 7 */ 8 9#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ 10#define _DT_BINDINGS_STM32MP13_RESET_H_ 11 12#define TIM2_R 13568 13#define TIM3_R 13569 14#define TIM4_R 13570 15#define TIM5_R 13571 16#define TIM6_R 13572 17#define TIM7_R 13573 18#define LPTIM1_R 13577 19#define SPI2_R 13579 20#define SPI3_R 13580 21#define USART3_R 13583 22#define UART4_R 13584 23#define UART5_R 13585 24#define UART7_R 13586 25#define UART8_R 13587 26#define I2C1_R 13589 27#define I2C2_R 13590 28#define SPDIF_R 13594 29#define TIM1_R 13632 30#define TIM8_R 13633 31#define SPI1_R 13640 32#define USART6_R 13645 33#define SAI1_R 13648 34#define SAI2_R 13649 35#define DFSDM_R 13652 36#define FDCAN_R 13656 37#define LPTIM2_R 13696 38#define LPTIM3_R 13697 39#define LPTIM4_R 13698 40#define LPTIM5_R 13699 41#define SYSCFG_R 13707 42#define VREF_R 13709 43#define DTS_R 13712 44#define PMBCTRL_R 13713 45#define LTDC_R 13760 46#define DCMIPP_R 13761 47#define DDRPERFM_R 13768 48#define USBPHY_R 13776 49#define STGEN_R 13844 50#define USART1_R 13888 51#define USART2_R 13889 52#define SPI4_R 13890 53#define SPI5_R 13891 54#define I2C3_R 13892 55#define I2C4_R 13893 56#define I2C5_R 13894 57#define TIM12_R 13895 58#define TIM13_R 13896 59#define TIM14_R 13897 60#define TIM15_R 13898 61#define TIM16_R 13899 62#define TIM17_R 13900 63#define DMA1_R 13952 64#define DMA2_R 13953 65#define DMAMUX1_R 13954 66#define DMA3_R 13955 67#define DMAMUX2_R 13956 68#define ADC1_R 13957 69#define ADC2_R 13958 70#define USBO_R 13960 71#define GPIOA_R 14080 72#define GPIOB_R 14081 73#define GPIOC_R 14082 74#define GPIOD_R 14083 75#define GPIOE_R 14084 76#define GPIOF_R 14085 77#define GPIOG_R 14086 78#define GPIOH_R 14087 79#define GPIOI_R 14088 80#define TSC_R 14095 81#define PKA_R 14146 82#define SAES_R 14147 83#define CRYP1_R 14148 84#define HASH1_R 14149 85#define RNG1_R 14150 86#define AXIMC_R 14160 87#define MDMA_R 14208 88#define MCE_R 14209 89#define ETH1MAC_R 14218 90#define FMC_R 14220 91#define QSPI_R 14222 92#define SDMMC1_R 14224 93#define SDMMC2_R 14225 94#define CRC1_R 14228 95#define USBH_R 14232 96#define ETH2MAC_R 14238 97 98/* SCMI reset domain identifiers */ 99#define RST_SCMI_LTDC 0 100#define RST_SCMI_MDMA 1 101 102#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ 103