1 /* $NetBSD: qcom,q6afe.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 #ifndef __DT_BINDINGS_Q6_AFE_H__ 5 #define __DT_BINDINGS_Q6_AFE_H__ 6 7 /* Audio Front End (AFE) virtual ports IDs */ 8 #define HDMI_RX 1 9 #define SLIMBUS_0_RX 2 10 #define SLIMBUS_0_TX 3 11 #define SLIMBUS_1_RX 4 12 #define SLIMBUS_1_TX 5 13 #define SLIMBUS_2_RX 6 14 #define SLIMBUS_2_TX 7 15 #define SLIMBUS_3_RX 8 16 #define SLIMBUS_3_TX 9 17 #define SLIMBUS_4_RX 10 18 #define SLIMBUS_4_TX 11 19 #define SLIMBUS_5_RX 12 20 #define SLIMBUS_5_TX 13 21 #define SLIMBUS_6_RX 14 22 #define SLIMBUS_6_TX 15 23 #define PRIMARY_MI2S_RX 16 24 #define PRIMARY_MI2S_TX 17 25 #define SECONDARY_MI2S_RX 18 26 #define SECONDARY_MI2S_TX 19 27 #define TERTIARY_MI2S_RX 20 28 #define TERTIARY_MI2S_TX 21 29 #define QUATERNARY_MI2S_RX 22 30 #define QUATERNARY_MI2S_TX 23 31 #define PRIMARY_TDM_RX_0 24 32 #define PRIMARY_TDM_TX_0 25 33 #define PRIMARY_TDM_RX_1 26 34 #define PRIMARY_TDM_TX_1 27 35 #define PRIMARY_TDM_RX_2 28 36 #define PRIMARY_TDM_TX_2 29 37 #define PRIMARY_TDM_RX_3 30 38 #define PRIMARY_TDM_TX_3 31 39 #define PRIMARY_TDM_RX_4 32 40 #define PRIMARY_TDM_TX_4 33 41 #define PRIMARY_TDM_RX_5 34 42 #define PRIMARY_TDM_TX_5 35 43 #define PRIMARY_TDM_RX_6 36 44 #define PRIMARY_TDM_TX_6 37 45 #define PRIMARY_TDM_RX_7 38 46 #define PRIMARY_TDM_TX_7 39 47 #define SECONDARY_TDM_RX_0 40 48 #define SECONDARY_TDM_TX_0 41 49 #define SECONDARY_TDM_RX_1 42 50 #define SECONDARY_TDM_TX_1 43 51 #define SECONDARY_TDM_RX_2 44 52 #define SECONDARY_TDM_TX_2 45 53 #define SECONDARY_TDM_RX_3 46 54 #define SECONDARY_TDM_TX_3 47 55 #define SECONDARY_TDM_RX_4 48 56 #define SECONDARY_TDM_TX_4 49 57 #define SECONDARY_TDM_RX_5 50 58 #define SECONDARY_TDM_TX_5 51 59 #define SECONDARY_TDM_RX_6 52 60 #define SECONDARY_TDM_TX_6 53 61 #define SECONDARY_TDM_RX_7 54 62 #define SECONDARY_TDM_TX_7 55 63 #define TERTIARY_TDM_RX_0 56 64 #define TERTIARY_TDM_TX_0 57 65 #define TERTIARY_TDM_RX_1 58 66 #define TERTIARY_TDM_TX_1 59 67 #define TERTIARY_TDM_RX_2 60 68 #define TERTIARY_TDM_TX_2 61 69 #define TERTIARY_TDM_RX_3 62 70 #define TERTIARY_TDM_TX_3 63 71 #define TERTIARY_TDM_RX_4 64 72 #define TERTIARY_TDM_TX_4 65 73 #define TERTIARY_TDM_RX_5 66 74 #define TERTIARY_TDM_TX_5 67 75 #define TERTIARY_TDM_RX_6 68 76 #define TERTIARY_TDM_TX_6 69 77 #define TERTIARY_TDM_RX_7 70 78 #define TERTIARY_TDM_TX_7 71 79 #define QUATERNARY_TDM_RX_0 72 80 #define QUATERNARY_TDM_TX_0 73 81 #define QUATERNARY_TDM_RX_1 74 82 #define QUATERNARY_TDM_TX_1 75 83 #define QUATERNARY_TDM_RX_2 76 84 #define QUATERNARY_TDM_TX_2 77 85 #define QUATERNARY_TDM_RX_3 78 86 #define QUATERNARY_TDM_TX_3 79 87 #define QUATERNARY_TDM_RX_4 80 88 #define QUATERNARY_TDM_TX_4 81 89 #define QUATERNARY_TDM_RX_5 82 90 #define QUATERNARY_TDM_TX_5 83 91 #define QUATERNARY_TDM_RX_6 84 92 #define QUATERNARY_TDM_TX_6 85 93 #define QUATERNARY_TDM_RX_7 86 94 #define QUATERNARY_TDM_TX_7 87 95 #define QUINARY_TDM_RX_0 88 96 #define QUINARY_TDM_TX_0 89 97 #define QUINARY_TDM_RX_1 90 98 #define QUINARY_TDM_TX_1 91 99 #define QUINARY_TDM_RX_2 92 100 #define QUINARY_TDM_TX_2 93 101 #define QUINARY_TDM_RX_3 94 102 #define QUINARY_TDM_TX_3 95 103 #define QUINARY_TDM_RX_4 96 104 #define QUINARY_TDM_TX_4 97 105 #define QUINARY_TDM_RX_5 98 106 #define QUINARY_TDM_TX_5 99 107 #define QUINARY_TDM_RX_6 100 108 #define QUINARY_TDM_TX_6 101 109 #define QUINARY_TDM_RX_7 102 110 #define QUINARY_TDM_TX_7 103 111 #define DISPLAY_PORT_RX 104 112 #define WSA_CODEC_DMA_RX_0 105 113 #define WSA_CODEC_DMA_TX_0 106 114 #define WSA_CODEC_DMA_RX_1 107 115 #define WSA_CODEC_DMA_TX_1 108 116 #define WSA_CODEC_DMA_TX_2 109 117 #define VA_CODEC_DMA_TX_0 110 118 #define VA_CODEC_DMA_TX_1 111 119 #define VA_CODEC_DMA_TX_2 112 120 #define RX_CODEC_DMA_RX_0 113 121 #define TX_CODEC_DMA_TX_0 114 122 #define RX_CODEC_DMA_RX_1 115 123 #define TX_CODEC_DMA_TX_1 116 124 #define RX_CODEC_DMA_RX_2 117 125 #define TX_CODEC_DMA_TX_2 118 126 #define RX_CODEC_DMA_RX_3 119 127 #define TX_CODEC_DMA_TX_3 120 128 #define RX_CODEC_DMA_RX_4 121 129 #define TX_CODEC_DMA_TX_4 122 130 #define RX_CODEC_DMA_RX_5 123 131 #define TX_CODEC_DMA_TX_5 124 132 #define RX_CODEC_DMA_RX_6 125 133 #define RX_CODEC_DMA_RX_7 126 134 #define QUINARY_MI2S_RX 127 135 #define QUINARY_MI2S_TX 128 136 137 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 138 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 139 #define LPASS_CLK_ID_SEC_MI2S_IBIT 3 140 #define LPASS_CLK_ID_SEC_MI2S_EBIT 4 141 #define LPASS_CLK_ID_TER_MI2S_IBIT 5 142 #define LPASS_CLK_ID_TER_MI2S_EBIT 6 143 #define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 144 #define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 145 #define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 146 #define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 147 #define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 148 #define LPASS_CLK_ID_QUI_MI2S_IBIT 12 149 #define LPASS_CLK_ID_QUI_MI2S_EBIT 13 150 #define LPASS_CLK_ID_SEN_MI2S_IBIT 14 151 #define LPASS_CLK_ID_SEN_MI2S_EBIT 15 152 #define LPASS_CLK_ID_INT0_MI2S_IBIT 16 153 #define LPASS_CLK_ID_INT1_MI2S_IBIT 17 154 #define LPASS_CLK_ID_INT2_MI2S_IBIT 18 155 #define LPASS_CLK_ID_INT3_MI2S_IBIT 19 156 #define LPASS_CLK_ID_INT4_MI2S_IBIT 20 157 #define LPASS_CLK_ID_INT5_MI2S_IBIT 21 158 #define LPASS_CLK_ID_INT6_MI2S_IBIT 22 159 #define LPASS_CLK_ID_QUI_MI2S_OSR 23 160 #define LPASS_CLK_ID_PRI_PCM_IBIT 24 161 #define LPASS_CLK_ID_PRI_PCM_EBIT 25 162 #define LPASS_CLK_ID_SEC_PCM_IBIT 26 163 #define LPASS_CLK_ID_SEC_PCM_EBIT 27 164 #define LPASS_CLK_ID_TER_PCM_IBIT 28 165 #define LPASS_CLK_ID_TER_PCM_EBIT 29 166 #define LPASS_CLK_ID_QUAD_PCM_IBIT 30 167 #define LPASS_CLK_ID_QUAD_PCM_EBIT 31 168 #define LPASS_CLK_ID_QUIN_PCM_IBIT 32 169 #define LPASS_CLK_ID_QUIN_PCM_EBIT 33 170 #define LPASS_CLK_ID_QUI_PCM_OSR 34 171 #define LPASS_CLK_ID_PRI_TDM_IBIT 35 172 #define LPASS_CLK_ID_PRI_TDM_EBIT 36 173 #define LPASS_CLK_ID_SEC_TDM_IBIT 37 174 #define LPASS_CLK_ID_SEC_TDM_EBIT 38 175 #define LPASS_CLK_ID_TER_TDM_IBIT 39 176 #define LPASS_CLK_ID_TER_TDM_EBIT 40 177 #define LPASS_CLK_ID_QUAD_TDM_IBIT 41 178 #define LPASS_CLK_ID_QUAD_TDM_EBIT 42 179 #define LPASS_CLK_ID_QUIN_TDM_IBIT 43 180 #define LPASS_CLK_ID_QUIN_TDM_EBIT 44 181 #define LPASS_CLK_ID_QUIN_TDM_OSR 45 182 #define LPASS_CLK_ID_MCLK_1 46 183 #define LPASS_CLK_ID_MCLK_2 47 184 #define LPASS_CLK_ID_MCLK_3 48 185 #define LPASS_CLK_ID_MCLK_4 49 186 #define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 187 #define LPASS_CLK_ID_INT_MCLK_0 51 188 #define LPASS_CLK_ID_INT_MCLK_1 52 189 #define LPASS_CLK_ID_MCLK_5 53 190 #define LPASS_CLK_ID_WSA_CORE_MCLK 54 191 #define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 192 #define LPASS_CLK_ID_VA_CORE_MCLK 56 193 #define LPASS_CLK_ID_TX_CORE_MCLK 57 194 #define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 195 #define LPASS_CLK_ID_RX_CORE_MCLK 59 196 #define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 197 #define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 198 199 #define LPASS_HW_AVTIMER_VOTE 101 200 #define LPASS_HW_MACRO_VOTE 102 201 #define LPASS_HW_DCODEC_VOTE 103 202 203 #define Q6AFE_MAX_CLK_ID 104 204 205 #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 206 #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 207 #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 208 #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 209 210 #endif /* __DT_BINDINGS_Q6_AFE_H__ */ 211
Indexes created Tue Sep 30 17:09:57 GMT 2025