1/*	$NetBSD: mediatek,lvts-thermal.h,v 1.1.1.1 2026/01/18 05:21:57 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Copyright (c) 2023 MediaTek Inc.
6 * Author: Balsam CHIHI <bchihi@baylibre.com>
7 */
8
9#ifndef __MEDIATEK_LVTS_DT_H
10#define __MEDIATEK_LVTS_DT_H
11
12#define MT7988_CPU_0		0
13#define MT7988_CPU_1		1
14#define MT7988_ETH2P5G_0	2
15#define MT7988_ETH2P5G_1	3
16#define MT7988_TOPS_0		4
17#define MT7988_TOPS_1		5
18#define MT7988_ETHWARP_0	6
19#define MT7988_ETHWARP_1	7
20
21#define MT8186_LITTLE_CPU0	0
22#define MT8186_LITTLE_CPU1	1
23#define MT8186_LITTLE_CPU2	2
24#define MT8186_CAM		3
25#define MT8186_BIG_CPU0	4
26#define MT8186_BIG_CPU1	5
27#define MT8186_NNA		6
28#define MT8186_ADSP		7
29#define MT8186_GPU		8
30
31#define MT8188_MCU_LITTLE_CPU0	0
32#define MT8188_MCU_LITTLE_CPU1	1
33#define MT8188_MCU_LITTLE_CPU2	2
34#define MT8188_MCU_LITTLE_CPU3	3
35#define MT8188_MCU_BIG_CPU0	4
36#define MT8188_MCU_BIG_CPU1	5
37
38#define MT8188_AP_APU		0
39#define MT8188_AP_GPU0		1
40#define MT8188_AP_GPU1		2
41#define MT8188_AP_ADSP		3
42#define MT8188_AP_VDO		4
43#define MT8188_AP_INFRA		5
44#define MT8188_AP_CAM1		6
45#define MT8188_AP_CAM2		7
46
47#define MT8195_MCU_BIG_CPU0     0
48#define MT8195_MCU_BIG_CPU1     1
49#define MT8195_MCU_BIG_CPU2     2
50#define MT8195_MCU_BIG_CPU3     3
51#define MT8195_MCU_LITTLE_CPU0  4
52#define MT8195_MCU_LITTLE_CPU1  5
53#define MT8195_MCU_LITTLE_CPU2  6
54#define MT8195_MCU_LITTLE_CPU3  7
55
56#define MT8195_AP_VPU0  8
57#define MT8195_AP_VPU1  9
58#define MT8195_AP_GPU0  10
59#define MT8195_AP_GPU1  11
60#define MT8195_AP_VDEC  12
61#define MT8195_AP_IMG   13
62#define MT8195_AP_INFRA 14
63#define MT8195_AP_CAM0  15
64#define MT8195_AP_CAM1  16
65
66#define MT8192_MCU_BIG_CPU0     0
67#define MT8192_MCU_BIG_CPU1     1
68#define MT8192_MCU_BIG_CPU2     2
69#define MT8192_MCU_BIG_CPU3     3
70#define MT8192_MCU_LITTLE_CPU0  4
71#define MT8192_MCU_LITTLE_CPU1  5
72#define MT8192_MCU_LITTLE_CPU2  6
73#define MT8192_MCU_LITTLE_CPU3  7
74
75#define MT8192_AP_VPU0  8
76#define MT8192_AP_VPU1  9
77#define MT8192_AP_GPU0  10
78#define MT8192_AP_GPU1  11
79#define MT8192_AP_INFRA 12
80#define MT8192_AP_CAM   13
81#define MT8192_AP_MD0   14
82#define MT8192_AP_MD1   15
83#define MT8192_AP_MD2   16
84
85#endif /* __MEDIATEK_LVTS_DT_H */
86