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tprof_x86.c revision 1.6
      1 /*	$NetBSD: tprof_x86.c,v 1.6 2018/11/26 07:45:47 knakahara Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2018 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Maxime Villard.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 #include <stdio.h>
     34 #include <stdlib.h>
     35 #include <stdbool.h>
     36 #include <string.h>
     37 #include <unistd.h>
     38 #include <err.h>
     39 #include <machine/specialreg.h>
     40 #include <dev/tprof/tprof_ioctl.h>
     41 #include "../tprof.h"
     42 
     43 int tprof_event_init(uint32_t);
     44 void tprof_event_list(void);
     45 void tprof_event_lookup(const char *, struct tprof_param *);
     46 
     47 struct name_to_event {
     48 	const char *name;
     49 	uint64_t event;
     50 	uint64_t unit;
     51 	bool enabled;
     52 };
     53 
     54 struct event_table {
     55 	const char *tablename;
     56 	struct name_to_event *names;
     57 	size_t nevents;
     58 	struct event_table *next;
     59 };
     60 
     61 static struct event_table *cpuevents = NULL;
     62 
     63 static void x86_cpuid(unsigned int *eax, unsigned int *ebx,
     64     unsigned int *ecx, unsigned int *edx)
     65 {
     66 	asm volatile("cpuid"
     67 	    : "=a" (*eax),
     68 	      "=b" (*ebx),
     69 	      "=c" (*ecx),
     70 	      "=d" (*edx)
     71 	    : "0" (*eax), "2" (*ecx));
     72 }
     73 
     74 /* -------------------------------------------------------------------------- */
     75 
     76 /*
     77  * Intel Architectural Version 1.
     78  */
     79 static struct name_to_event intel_arch1_names[] = {
     80 	/* Event Name - Event Select - UMask */
     81 	{ "unhalted-core-cycles",	0x3C, 0x00, true },
     82 	{ "instruction-retired",	0xC0, 0x00, true },
     83 	{ "unhalted-reference-cycles",	0x3C, 0x01, true },
     84 	{ "llc-reference",		0x2E, 0x4F, true },
     85 	{ "llc-misses",			0x2E, 0x41, true },
     86 	{ "branch-instruction-retired",	0xC4, 0x00, true },
     87 	{ "branch-misses-retired",	0xC5, 0x00, true },
     88 };
     89 
     90 static struct event_table intel_arch1 = {
     91 	.tablename = "Intel Architectural Version 1",
     92 	.names = intel_arch1_names,
     93 	.nevents = sizeof(intel_arch1_names) /
     94 	    sizeof(struct name_to_event),
     95 	.next = NULL
     96 };
     97 
     98 static struct event_table *
     99 init_intel_arch1(void)
    100 {
    101 	unsigned int eax, ebx, ecx, edx;
    102 	struct event_table *table;
    103 	size_t i;
    104 
    105 	eax = 0x0A;
    106 	ebx = 0;
    107 	ecx = 0;
    108 	edx = 0;
    109 	x86_cpuid(&eax, &ebx, &ecx, &edx);
    110 
    111 	table = &intel_arch1;
    112 	for (i = 0; i < table->nevents; i++) {
    113 		/* Disable the unsupported events. */
    114 		if ((ebx & (i << 1)) != 0)
    115 			table->names[i].enabled = false;
    116 	}
    117 
    118 	return table;
    119 }
    120 
    121 /*
    122  * Intel Silvermont/Airmont.
    123  */
    124 static struct name_to_event intel_silvermont_airmont_names[] = {
    125 	{ "REHABQ.LD_BLOCK_ST_FORWARD",		0x03, 0x01, true },
    126 	{ "REHABQ.LD_BLOCK_STD_NOTREADY",	0x03, 0x02, true },
    127 	{ "REHABQ.ST_SPLITS",			0x03, 0x04, true },
    128 	{ "REHABQ.LD_SPLITS",			0x03, 0x08, true },
    129 	{ "REHABQ.LOCK",			0x03, 0x10, true },
    130 	{ "REHABQ.STA_FULL",			0x03, 0x20, true },
    131 	{ "REHABQ.ANY_LD",			0x03, 0x40, true },
    132 	{ "REHABQ.ANY_ST",			0x03, 0x80, true },
    133 	{ "MEM_UOPS_RETIRED.L1_MISS_LOADS",	0x04, 0x01, true },
    134 	{ "MEM_UOPS_RETIRED.L2_HIT_LOADS",	0x04, 0x02, true },
    135 	{ "MEM_UOPS_RETIRED.L2_MISS_LOADS",	0x04, 0x04, true },
    136 	{ "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",	0x04, 0x08, true },
    137 	{ "MEM_UOPS_RETIRED.UTLB_MISS",		0x04, 0x10, true },
    138 	{ "MEM_UOPS_RETIRED.HITM",		0x04, 0x20, true },
    139 	{ "MEM_UOPS_RETIRED.ALL_LOADS",		0x04, 0x40, true },
    140 	{ "MEM_UOP_RETIRED.ALL_STORES",		0x04, 0x80, true },
    141 	{ "PAGE_WALKS.D_SIDE_CYCLES",		0x05, 0x01, true },
    142 	{ "PAGE_WALKS.I_SIDE_CYCLES",		0x05, 0x02, true },
    143 	{ "PAGE_WALKS.WALKS",			0x05, 0x03, true },
    144 	{ "LONGEST_LAT_CACHE.MISS",		0x2E, 0x41, true },
    145 	{ "LONGEST_LAT_CACHE.REFERENCE",	0x2E, 0x4F, true },
    146 	{ "L2_REJECT_XQ.ALL",			0x30, 0x00, true },
    147 	{ "CORE_REJECT_L2Q.ALL",		0x31, 0x00, true },
    148 	{ "CPU_CLK_UNHALTED.CORE_P",		0x3C, 0x00, true },
    149 	{ "CPU_CLK_UNHALTED.REF_P",		0x3C, 0x01, true },
    150 	{ "ICACHE.HIT",				0x80, 0x01, true },
    151 	{ "ICACHE.MISSES",			0x80, 0x02, true },
    152 	{ "ICACHE.ACCESSES",			0x80, 0x03, true },
    153 	{ "OFFCORE_RESPONSE_0",			0xB7, 0x01, true },
    154 	{ "OFFCORE_RESPONSE_1",			0xB7, 0x02, true },
    155 	{ "INST_RETIRED.ANY_P",			0xC0, 0x00, true },
    156 	{ "UOPS_RETIRED.MS",			0xC2, 0x01, true },
    157 	{ "UOPS_RETIRED.ALL",			0xC2, 0x10, true },
    158 	{ "MACHINE_CLEARS.SMC",			0xC3, 0x01, true },
    159 	{ "MACHINE_CLEARS.MEMORY_ORDERING",	0xC3, 0x02, true },
    160 	{ "MACHINE_CLEARS.FP_ASSIST",		0xC3, 0x04, true },
    161 	{ "MACHINE_CLEARS.ALL",			0xC3, 0x08, true },
    162 	{ "BR_INST_RETIRED.ALL_BRANCHES",	0xC4, 0x00, true },
    163 	{ "BR_INST_RETIRED.JCC",		0xC4, 0x7E, true },
    164 	{ "BR_INST_RETIRED.FAR_BRANCH",		0xC4, 0xBF, true },
    165 	{ "BR_INST_RETIRED.NON_RETURN_IND",	0xC4, 0xEB, true },
    166 	{ "BR_INST_RETIRED.RETURN",		0xC4, 0xF7, true },
    167 	{ "BR_INST_RETIRED.CALL",		0xC4, 0xF9, true },
    168 	{ "BR_INST_RETIRED.IND_CALL",		0xC4, 0xFB, true },
    169 	{ "BR_INST_RETIRED.REL_CALL",		0xC4, 0xFD, true },
    170 	{ "BR_INST_RETIRED.TAKEN_JCC",		0xC4, 0xFE, true },
    171 	{ "BR_MISP_RETIRED.ALL_BRANCHES",	0xC5, 0x00, true },
    172 	{ "BR_MISP_RETIRED.JCC",		0xC5, 0x7E, true },
    173 	{ "BR_MISP_RETIRED.FAR",		0xC5, 0xBF, true },
    174 	{ "BR_MISP_RETIRED.NON_RETURN_IND",	0xC5, 0xEB, true },
    175 	{ "BR_MISP_RETIRED.RETURN",		0xC5, 0xF7, true },
    176 	{ "BR_MISP_RETIRED.CALL",		0xC5, 0xF9, true },
    177 	{ "BR_MISP_RETIRED.IND_CALL",		0xC5, 0xFB, true },
    178 	{ "BR_MISP_RETIRED.REL_CALL",		0xC5, 0xFD, true },
    179 	{ "BR_MISP_RETIRED.TAKEN_JCC",		0xC5, 0xFE, true },
    180 	{ "NO_ALLOC_CYCLES.ROB_FULL",		0xCA, 0x01, true },
    181 	{ "NO_ALLOC_CYCLES.RAT_STALL",		0xCA, 0x20, true },
    182 	{ "NO_ALLOC_CYCLES.ALL",		0xCA, 0x3F, true },
    183 	{ "NO_ALLOC_CYCLES.NOT_DELIVERED",	0xCA, 0x50, true },
    184 	{ "RS_FULL_STALL.MEC",			0xCB, 0x01, true },
    185 	{ "RS_FULL_STALL.ALL",			0xCB, 0x1F, true },
    186 	{ "CYCLES_DIV_BUSY.ANY",		0xCD, 0x01, true },
    187 	{ "BACLEARS.ALL",			0xE6, 0x01, true },
    188 	{ "BACLEARS.RETURN",			0xE6, 0x08, true },
    189 	{ "BACLEARS.COND",			0xE6, 0x10, true },
    190 	{ "MS_DECODED.MS_ENTRY",		0xE7, 0x01, true },
    191 };
    192 
    193 static struct event_table intel_silvermont_airmont = {
    194 	.tablename = "Intel Silvermont/Airmont",
    195 	.names = intel_silvermont_airmont_names,
    196 	.nevents = sizeof(intel_silvermont_airmont_names) /
    197 	    sizeof(struct name_to_event),
    198 	.next = NULL
    199 };
    200 
    201 static struct event_table *
    202 init_intel_silvermont_airmont(void)
    203 {
    204 
    205 	return &intel_silvermont_airmont;
    206 }
    207 
    208 /*
    209  * Intel Goldmont
    210  */
    211 static struct name_to_event intel_goldmont_names[] = {
    212 	{ "LD_BLOCKS.ALL_BLOCK",			0x03,	0x10, true },
    213 	{ "LD_BLOCKS.UTLB_MISS",			0x03,	0x08, true },
    214 	{ "LD_BLOCKS.STORE_FORWARD",			0x03,	0x02, true },
    215 	{ "LD_BLOCKS.DATA_UNKNOWN",			0x03,	0x01, true },
    216 	{ "LD_BLOCKS.4K_ALIAS",				0x03,	0x04, true },
    217 	{ "PAGE_WALKS.D_SIDE_CYCLES",			0x05,	0x01, true },
    218 	{ "PAGE_WALKS.I_SIDE_CYCLES",			0x05,	0x02, true },
    219 	{ "PAGE_WALKS.CYCLES",				0x05,	0x03, true },
    220 	{ "UOPS_ISSUED.ANY",				0x0E,	0x00, true },
    221 	{ "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",		0x13,	0x02, true },
    222 	{ "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",		0x13,	0x04, true },
    223 	{ "LONGEST_LAT_CACHE.REFERENCE",		0x2E,	0x4F, true },
    224 	{ "LONGEST_LAT_CACHE.MISS",			0x2E,	0x41, true },
    225 	{ "L2_REJECT_XQ.ALL",				0x30,	0x00, true },
    226 	{ "CORE_REJECT_L2Q.ALL",			0x31,	0x00, true },
    227 	{ "CPU_CLK_UNHALTED.CORE_P",			0x3C,	0x00, true },
    228 	{ "CPU_CLK_UNHALTED.REF",			0x3C,	0x01, true },
    229 	{ "DL1.DIRTY_EVICTION",				0x51,	0x01, true },
    230 	{ "ICACHE.HIT",					0x80,	0x01, true },
    231 	{ "ICACHE.MISSES",				0x80,	0x02, true },
    232 	{ "ICACHE.ACCESSES",				0x80,	0x03, true },
    233 	{ "ITLB.MISS",					0x81,	0x04, true },
    234 	{ "FETCH_STALL.ALL",				0x86,	0x00, true },
    235 	{ "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",	0x86,	0x01, true },
    236 	{ "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",	0x86,	0x02, true },
    237 	{ "UOPS_NOT_DELIVERED.ANY",			0x9C,	0x00, true },
    238 	{ "OFFCORE_RESPONSE.0",				0xB7,	0x01, true },
    239 	{ "OFFCORE_RESPONSE.1",				0xB7,	0x02, true },
    240 	{ "INST_RETIRED.ANY_P",				0xC0,	0x00, true },
    241 	{ "UOPS_RETIRED.ANY",				0xC2,	0x00, true },
    242 	{ "UOPS_RETIRED.MS",				0xC2,	0x01, true },
    243 	{ "UOPS_RETIRED.FPDIV",				0xC2,	0x08, true },
    244 	{ "UOPS_RETIRED.IDIV",				0xC2,	0x10, true },
    245 	{ "MACHINE_CLEARS.SMC",				0xC3,	0x01, true },
    246 	{ "MACHINE_CLEARS.MEMORY_ORDERING",		0xC3,	0x02, true },
    247 	{ "MACHINE_CLEARS.FP_ASSIST",			0xC3,	0x04, true },
    248 	{ "MACHINE_CLEARS.DISAMBIGUATION",		0xC3,	0x08, true },
    249 	{ "MACHINE_CLEARS.ALL",				0xC3,	0x00, true },
    250 	{ "BR_INST_RETIRED.ALL_BRANCHES",		0xC4,	0x00, true },
    251 	{ "BR_INST_RETIRED.JCC",			0xC4,	0x7E, true },
    252 	{ "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",		0xC4,	0x80, true },
    253 	{ "BR_INST_RETIRED.TAKEN_JCC",			0xC4,	0xFE, true },
    254 	{ "BR_INST_RETIRED.CALL",			0xC4,	0xF9, true },
    255 	{ "BR_INST_RETIRED.REL_CALL",			0xC4,	0xFD, true },
    256 	{ "BR_INST_RETIRED.IND_CALL",			0xC4,	0xFB, true },
    257 	{ "BR_INST_RETIRED.RETURN",			0xC4,	0xF7, true },
    258 	{ "BR_INST_RETIRED.NON_RETURN_IND",		0xC4,	0xEB, true },
    259 	{ "BR_INST_RETIRED.FAR_BRANCH",			0xC4,	0xBF, true },
    260 	{ "BR_MISP_RETIRED.ALL_BRANCHES",		0xC5,	0x00, true },
    261 	{ "BR_MISP_RETIRED.JCC",			0xC5,	0x7E, true },
    262 	{ "BR_MISP_RETIRED.TAKEN_JCC",			0xC5,	0xFE, true },
    263 	{ "BR_MISP_RETIRED.IND_CALL",			0xC5,	0xFB, true },
    264 	{ "BR_MISP_RETIRED.RETURN",			0xC5,	0xF7, true },
    265 	{ "BR_MISP_RETIRED.NON_RETURN_IND",		0xC5,	0xEB, true },
    266 	{ "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",	0xCA,	0x01, true },
    267 	{ "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",		0xCA,	0x02, true },
    268 	{ "ISSUE_SLOTS_NOT_CONSUMED.ANY",		0xCA,	0x00, true },
    269 	{ "HW_INTERRUPTS.RECEIVED",			0xCB,	0x01, true },
    270 	{ "HW_INTERRUPTS.MASKED",			0xCB,	0x02, true },
    271 	{ "HW_INTERRUPTS.PENDING_AND_MASKED",		0xCB,	0x04, true },
    272 	{ "CYCLES_DIV_BUSY.ALL",			0xCD,	0x00, true },
    273 	{ "CYCLES_DIV_BUSY.IDIV",			0xCD,	0x01, true },
    274 	{ "CYCLES_DIV_BUSY.FPDIV",			0xCD,	0x02, true },
    275 	{ "MEM_UOPS_RETIRED.ALL_LOADS",			0xD0,	0x81, true },
    276 	{ "MEM_UOPS_RETIRED.ALL_STORES",		0xD0,	0x82, true },
    277 	{ "MEM_UOPS_RETIRED.ALL",			0xD0,	0x83, true },
    278 	{ "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",		0xD0,	0x11, true },
    279 	{ "MEM_UOPS_RETIRED.DTLB_MISS_STORES",		0xD0,	0x12, true },
    280 	{ "MEM_UOPS_RETIRED.DTLB_MISS",			0xD0,	0x13, true },
    281 	{ "MEM_UOPS_RETIRED.LOCK_LOADS",		0xD0,	0x21, true },
    282 	{ "MEM_UOPS_RETIRED.SPLIT_LOADS",		0xD0,	0x41, true },
    283 	{ "MEM_UOPS_RETIRED.SPLIT_STORES",		0xD0,	0x42, true },
    284 	{ "MEM_UOPS_RETIRED.SPLIT",			0xD0,	0x43, true },
    285 	{ "MEM_LOAD_UOPS_RETIRED.L1_HIT",		0xD1,	0x01, true },
    286 	{ "MEM_LOAD_UOPS_RETIRED.L1_MISS",		0xD1,	0x08, true },
    287 	{ "MEM_LOAD_UOPS_RETIRED.L2_HIT",		0xD1,	0x02, true },
    288 	{ "MEM_LOAD_UOPS_RETIRED.L2_MISS",		0xD1,	0x10, true },
    289 	{ "MEM_LOAD_UOPS_RETIRED.HITM",			0xD1,	0x20, true },
    290 	{ "MEM_LOAD_UOPS_RETIRED.WCB_HIT",		0xD1,	0x40, true },
    291 	{ "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",		0xD1,	0x80, true },
    292 	{ "BACLEARS.ALL",				0xE6,	0x01, true },
    293 	{ "BACLEARS.RETURN",				0xE6,	0x08, true },
    294 	{ "BACLEAR.CONDS",				0xE6,	0x10, true },
    295 	{ "MS_DECODED.MS_ENTRY",			0xE7,	0x01, true },
    296 	{ "DECODED_RESTRICTION.PREDECODE_WRONG",	0xE9,	0x01, true },
    297 };
    298 
    299 static struct event_table intel_goldmont = {
    300 	.tablename = "Intel Goldmont",
    301 	.names = intel_goldmont_names,
    302 	.nevents = sizeof(intel_goldmont_names) /
    303 	    sizeof(struct name_to_event),
    304 	.next = NULL
    305 };
    306 
    307 static struct event_table *
    308 init_intel_goldmont(void)
    309 {
    310 
    311 	return &intel_goldmont;
    312 }
    313 
    314 /*
    315  * Intel Skylake/Kabylake.
    316  *
    317  * The events that are not listed, because they are of little interest or
    318  * require extra configuration:
    319  *     TX_*
    320  *     FRONTEND_RETIRED.*
    321  *     FP_ARITH_INST_RETIRED.*
    322  *     HLE_RETIRED.*
    323  *     RTM_RETIRED.*
    324  *     MEM_TRANS_RETIRED.*
    325  *     UOPS_DISPATCHED_PORT.*
    326  */
    327 static struct name_to_event intel_skylake_kabylake_names[] = {
    328 	/* Event Name - Event Select - UMask */
    329 	{ "LD_BLOCKS.STORE_FORWARD",					0x03, 0x02, true },
    330 	{ "LD_BLOCKS.NO_SR",						0x03, 0x08, true },
    331 	{ "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",				0x07, 0x01, true },
    332 	{ "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",			0x08, 0x01, true },
    333 	{ "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",				0x08, 0x02, true },
    334 	{ "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",			0x08, 0x04, true },
    335 	{ "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",				0x08, 0x08, true },
    336 	{ "DTLB_LOAD_MISSES.WALK_COMPLETED",				0x08, 0x0E, true },
    337 	{ "DTLB_LOAD_MISSES.WALK_PENDING",				0x08, 0x10, true },
    338 	{ "DTLB_LOAD_MISSES.STLB_HIT",					0x08, 0x20, true },
    339 	{ "INT_MISC.RECOVERY_CYCLES",					0x0D, 0x01, true },
    340 	{ "INT_MISC.CLEAR_RESTEER_CYCLES",				0x0D, 0x80, true },
    341 	{ "UOPS_ISSUED.ANY",						0x0E, 0x01, true },
    342 	{ "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",				0x0E, 0x02, true },
    343 	{ "UOPS_ISSUED.SLOW_LEA",					0x0E, 0x20, true },
    344 	{ "L2_RQSTS.DEMAND_DATA_RD_MISS",				0x24, 0x21, true },
    345 	{ "L2_RQSTS.RFO_MISS",						0x24, 0x22, true },
    346 	{ "L2_RQSTS.CODE_RD_MISS",					0x24, 0x24, true },
    347 	{ "L2_RQSTS.ALL_DEMAND_MISS",					0x24, 0x27, true },
    348 	{ "L2_RQSTS.PF_MISS",						0x24, 0x38, true },
    349 	{ "L2_RQSTS.MISS",						0x24, 0x3F, true },
    350 	{ "L2_RQSTS.DEMAND_DATA_RD_HIT",				0x24, 0x41, true },
    351 	{ "L2_RQSTS.RFO_HIT",						0x24, 0x42, true },
    352 	{ "L2_RQSTS.CODE_RD_HIT",					0x24, 0x44, true },
    353 	{ "L2_RQSTS.PF_HIT",						0x24, 0xD8, true },
    354 	{ "L2_RQSTS.ALL_DEMAND_DATA_RD",				0x24, 0xE1, true },
    355 	{ "L2_RQSTS.ALL_RFO",						0x24, 0xE2, true },
    356 	{ "L2_RQSTS.ALL_CODE_RD",					0x24, 0xE4, true },
    357 	{ "L2_RQSTS.ALL_DEMAND_REFERENCES",				0x24, 0xE7, true },
    358 	{ "L2_RQSTS.ALL_PF",						0x24, 0xF8, true },
    359 	{ "L2_RQSTS.REFERENCES",					0x24, 0xFF, true },
    360 	{ "SW_PREFETCH_ACCESS.NTA",					0x32, 0x01, true },
    361 	{ "SW_PREFETCH_ACCESS.T0",					0x32, 0x02, true },
    362 	{ "SW_PREFETCH_ACCESS.T1_T2",					0x32, 0x04, true },
    363 	{ "SW_PREFETCH_ACCESS.PREFETCHW",				0x32, 0x08, true },
    364 	{ "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",			0x3C, 0x02, true },
    365 	{ "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",				0x3C, 0x02, true },
    366 	{ "L1D_PEND_MISS.PENDING",					0x48, 0x01, true },
    367 	{ "L1D_PEND_MISS.FB_FULL",					0x48, 0x02, true },
    368 	{ "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",			0x49, 0x01, true },
    369 	{ "DTLB_STORE_MISSES.WALK_COMPLETED_4K",			0x49, 0x02, true },
    370 	{ "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",			0x49, 0x04, true },
    371 	{ "DTLB_STORE_MISSES.WALK_COMPLETED_1G",			0x49, 0x08, true },
    372 	{ "DTLB_STORE_MISSES.WALK_COMPLETED",				0x49, 0x0E, true },
    373 	{ "DTLB_STORE_MISSES.WALK_PENDING",				0x49, 0x10, true },
    374 	{ "DTLB_STORE_MISSES.STLB_HIT",					0x49, 0x20, true },
    375 	{ "LOAD_HIT_PRE.SW_PF",						0x4C, 0x01, true },
    376 	{ "EPT.WALK_PENDING",						0x4F, 0x10, true },
    377 	{ "L1D.REPLACEMENT",						0x51, 0x01, true },
    378 	{ "RS_EVENTS.EMPTY_CYCLES",					0x5E, 0x01, true },
    379 	{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",		0x60, 0x01, true },
    380 	{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",		0x60, 0x02, true },
    381 	{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",			0x60, 0x04, true },
    382 	{ "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",			0x60, 0x08, true },
    383 	{ "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",	0x60, 0x10, true },
    384 	{ "IDQ.MITE_UOPS",						0x79, 0x04, true },
    385 	{ "IDQ.DSB_UOPS",						0x79, 0x08, true },
    386 	{ "IDQ.MS_MITE_UOPS",						0x79, 0x20, true },
    387 	{ "IDQ.MS_UOPS",						0x79, 0x30, true },
    388 	{ "ICACHE_16B.IFDATA_STALL",					0x80, 0x04, true },
    389 	{ "ICACHE_64B.IFTAG_HIT",					0x83, 0x01, true },
    390 	{ "ICACHE_64B.IFTAG_MISS",					0x83, 0x02, true },
    391 	{ "ICACHE_64B.IFTAG_STALL",					0x83, 0x04, true },
    392 	{ "ITLB_MISSES.MISS_CAUSES_A_WALK",				0x85, 0x01, true },
    393 	{ "ITLB_MISSES.WALK_COMPLETED_4K",				0x85, 0x02, true },
    394 	{ "ITLB_MISSES.WALK_COMPLETED_2M_4M",				0x85, 0x04, true },
    395 	{ "ITLB_MISSES.WALK_COMPLETED_1G",				0x85, 0x08, true },
    396 	{ "ITLB_MISSES.WALK_COMPLETED",					0x85, 0x0E, true },
    397 	{ "ITLB_MISSES.WALK_PENDING",					0x85, 0x10, true },
    398 	{ "ITLB_MISSES.STLB_HIT",					0x85, 0x20, true },
    399 	{ "ILD_STALL.LCP",						0x87, 0x01, true },
    400 	{ "IDQ_UOPS_NOT_DELIVERED.CORE",				0x9C, 0x01, true },
    401 	{ "RESOURCE_STALLS.ANY",					0xA2, 0x01, true },
    402 	{ "RESOURCE_STALLS.SB",						0xA2, 0x08, true },
    403 	{ "EXE_ACTIVITY.EXE_BOUND_0_PORTS",				0xA6, 0x01, true },
    404 	{ "EXE_ACTIVITY.1_PORTS_UTIL",					0xA6, 0x02, true },
    405 	{ "EXE_ACTIVITY.2_PORTS_UTIL",					0xA6, 0x04, true },
    406 	{ "EXE_ACTIVITY.3_PORTS_UTIL",					0xA6, 0x08, true },
    407 	{ "EXE_ACTIVITY.4_PORTS_UTIL",					0xA6, 0x10, true },
    408 	{ "EXE_ACTIVITY.BOUND_ON_STORES",				0xA6, 0x40, true },
    409 	{ "LSD.UOPS",							0xA8, 0x01, true },
    410 	{ "DSB2MITE_SWITCHES.PENALTY_CYCLES",				0xAB, 0x02, true },
    411 	{ "ITLB.ITLB_FLUSH",						0xAE, 0x01, true },
    412 	{ "OFFCORE_REQUESTS.DEMAND_DATA_RD",				0xB0, 0x01, true },
    413 	{ "OFFCORE_REQUESTS.DEMAND_CODE_RD",				0xB0, 0x02, true },
    414 	{ "OFFCORE_REQUESTS.DEMAND_RFO",				0xB0, 0x04, true },
    415 	{ "OFFCORE_REQUESTS.ALL_DATA_RD",				0xB0, 0x08, true },
    416 	{ "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",			0xB0, 0x10, true },
    417 	{ "OFFCORE_REQUESTS.ALL_REQUESTS",				0xB0, 0x80, true },
    418 	{ "UOPS_EXECUTED.THREAD",					0xB1, 0x01, true },
    419 	{ "UOPS_EXECUTED.CORE",						0xB1, 0x02, true },
    420 	{ "UOPS_EXECUTED.X87",						0xB1, 0x10, true },
    421 	{ "OFFCORE_REQUESTS_BUFFER.SQ_FULL",				0xB2, 0x01, true },
    422 	{ "TLB_FLUSH.DTLB_THREAD",					0xBD, 0x01, true },
    423 	{ "TLB_FLUSH.STLB_ANY",						0xBD, 0x20, true },
    424 	{ "INST_RETIRED.PREC_DIST",					0xC0, 0x01, true },
    425 	{ "OTHER_ASSISTS.ANY",						0xC1, 0x3F, true },
    426 	{ "UOPS_RETIRED.RETIRE_SLOTS",					0xC2, 0x02, true },
    427 	{ "MACHINE_CLEARS.MEMORY_ORDERING",				0xC3, 0x02, true },
    428 	{ "MACHINE_CLEARS.SMC",						0xC3, 0x04, true },
    429 	{ "BR_INST_RETIRED.CONDITIONAL",				0xC4, 0x01, true },
    430 	{ "BR_INST_RETIRED.NEAR_CALL",					0xC4, 0x02, true },
    431 	{ "BR_INST_RETIRED.NEAR_RETURN",				0xC4, 0x08, true },
    432 	{ "BR_INST_RETIRED.NOT_TAKEN",					0xC4, 0x10, true },
    433 	{ "BR_INST_RETIRED.NEAR_TAKEN",					0xC4, 0x20, true },
    434 	{ "BR_INST_RETIRED.FAR_BRANCH",					0xC4, 0x40, true },
    435 	{ "BR_MISP_RETIRED.CONDITIONAL",				0xC5, 0x01, true },
    436 	{ "BR_MISP_RETIRED.NEAR_CALL",					0xC5, 0x02, true },
    437 	{ "BR_MISP_RETIRED.NEAR_TAKEN",					0xC5, 0x20, true },
    438 	{ "HW_INTERRUPTS.RECEIVED",					0xCB, 0x01, true },
    439 	{ "MEM_INST_RETIRED.STLB_MISS_LOADS",				0xD0, 0x11, true },
    440 	{ "MEM_INST_RETIRED.STLB_MISS_STORES",				0xD0, 0x12, true },
    441 	{ "MEM_INST_RETIRED.LOCK_LOADS",				0xD0, 0x21, true },
    442 	{ "MEM_INST_RETIRED.SPLIT_LOADS",				0xD0, 0x41, true },
    443 	{ "MEM_INST_RETIRED.SPLIT_STORES",				0xD0, 0x42, true },
    444 	{ "MEM_INST_RETIRED.ALL_LOADS",					0xD0, 0x81, true },
    445 	{ "MEM_INST_RETIRED.ALL_STORES",				0xD0, 0x82, true },
    446 	{ "MEM_LOAD_RETIRED.L1_HIT",					0xD1, 0x01, true },
    447 	{ "MEM_LOAD_RETIRED.L2_HIT",					0xD1, 0x02, true },
    448 	{ "MEM_LOAD_RETIRED.L3_HIT",					0xD1, 0x04, true },
    449 	{ "MEM_LOAD_RETIRED.L1_MISS",					0xD1, 0x08, true },
    450 	{ "MEM_LOAD_RETIRED.L2_MISS",					0xD1, 0x10, true },
    451 	{ "MEM_LOAD_RETIRED.L3_MISS",					0xD1, 0x20, true },
    452 	{ "MEM_LOAD_RETIRED.FB_HIT",					0xD1, 0x40, true },
    453 	{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",				0xD2, 0x01, true },
    454 	{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",				0xD2, 0x02, true },
    455 	{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",				0xD2, 0x04, true },
    456 	{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",				0xD2, 0x08, true },
    457 	{ "MEM_LOAD_MISC_RETIRED.UC",					0xD4, 0x04, true },
    458 	{ "BACLEARS.ANY",						0xE6, 0x01, true },
    459 	{ "L2_TRANS.L2_WB",						0xF0, 0x40, true },
    460 	{ "L2_LINES_IN.ALL",						0xF1, 0x1F, true },
    461 	{ "L2_LINES_OUT.SILENT",					0xF2, 0x01, true },
    462 	{ "L2_LINES_OUT.NON_SILENT",					0xF2, 0x02, true },
    463 	{ "L2_LINES_OUT.USELESS_HWPF",					0xF2, 0x04, true },
    464 	{ "SQ_MISC.SPLIT_LOCK",						0xF4, 0x10, true },
    465 };
    466 
    467 static struct event_table intel_skylake_kabylake = {
    468 	.tablename = "Intel Skylake/Kabylake",
    469 	.names = intel_skylake_kabylake_names,
    470 	.nevents = sizeof(intel_skylake_kabylake_names) /
    471 	    sizeof(struct name_to_event),
    472 	.next = NULL
    473 };
    474 
    475 static struct event_table *
    476 init_intel_skylake_kabylake(void)
    477 {
    478 	return &intel_skylake_kabylake;
    479 }
    480 
    481 static struct event_table *
    482 init_intel_generic(void)
    483 {
    484 	unsigned int eax, ebx, ecx, edx;
    485 	struct event_table *table;
    486 
    487 	/*
    488 	 * The kernel made sure the Architectural Version 1 PMCs were
    489 	 * present.
    490 	 */
    491 	table = init_intel_arch1();
    492 
    493 	/*
    494 	 * Now query the additional (non-architectural) events. They
    495 	 * depend on the CPU model.
    496 	 */
    497 	eax = 0x01;
    498 	ebx = 0;
    499 	ecx = 0;
    500 	edx = 0;
    501 	x86_cpuid(&eax, &ebx, &ecx, &edx);
    502 
    503 	if (CPUID_TO_FAMILY(eax) == 6) {
    504 		switch (CPUID_TO_MODEL(eax)) {
    505 		case 0x37: /* Silvermont (Bay Trail) */
    506 		case 0x4A: /* Silvermont (Tangier) */
    507 		case 0x4C: /* Airmont (Braswell, Cherry Trail) */
    508 		case 0x4D: /* Silvermont (Avoton, Rangeley) */
    509 		case 0x5A: /* Silvermont (Anniedale) */
    510 		case 0x5D: /* Silvermont (SoFIA) */
    511 			table->next = init_intel_silvermont_airmont();
    512 			break;
    513 		case 0x5C: /* Goldmont (Apollo Lake) */
    514 		case 0x5F: /* Goldmont (Denvertion) */
    515 			table->next = init_intel_goldmont();
    516 			break;
    517 		case 0x4E: /* Skylake */
    518 		case 0x5E: /* Skylake */
    519 		case 0x8E: /* Kabylake */
    520 		case 0x9E: /* Kabylake */
    521 			table->next = init_intel_skylake_kabylake();
    522 			break;
    523 		}
    524 	}
    525 
    526 	return table;
    527 }
    528 
    529 /* -------------------------------------------------------------------------- */
    530 
    531 /*
    532  * AMD Family 10h
    533  */
    534 static struct name_to_event amd_f10h_names[] = {
    535 	{ "seg-load-all",		0x20, 0x7f, true },
    536 	{ "seg-load-es",		0x20, 0x01, true },
    537 	{ "seg-load-cs",		0x20, 0x02, true },
    538 	{ "seg-load-ss",		0x20, 0x04, true },
    539 	{ "seg-load-ds",		0x20, 0x08, true },
    540 	{ "seg-load-fs",		0x20, 0x10, true },
    541 	{ "seg-load-gs",		0x20, 0x20, true },
    542 	{ "seg-load-hs",		0x20, 0x40, true },
    543 	{ "l1cache-access",		0x40, 0x00, true },
    544 	{ "l1cache-miss",		0x41, 0x00, true },
    545 	{ "l1cache-refill",		0x42, 0x1f, true },
    546 	{ "l1cache-refill-invalid",	0x42, 0x01, true },
    547 	{ "l1cache-refill-shared",	0x42, 0x02, true },
    548 	{ "l1cache-refill-exclusive",	0x42, 0x04, true },
    549 	{ "l1cache-refill-owner",	0x42, 0x08, true },
    550 	{ "l1cache-refill-modified",	0x42, 0x10, true },
    551 	{ "l1cache-load",		0x43, 0x1f, true },
    552 	{ "l1cache-load-invalid",	0x43, 0x01, true },
    553 	{ "l1cache-load-shared",	0x43, 0x02, true },
    554 	{ "l1cache-load-exclusive",	0x43, 0x04, true },
    555 	{ "l1cache-load-owner",		0x43, 0x08, true },
    556 	{ "l1cache-load-modified",	0x43, 0x10, true },
    557 	{ "l1cache-writeback",		0x44, 0x1f, true },
    558 	{ "l1cache-writeback-invalid",	0x44, 0x01, true },
    559 	{ "l1cache-writeback-shared",	0x44, 0x02, true },
    560 	{ "l1cache-writeback-exclusive",0x44, 0x04, true },
    561 	{ "l1cache-writeback-owner",	0x44, 0x08, true },
    562 	{ "l1cache-writeback-modified",	0x44, 0x10, true },
    563 	{ "l1DTLB-hit-all",		0x4D, 0x07, true },
    564 	{ "l1DTLB-hit-4Kpage",		0x4D, 0x01, true },
    565 	{ "l1DTLB-hit-2Mpage",		0x4D, 0x02, true },
    566 	{ "l1DTLB-hit-1Gpage",		0x4D, 0x04, true },
    567 	{ "l1DTLB-miss-all",		0x45, 0x07, true },
    568 	{ "l1DTLB-miss-4Kpage",		0x45, 0x01, true },
    569 	{ "l1DTLB-miss-2Mpage",		0x45, 0x02, true },
    570 	{ "l1DTLB-miss-1Gpage",		0x45, 0x04, true },
    571 	{ "l2DTLB-miss-all",		0x46, 0x03, true },
    572 	{ "l2DTLB-miss-4Kpage",		0x46, 0x01, true },
    573 	{ "l2DTLB-miss-2Mpage",		0x46, 0x02, true },
    574 	/* l2DTLB-miss-1Gpage: reserved on some revisions, so disabled */
    575 	{ "l1ITLB-miss",		0x84, 0x00, true },
    576 	{ "l2ITLB-miss-all",		0x85, 0x03, true },
    577 	{ "l2ITLB-miss-4Kpage",		0x85, 0x01, true },
    578 	{ "l2ITLB-miss-2Mpage",		0x85, 0x02, true },
    579 	{ "mem-misalign-ref",		0x47, 0x00, true },
    580 	{ "ins-fetch",			0x80, 0x00, true },
    581 	{ "ins-fetch-miss",		0x81, 0x00, true },
    582 	{ "ins-refill-l2",		0x82, 0x00, true },
    583 	{ "ins-refill-sys",		0x83, 0x00, true },
    584 	{ "ins-fetch-stall",		0x87, 0x00, true },
    585 	{ "ins-retired",		0xC0, 0x00, true },
    586 	{ "ins-empty",			0xD0, 0x00, true },
    587 	{ "ops-retired",		0xC1, 0x00, true },
    588 	{ "branch-retired",		0xC2, 0x00, true },
    589 	{ "branch-miss-retired",	0xC3, 0x00, true },
    590 	{ "branch-taken-retired",	0xC4, 0x00, true },
    591 	{ "branch-taken-miss-retired",	0xC5, 0x00, true },
    592 	{ "branch-far-retired",		0xC6, 0x00, true },
    593 	{ "branch-resync-retired",	0xC7, 0x00, true },
    594 	{ "branch-near-retired",	0xC8, 0x00, true },
    595 	{ "branch-near-miss-retired",	0xC9, 0x00, true },
    596 	{ "branch-indirect-miss-retired", 0xCA, 0x00, true },
    597 	{ "int-hw",			0xCF, 0x00, true },
    598 	{ "int-cycles-masked",		0xCD, 0x00, true },
    599 	{ "int-cycles-masked-pending",	0xCE, 0x00, true },
    600 	{ "fpu-exceptions",		0xDB, 0x00, true },
    601 	{ "break-match0",		0xDC, 0x00, true },
    602 	{ "break-match1",		0xDD, 0x00, true },
    603 	{ "break-match2",		0xDE, 0x00, true },
    604 	{ "break-match3",		0xDF, 0x00, true },
    605 };
    606 
    607 static struct event_table amd_f10h = {
    608 	.tablename = "AMD Family 10h",
    609 	.names = amd_f10h_names,
    610 	.nevents = sizeof(amd_f10h_names) /
    611 	    sizeof(struct name_to_event),
    612 	.next = NULL
    613 };
    614 
    615 static struct event_table *
    616 init_amd_f10h(void)
    617 {
    618 	return &amd_f10h;
    619 }
    620 
    621 static struct event_table *
    622 init_amd_generic(void)
    623 {
    624 	unsigned int eax, ebx, ecx, edx;
    625 
    626 	eax = 0x01;
    627 	ebx = 0;
    628 	ecx = 0;
    629 	edx = 0;
    630 	x86_cpuid(&eax, &ebx, &ecx, &edx);
    631 
    632 	switch (CPUID_TO_FAMILY(eax)) {
    633 	case 0x10:
    634 		return init_amd_f10h();
    635 	}
    636 
    637 	return NULL;
    638 }
    639 
    640 /* -------------------------------------------------------------------------- */
    641 
    642 int
    643 tprof_event_init(uint32_t ident)
    644 {
    645 	switch (ident) {
    646 	case TPROF_IDENT_NONE:
    647 		return -1;
    648 	case TPROF_IDENT_INTEL_GENERIC:
    649 		cpuevents = init_intel_generic();
    650 		break;
    651 	case TPROF_IDENT_AMD_GENERIC:
    652 		cpuevents = init_amd_generic();
    653 		break;
    654 	}
    655 	return (cpuevents == NULL) ? -1 : 0;
    656 }
    657 
    658 static void
    659 recursive_event_list(struct event_table *table)
    660 {
    661 	size_t i;
    662 
    663 	printf("%s:\n", table->tablename);
    664 	for (i = 0; i < table->nevents; i++) {
    665 		if (!table->names[i].enabled)
    666 			continue;
    667 		printf("\t%s\n", table->names[i].name);
    668 	}
    669 
    670 	if (table->next != NULL) {
    671 		recursive_event_list(table->next);
    672 	}
    673 }
    674 
    675 void
    676 tprof_event_list(void)
    677 {
    678 	recursive_event_list(cpuevents);
    679 }
    680 
    681 static void
    682 recursive_event_lookup(struct event_table *table, const char *name,
    683     struct tprof_param *param)
    684 {
    685 	size_t i;
    686 
    687 	for (i = 0; i < table->nevents; i++) {
    688 		if (!table->names[i].enabled)
    689 			continue;
    690 		if (!strcmp(table->names[i].name, name)) {
    691 			param->p_event = table->names[i].event;
    692 			param->p_unit = table->names[i].unit;
    693 			return;
    694 		}
    695 	}
    696 
    697 	if (table->next != NULL) {
    698 		recursive_event_lookup(table->next, name, param);
    699 	} else {
    700 		errx(EXIT_FAILURE, "event '%s' unknown", name);
    701 	}
    702 }
    703 
    704 void
    705 tprof_event_lookup(const char *name, struct tprof_param *param)
    706 {
    707 	recursive_event_lookup(cpuevents, name, param);
    708 }
    709