1/* 2 * Copyright © 2007-2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27/** 28**************************************************************************************************** 29* @file addrinterface.h 30* @brief Contains the addrlib interfaces declaration and parameter defines 31**************************************************************************************************** 32*/ 33#ifndef __ADDR_INTERFACE_H__ 34#define __ADDR_INTERFACE_H__ 35 36#include "addrtypes.h" 37 38#if defined(__cplusplus) 39extern "C" 40{ 41#endif 42 43#define ADDRLIB_VERSION_MAJOR 6 44#define ADDRLIB_VERSION_MINOR 2 45#define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR) 46 47/// Virtually all interface functions need ADDR_HANDLE as first parameter 48#ifndef ADDR_HANDLE_TYPEDEF 49#define ADDR_HANDLE_TYPEDEF 50typedef VOID* ADDR_HANDLE; 51#endif 52 53/// Client handle used in callbacks 54typedef VOID* ADDR_CLIENT_HANDLE; 55 56/** 57* ///////////////////////////////////////////////////////////////////////////////////////////////// 58* // Callback functions 59* ///////////////////////////////////////////////////////////////////////////////////////////////// 60* typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 61* const ADDR_ALLOCSYSMEM_INPUT* pInput); 62* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 63* VOID* pVirtAddr); 64* typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 65* const ADDR_DEBUGPRINT_INPUT* pInput); 66* 67* ///////////////////////////////////////////////////////////////////////////////////////////////// 68* // Create/Destroy/Config functions 69* ///////////////////////////////////////////////////////////////////////////////////////////////// 70* AddrCreate() 71* AddrDestroy() 72* 73* ///////////////////////////////////////////////////////////////////////////////////////////////// 74* // Surface functions 75* ///////////////////////////////////////////////////////////////////////////////////////////////// 76* AddrComputeSurfaceInfo() 77* AddrComputeSurfaceAddrFromCoord() 78* AddrComputeSurfaceCoordFromAddr() 79* 80* ///////////////////////////////////////////////////////////////////////////////////////////////// 81* // HTile functions 82* ///////////////////////////////////////////////////////////////////////////////////////////////// 83* AddrComputeHtileInfo() 84* AddrComputeHtileAddrFromCoord() 85* AddrComputeHtileCoordFromAddr() 86* 87* ///////////////////////////////////////////////////////////////////////////////////////////////// 88* // C-mask functions 89* ///////////////////////////////////////////////////////////////////////////////////////////////// 90* AddrComputeCmaskInfo() 91* AddrComputeCmaskAddrFromCoord() 92* AddrComputeCmaskCoordFromAddr() 93* 94* ///////////////////////////////////////////////////////////////////////////////////////////////// 95* // F-mask functions 96* ///////////////////////////////////////////////////////////////////////////////////////////////// 97* AddrComputeFmaskInfo() 98* AddrComputeFmaskAddrFromCoord() 99* AddrComputeFmaskCoordFromAddr() 100* 101* ///////////////////////////////////////////////////////////////////////////////////////////////// 102* // Element/Utility functions 103* ///////////////////////////////////////////////////////////////////////////////////////////////// 104* ElemFlt32ToDepthPixel() 105* ElemFlt32ToColorPixel() 106* AddrExtractBankPipeSwizzle() 107* AddrCombineBankPipeSwizzle() 108* AddrComputeSliceSwizzle() 109* AddrConvertTileInfoToHW() 110* AddrConvertTileIndex() 111* AddrConvertTileIndex1() 112* AddrGetTileIndex() 113* AddrComputeBaseSwizzle() 114* AddrUseTileIndex() 115* AddrUseCombinedSwizzle() 116* 117**/ 118 119//////////////////////////////////////////////////////////////////////////////////////////////////// 120// Callback functions 121//////////////////////////////////////////////////////////////////////////////////////////////////// 122 123/** 124**************************************************************************************************** 125* @brief channel setting structure 126**************************************************************************************************** 127*/ 128typedef union _ADDR_CHANNEL_SETTING 129{ 130 struct 131 { 132 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 133 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel 134 UINT_8 index : 5; ///< Channel index 135 }; 136 UINT_8 value; ///< Value 137} ADDR_CHANNEL_SETTING; 138 139/** 140**************************************************************************************************** 141* @brief address equation key structure 142**************************************************************************************************** 143*/ 144typedef union _ADDR_EQUATION_KEY 145{ 146 struct 147 { 148 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 149 UINT_32 tileMode : 5; ///< Tile mode 150 UINT_32 microTileType : 3; ///< Micro tile type 151 UINT_32 pipeConfig : 5; ///< pipe config 152 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 153 UINT_32 bankWidth : 4; ///< Bank width 154 UINT_32 bankHeight : 4; ///< Bank height 155 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 156 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 157 UINT_32 reserved : 1; ///< Reserved bit 158 } fields; 159 UINT_32 value; 160} ADDR_EQUATION_KEY; 161 162/** 163**************************************************************************************************** 164* @brief address equation structure 165**************************************************************************************************** 166*/ 167#define ADDR_MAX_EQUATION_BIT 20u 168 169// Invalid equation index 170#define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 171 172typedef struct _ADDR_EQUATION 173{ 174 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 175 ///< each bit is result of addr ^ xor ^ xor2 176 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 177 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 178 UINT_32 numBits; ///< The number of bits in equation 179 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 180 ///< stacked vertically prior to swizzling 181} ADDR_EQUATION; 182 183/** 184**************************************************************************************************** 185* @brief Alloc system memory flags. 186* @note These flags are reserved for future use and if flags are added will minimize the impact 187* of the client. 188**************************************************************************************************** 189*/ 190typedef union _ADDR_ALLOCSYSMEM_FLAGS 191{ 192 struct 193 { 194 UINT_32 reserved : 32; ///< Reserved for future use. 195 } fields; 196 UINT_32 value; 197 198} ADDR_ALLOCSYSMEM_FLAGS; 199 200/** 201**************************************************************************************************** 202* @brief Alloc system memory input structure 203**************************************************************************************************** 204*/ 205typedef struct _ADDR_ALLOCSYSMEM_INPUT 206{ 207 UINT_32 size; ///< Size of this structure in bytes 208 209 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 210 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 211 ADDR_CLIENT_HANDLE hClient; ///< Client handle 212} ADDR_ALLOCSYSMEM_INPUT; 213 214/** 215**************************************************************************************************** 216* ADDR_ALLOCSYSMEM 217* @brief 218* Allocate system memory callback function. Returns valid pointer on success. 219**************************************************************************************************** 220*/ 221typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 222 const ADDR_ALLOCSYSMEM_INPUT* pInput); 223 224/** 225**************************************************************************************************** 226* @brief Free system memory input structure 227**************************************************************************************************** 228*/ 229typedef struct _ADDR_FREESYSMEM_INPUT 230{ 231 UINT_32 size; ///< Size of this structure in bytes 232 233 VOID* pVirtAddr; ///< Virtual address 234 ADDR_CLIENT_HANDLE hClient; ///< Client handle 235} ADDR_FREESYSMEM_INPUT; 236 237/** 238**************************************************************************************************** 239* ADDR_FREESYSMEM 240* @brief 241* Free system memory callback function. 242* Returns ADDR_OK on success. 243**************************************************************************************************** 244*/ 245typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 246 const ADDR_FREESYSMEM_INPUT* pInput); 247 248/** 249**************************************************************************************************** 250* @brief Print debug message input structure 251**************************************************************************************************** 252*/ 253typedef struct _ADDR_DEBUGPRINT_INPUT 254{ 255 UINT_32 size; ///< Size of this structure in bytes 256 257 CHAR* pDebugString; ///< Debug print string 258 va_list ap; ///< Variable argument list 259 ADDR_CLIENT_HANDLE hClient; ///< Client handle 260} ADDR_DEBUGPRINT_INPUT; 261 262/** 263**************************************************************************************************** 264* ADDR_DEBUGPRINT 265* @brief 266* Print debug message callback function. 267* Returns ADDR_OK on success. 268**************************************************************************************************** 269*/ 270typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 271 const ADDR_DEBUGPRINT_INPUT* pInput); 272 273/** 274**************************************************************************************************** 275* ADDR_CALLBACKS 276* 277* @brief 278* Address Library needs client to provide system memory alloc/free routines. 279**************************************************************************************************** 280*/ 281typedef struct _ADDR_CALLBACKS 282{ 283 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 284 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 285 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 286} ADDR_CALLBACKS; 287 288//////////////////////////////////////////////////////////////////////////////////////////////////// 289// Create/Destroy functions 290//////////////////////////////////////////////////////////////////////////////////////////////////// 291 292/** 293**************************************************************************************************** 294* ADDR_CREATE_FLAGS 295* 296* @brief 297* This structure is used to pass some setup in creation of AddrLib 298* @note 299**************************************************************************************************** 300*/ 301typedef union _ADDR_CREATE_FLAGS 302{ 303 struct 304 { 305 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 306 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 307 /// output structure 308 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 309 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 310 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 311 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 312 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 313 UINT_32 reserved : 25; ///< Reserved bits for future use 314 }; 315 316 UINT_32 value; 317} ADDR_CREATE_FLAGS; 318 319/** 320**************************************************************************************************** 321* ADDR_REGISTER_VALUE 322* 323* @brief 324* Data from registers to setup AddrLib global data, used in AddrCreate 325**************************************************************************************************** 326*/ 327typedef struct _ADDR_REGISTER_VALUE 328{ 329 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 330 /// For R6xx/R7xx, use GB_TILING_CONFIG. 331 /// But they can be treated as the same. 332 /// if this value is 0, use chip to set default value 333 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 334 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 335 336 /// R800 registers----------------------------------------------- 337 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 338 /// No enums for this value in h/w header files 339 /// 0: 4 340 /// 1: 8 341 /// 2: 16 342 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 343 /// 0: 1 344 /// 1: 2 345 /// SI (R1000) registers----------------------------------------- 346 const UINT_32* pTileConfig; ///< Global tile setting tables 347 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 348 349 ///< CI registers------------------------------------------------- 350 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 351 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 352 353 ///< GFX9 HW parameters 354 UINT_32 blockVarSizeLog2; ///< SW_VAR_* block size 355} ADDR_REGISTER_VALUE; 356 357/** 358**************************************************************************************************** 359* ADDR_CREATE_INPUT 360* 361* @brief 362* Parameters use to create an AddrLib Object. Caller must provide all fields. 363* 364**************************************************************************************************** 365*/ 366typedef struct _ADDR_CREATE_INPUT 367{ 368 UINT_32 size; ///< Size of this structure in bytes 369 370 UINT_32 chipEngine; ///< Chip Engine 371 UINT_32 chipFamily; ///< Chip Family 372 UINT_32 chipRevision; ///< Chip Revision 373 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 374 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 375 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 376 ADDR_CLIENT_HANDLE hClient; ///< Client handle 377 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 378} ADDR_CREATE_INPUT; 379 380/** 381**************************************************************************************************** 382* ADDR_CREATEINFO_OUTPUT 383* 384* @brief 385* Return AddrLib handle to client driver 386* 387**************************************************************************************************** 388*/ 389typedef struct _ADDR_CREATE_OUTPUT 390{ 391 UINT_32 size; ///< Size of this structure in bytes 392 393 ADDR_HANDLE hLib; ///< Address lib handle 394 395 UINT_32 numEquations; ///< Number of equations in the table 396 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 397} ADDR_CREATE_OUTPUT; 398 399/** 400**************************************************************************************************** 401* AddrCreate 402* 403* @brief 404* Create AddrLib object, must be called before any interface calls 405* 406* @return 407* ADDR_OK if successful 408**************************************************************************************************** 409*/ 410ADDR_E_RETURNCODE ADDR_API AddrCreate( 411 const ADDR_CREATE_INPUT* pAddrCreateIn, 412 ADDR_CREATE_OUTPUT* pAddrCreateOut); 413 414/** 415**************************************************************************************************** 416* AddrDestroy 417* 418* @brief 419* Destroy AddrLib object, must be called to free internally allocated resources. 420* 421* @return 422* ADDR_OK if successful 423**************************************************************************************************** 424*/ 425ADDR_E_RETURNCODE ADDR_API AddrDestroy( 426 ADDR_HANDLE hLib); 427 428//////////////////////////////////////////////////////////////////////////////////////////////////// 429// Surface functions 430//////////////////////////////////////////////////////////////////////////////////////////////////// 431 432/** 433**************************************************************************************************** 434* @brief 435* Bank/tiling parameters. On function input, these can be set as desired or 436* left 0 for AddrLib to calculate/default. On function output, these are the actual 437* parameters used. 438* @note 439* Valid bankWidth/bankHeight value: 440* 1,2,4,8. They are factors instead of pixels or bytes. 441* 442* The bank number remains constant across each row of the 443* macro tile as each pipe is selected, so the number of 444* tiles in the x direction with the same bank number will 445* be bank_width * num_pipes. 446**************************************************************************************************** 447*/ 448typedef struct _ADDR_TILEINFO 449{ 450 /// Any of these parameters can be set to 0 to use the HW default. 451 UINT_32 banks; ///< Number of banks, numerical value 452 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 453 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 454 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 455 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 456 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 457} ADDR_TILEINFO; 458 459// Create a define to avoid client change. The removal of R800 is because we plan to implement SI 460// within 800 HWL - An AddrPipeCfg is added in above data structure 461typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 462 463/** 464**************************************************************************************************** 465* @brief 466* Information needed by quad buffer stereo support 467**************************************************************************************************** 468*/ 469typedef struct _ADDR_QBSTEREOINFO 470{ 471 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 472 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 473 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 474} ADDR_QBSTEREOINFO; 475 476/** 477**************************************************************************************************** 478* ADDR_SURFACE_FLAGS 479* 480* @brief 481* Surface flags 482**************************************************************************************************** 483*/ 484typedef union _ADDR_SURFACE_FLAGS 485{ 486 struct 487 { 488 UINT_32 color : 1; ///< Flag indicates this is a color buffer 489 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 490 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 491 UINT_32 texture : 1; ///< Flag indicates this is a texture 492 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 493 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 494 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 495 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 496 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 497 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 498 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 499 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 500 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 501 /// i.e. save some memory but may lose performance 502 UINT_32 prt : 1; ///< Flag for partially resident texture 503 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 504 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 505 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 506 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 507 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 508 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 509 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 510 /// dcc can't be enabled if pipe config of tile mode 511 /// is different from that of ASIC, this flag 512 /// is address lib internal flag, client should ignore it 513 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 514 /// This flag indicates we need to follow the 515 /// alignment with CZ families or other ASICs under 516 /// PX configuration + CZ. 517 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 518 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 519 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 520 /// This flag indicates we need to override tile 521 /// mode to PRT_* tile mode to disable slice rotation, 522 /// which is needed by swizzle pattern equation. 523 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 524 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 525 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 526 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 527 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 528 /// to make sure they share same tile config parameters 529 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 530 UINT_32 reserved : 1; ///< Reserved bits 531 }; 532 533 UINT_32 value; 534} ADDR_SURFACE_FLAGS; 535 536/** 537**************************************************************************************************** 538* ADDR_COMPUTE_SURFACE_INFO_INPUT 539* 540* @brief 541* Input structure for AddrComputeSurfaceInfo 542**************************************************************************************************** 543*/ 544typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 545{ 546 UINT_32 size; ///< Size of this structure in bytes 547 548 AddrTileMode tileMode; ///< Tile mode 549 AddrFormat format; ///< If format is set to valid one, bpp/width/height 550 /// might be overwritten 551 UINT_32 bpp; ///< Bits per pixel 552 UINT_32 numSamples; ///< Number of samples 553 UINT_32 width; ///< Width, in pixels 554 UINT_32 height; ///< Height, in pixels 555 UINT_32 numSlices; ///< Number of surface slices or depth 556 UINT_32 slice; ///< Slice index 557 UINT_32 mipLevel; ///< Current mipmap level 558 UINT_32 numMipLevels; ///< Number of mips in mip chain 559 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 560 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 561 /// number of samples for normal AA; Set it to the 562 /// number of fragments for EQAA 563 /// r800 and later HWL parameters 564 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 565 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 566 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 567 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 568 /// while the global useTileIndex is set to 1 569 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 570 /// must for mip levels from SI+. 571 /// Don't use pitch in blocks for compressed formats! 572 UINT_32 maxBaseAlign; ///< Max base alignment request from client 573 UINT_32 pitchAlign; ///< Pitch alignment request from client 574 UINT_32 heightAlign; ///< Height alignment request from client 575} ADDR_COMPUTE_SURFACE_INFO_INPUT; 576 577/** 578**************************************************************************************************** 579* ADDR_COMPUTE_SURFACE_INFO_OUTPUT 580* 581* @brief 582* Output structure for AddrComputeSurfInfo 583* @note 584 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 585 Pixel: Original pixel 586**************************************************************************************************** 587*/ 588typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 589{ 590 UINT_32 size; ///< Size of this structure in bytes 591 592 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 593 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 594 UINT_32 depth; ///< Number of slice/depth 595 UINT_64 surfSize; ///< Surface size in bytes 596 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 597 UINT_32 baseAlign; ///< Base address alignment 598 UINT_32 pitchAlign; ///< Pitch alignment, in elements 599 UINT_32 heightAlign; ///< Height alignment, in elements 600 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 601 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 602 UINT_32 pixelPitch; ///< Pitch in original pixels 603 UINT_32 pixelHeight; ///< Height in original pixels 604 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 605 UINT_64 sliceSize; ///< Size of slice specified by input's slice 606 /// The result is controlled by surface flags & createFlags 607 /// By default this value equals to surfSize for volume 608 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 609 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 610 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 611 612 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 613 614 /// r800 and later HWL parameters 615 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 616 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 617 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 618 619 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 620 /// Output flags 621 struct 622 { 623 /// Special information to work around SI mipmap swizzle bug UBTS #317508 624 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 625 ///< Only meaningful when create flag checkLast2DLevel is set 626 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 627 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 628 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 629 ///< If address lib return true for mip 0, client should set prt flag 630 ///< for child mips in subsequent compute surface info calls 631 UINT_32 reserved :28; ///< Reserved bits 632 }; 633 634 UINT_32 equationIndex; ///< Equation index in the equation table; 635 636 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 637 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 638 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 639 640 /// Stereo info 641 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 642 643 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 644} ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 645 646/** 647**************************************************************************************************** 648* AddrComputeSurfaceInfo 649* 650* @brief 651* Compute surface width/height/depth/alignments and suitable tiling mode 652**************************************************************************************************** 653*/ 654ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 655 ADDR_HANDLE hLib, 656 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 657 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 658 659/** 660**************************************************************************************************** 661* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 662* 663* @brief 664* Input structure for AddrComputeSurfaceAddrFromCoord 665**************************************************************************************************** 666*/ 667typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 668{ 669 UINT_32 size; ///< Size of this structure in bytes 670 671 UINT_32 x; ///< X coordinate 672 UINT_32 y; ///< Y coordinate 673 UINT_32 slice; ///< Slice index 674 UINT_32 sample; ///< Sample index, use fragment index for EQAA 675 676 UINT_32 bpp; ///< Bits per pixel 677 UINT_32 pitch; ///< Surface pitch, in pixels 678 UINT_32 height; ///< Surface height, in pixels 679 UINT_32 numSlices; ///< Surface depth 680 UINT_32 numSamples; ///< Number of samples 681 682 AddrTileMode tileMode; ///< Tile mode 683 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 684 /// micro tile. Textures can also choose depth sample order 685 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 686 /// the case that components are stored separately 687 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 688 689 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 690 /// number of samples for normal AA; Set it to the 691 /// number of fragments for EQAA 692 /// r800 and later HWL parameters 693 // Used for 1D tiling above 694 AddrTileType tileType; ///< See defintion of AddrTileType 695 struct 696 { 697 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 698 /// only flag. Only non-RT texture can set this to TRUE 699 UINT_32 reserved :31; ///< Reserved for future use. 700 }; 701 // 2D tiling needs following structure 702 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 703 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 704 /// while the global useTileIndex is set to 1 705 union 706 { 707 struct 708 { 709 UINT_32 bankSwizzle; ///< Bank swizzle 710 UINT_32 pipeSwizzle; ///< Pipe swizzle 711 }; 712 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 713 }; 714} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 715 716/** 717**************************************************************************************************** 718* ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 719* 720* @brief 721* Output structure for AddrComputeSurfaceAddrFromCoord 722**************************************************************************************************** 723*/ 724typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 725{ 726 UINT_32 size; ///< Size of this structure in bytes 727 728 UINT_64 addr; ///< Byte address 729 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 730 /// For surface bpp < 8, e.g. FMT_1. 731 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 732} ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 733 734/** 735**************************************************************************************************** 736* AddrComputeSurfaceAddrFromCoord 737* 738* @brief 739* Compute surface address from a given coordinate. 740**************************************************************************************************** 741*/ 742ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 743 ADDR_HANDLE hLib, 744 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 745 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 746 747/** 748**************************************************************************************************** 749* ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 750* 751* @brief 752* Input structure for AddrComputeSurfaceCoordFromAddr 753**************************************************************************************************** 754*/ 755typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 756{ 757 UINT_32 size; ///< Size of this structure in bytes 758 759 UINT_64 addr; ///< Address in bytes 760 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 761 /// e.g. FMT_1; 762 UINT_32 bpp; ///< Bits per pixel 763 UINT_32 pitch; ///< Pitch, in pixels 764 UINT_32 height; ///< Height in pixels 765 UINT_32 numSlices; ///< Surface depth 766 UINT_32 numSamples; ///< Number of samples 767 768 AddrTileMode tileMode; ///< Tile mode 769 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 770 /// Note: Textures can choose depth sample order as well. 771 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 772 /// the case that components are stored separately 773 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 774 775 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 776 /// number of samples for normal AA; Set it to the 777 /// number of fragments for EQAA 778 /// r800 and later HWL parameters 779 // Used for 1D tiling above 780 AddrTileType tileType; ///< See defintion of AddrTileType 781 struct 782 { 783 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 784 /// only flag. Only non-RT texture can set this to TRUE 785 UINT_32 reserved :31; ///< Reserved for future use. 786 }; 787 // 2D tiling needs following structure 788 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 789 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 790 /// while the global useTileIndex is set to 1 791 union 792 { 793 struct 794 { 795 UINT_32 bankSwizzle; ///< Bank swizzle 796 UINT_32 pipeSwizzle; ///< Pipe swizzle 797 }; 798 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 799 }; 800} ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 801 802/** 803**************************************************************************************************** 804* ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 805* 806* @brief 807* Output structure for AddrComputeSurfaceCoordFromAddr 808**************************************************************************************************** 809*/ 810typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 811{ 812 UINT_32 size; ///< Size of this structure in bytes 813 814 UINT_32 x; ///< X coordinate 815 UINT_32 y; ///< Y coordinate 816 UINT_32 slice; ///< Index of slices 817 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 818} ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 819 820/** 821**************************************************************************************************** 822* AddrComputeSurfaceCoordFromAddr 823* 824* @brief 825* Compute coordinate from a given surface address 826**************************************************************************************************** 827*/ 828ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 829 ADDR_HANDLE hLib, 830 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 831 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 832 833//////////////////////////////////////////////////////////////////////////////////////////////////// 834// HTile functions 835//////////////////////////////////////////////////////////////////////////////////////////////////// 836 837/** 838**************************************************************************************************** 839* ADDR_HTILE_FLAGS 840* 841* @brief 842* HTILE flags 843**************************************************************************************************** 844*/ 845typedef union _ADDR_HTILE_FLAGS 846{ 847 struct 848 { 849 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 850 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 851 /// size to 256xBankxPipe when computing tc-compatible 852 /// htile info. 853 UINT_32 reserved : 30; ///< Reserved bits 854 }; 855 856 UINT_32 value; 857} ADDR_HTILE_FLAGS; 858 859/** 860**************************************************************************************************** 861* ADDR_COMPUTE_HTILE_INFO_INPUT 862* 863* @brief 864* Input structure of AddrComputeHtileInfo 865**************************************************************************************************** 866*/ 867typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 868{ 869 UINT_32 size; ///< Size of this structure in bytes 870 871 ADDR_HTILE_FLAGS flags; ///< HTILE flags 872 UINT_32 pitch; ///< Surface pitch, in pixels 873 UINT_32 height; ///< Surface height, in pixels 874 UINT_32 numSlices; ///< Number of slices 875 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 876 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 877 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 878 ADDR_TILEINFO* pTileInfo; ///< Tile info 879 880 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 881 /// while the global useTileIndex is set to 1 882 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 883 ///< README: When tileIndex is not -1, this must be valid 884} ADDR_COMPUTE_HTILE_INFO_INPUT; 885 886/** 887**************************************************************************************************** 888* ADDR_COMPUTE_HTILE_INFO_OUTPUT 889* 890* @brief 891* Output structure of AddrComputeHtileInfo 892**************************************************************************************************** 893*/ 894typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 895{ 896 UINT_32 size; ///< Size of this structure in bytes 897 898 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 899 /// HTile buffer. This might be larger than original depth 900 /// buffer pitch when called with an unaligned pitch. 901 UINT_32 height; ///< Height in pixels, as above 902 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 903 UINT_32 baseAlign; ///< Base alignment 904 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 905 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 906 UINT_32 macroHeight; ///< Macro height in pixels 907 UINT_64 sliceSize; ///< Slice size, in bytes. 908 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 909 /// Compute engine clear can't be used if htile is interleaved 910 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 911 /// next mip level, it also indicates if memory set based 912 /// fast clear can be used for current mip level. 913} ADDR_COMPUTE_HTILE_INFO_OUTPUT; 914 915/** 916**************************************************************************************************** 917* AddrComputeHtileInfo 918* 919* @brief 920* Compute Htile pitch, height, base alignment and size in bytes 921**************************************************************************************************** 922*/ 923ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 924 ADDR_HANDLE hLib, 925 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 926 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 927 928/** 929**************************************************************************************************** 930* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 931* 932* @brief 933* Input structure for AddrComputeHtileAddrFromCoord 934**************************************************************************************************** 935*/ 936typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 937{ 938 UINT_32 size; ///< Size of this structure in bytes 939 940 UINT_32 pitch; ///< Pitch, in pixels 941 UINT_32 height; ///< Height in pixels 942 UINT_32 x; ///< X coordinate 943 UINT_32 y; ///< Y coordinate 944 UINT_32 slice; ///< Index of slice 945 UINT_32 numSlices; ///< Number of slices 946 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 947 ADDR_HTILE_FLAGS flags; ///< htile flags 948 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 949 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 950 ADDR_TILEINFO* pTileInfo; ///< Tile info 951 952 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 953 /// while the global useTileIndex is set to 1 954 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 955 ///< README: When tileIndex is not -1, this must be valid 956 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 957 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 958} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 959 960/** 961**************************************************************************************************** 962* ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 963* 964* @brief 965* Output structure for AddrComputeHtileAddrFromCoord 966**************************************************************************************************** 967*/ 968typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 969{ 970 UINT_32 size; ///< Size of this structure in bytes 971 972 UINT_64 addr; ///< Address in bytes 973 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 974 /// So we keep bitPosition for HTILE as well 975} ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 976 977/** 978**************************************************************************************************** 979* AddrComputeHtileAddrFromCoord 980* 981* @brief 982* Compute Htile address according to coordinates (of depth buffer) 983**************************************************************************************************** 984*/ 985ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 986 ADDR_HANDLE hLib, 987 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 988 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 989 990/** 991**************************************************************************************************** 992* ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 993* 994* @brief 995* Input structure for AddrComputeHtileCoordFromAddr 996**************************************************************************************************** 997*/ 998typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 999{ 1000 UINT_32 size; ///< Size of this structure in bytes 1001 1002 UINT_64 addr; ///< Address 1003 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1004 /// so we keep bitPosition for HTILE as well 1005 UINT_32 pitch; ///< Pitch, in pixels 1006 UINT_32 height; ///< Height, in pixels 1007 UINT_32 numSlices; ///< Number of slices 1008 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1009 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1010 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1011 ADDR_TILEINFO* pTileInfo; ///< Tile info 1012 1013 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1014 /// while the global useTileIndex is set to 1 1015 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1016 ///< README: When tileIndex is not -1, this must be valid 1017} ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1018 1019/** 1020**************************************************************************************************** 1021* ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1022* 1023* @brief 1024* Output structure for AddrComputeHtileCoordFromAddr 1025**************************************************************************************************** 1026*/ 1027typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1028{ 1029 UINT_32 size; ///< Size of this structure in bytes 1030 1031 UINT_32 x; ///< X coordinate 1032 UINT_32 y; ///< Y coordinate 1033 UINT_32 slice; ///< Slice index 1034} ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1035 1036/** 1037**************************************************************************************************** 1038* AddrComputeHtileCoordFromAddr 1039* 1040* @brief 1041* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1042* Htile address 1043**************************************************************************************************** 1044*/ 1045ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1046 ADDR_HANDLE hLib, 1047 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1048 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1049 1050//////////////////////////////////////////////////////////////////////////////////////////////////// 1051// C-mask functions 1052//////////////////////////////////////////////////////////////////////////////////////////////////// 1053 1054/** 1055**************************************************************************************************** 1056* ADDR_CMASK_FLAGS 1057* 1058* @brief 1059* CMASK flags 1060**************************************************************************************************** 1061*/ 1062typedef union _ADDR_CMASK_FLAGS 1063{ 1064 struct 1065 { 1066 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1067 UINT_32 reserved :31; ///< Reserved bits 1068 }; 1069 1070 UINT_32 value; 1071} ADDR_CMASK_FLAGS; 1072 1073/** 1074**************************************************************************************************** 1075* ADDR_COMPUTE_CMASK_INFO_INPUT 1076* 1077* @brief 1078* Input structure of AddrComputeCmaskInfo 1079**************************************************************************************************** 1080*/ 1081typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1082{ 1083 UINT_32 size; ///< Size of this structure in bytes 1084 1085 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1086 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1087 UINT_32 height; ///< Height, in pixels, of color buffer 1088 UINT_32 numSlices; ///< Number of slices, of color buffer 1089 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1090 ADDR_TILEINFO* pTileInfo; ///< Tile info 1091 1092 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1093 /// while the global useTileIndex is set to 1 1094 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1095 ///< README: When tileIndex is not -1, this must be valid 1096} ADDR_COMPUTE_CMASK_INFO_INPUT; 1097 1098/** 1099**************************************************************************************************** 1100* ADDR_COMPUTE_CMASK_INFO_OUTPUT 1101* 1102* @brief 1103* Output structure of AddrComputeCmaskInfo 1104**************************************************************************************************** 1105*/ 1106typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1107{ 1108 UINT_32 size; ///< Size of this structure in bytes 1109 1110 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1111 /// this Cmask matches. The size might be larger than 1112 /// original color buffer pitch when called with 1113 /// an unaligned pitch. 1114 UINT_32 height; ///< Height in pixels, as above 1115 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1116 UINT_32 baseAlign; ///< Base alignment 1117 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1118 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1119 UINT_32 macroHeight; ///< Macro height in pixels 1120 UINT_64 sliceSize; ///< Slice size, in bytes. 1121} ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1122 1123/** 1124**************************************************************************************************** 1125* AddrComputeCmaskInfo 1126* 1127* @brief 1128* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1129* info 1130**************************************************************************************************** 1131*/ 1132ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1133 ADDR_HANDLE hLib, 1134 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1135 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1136 1137/** 1138**************************************************************************************************** 1139* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1140* 1141* @brief 1142* Input structure for AddrComputeCmaskAddrFromCoord 1143* 1144**************************************************************************************************** 1145*/ 1146typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1147{ 1148 UINT_32 size; ///< Size of this structure in bytes 1149 UINT_32 x; ///< X coordinate 1150 UINT_32 y; ///< Y coordinate 1151 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1152 UINT_32 slice; ///< Slice index 1153 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1154 UINT_32 height; ///< Height in pixels, of color buffer 1155 UINT_32 numSlices; ///< Number of slices 1156 UINT_32 bpp; 1157 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1158 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1159 ADDR_TILEINFO* pTileInfo; ///< Tile info 1160 1161 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1162 ///< while the global useTileIndex is set to 1 1163 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1164 ///< README: When tileIndex is not -1, this must be valid 1165} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1166 1167/** 1168**************************************************************************************************** 1169* ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1170* 1171* @brief 1172* Output structure for AddrComputeCmaskAddrFromCoord 1173**************************************************************************************************** 1174*/ 1175typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1176{ 1177 UINT_32 size; ///< Size of this structure in bytes 1178 1179 UINT_64 addr; ///< CMASK address in bytes 1180 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1181 /// so the address may be located in bit 0 (0) or 4 (4) 1182} ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1183 1184/** 1185**************************************************************************************************** 1186* AddrComputeCmaskAddrFromCoord 1187* 1188* @brief 1189* Compute Cmask address according to coordinates (of MSAA color buffer) 1190**************************************************************************************************** 1191*/ 1192ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1193 ADDR_HANDLE hLib, 1194 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1195 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1196 1197/** 1198**************************************************************************************************** 1199* ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1200* 1201* @brief 1202* Input structure for AddrComputeCmaskCoordFromAddr 1203**************************************************************************************************** 1204*/ 1205typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1206{ 1207 UINT_32 size; ///< Size of this structure in bytes 1208 1209 UINT_64 addr; ///< CMASK address in bytes 1210 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1211 /// so the address may be located in bit 0 (0) or 4 (4) 1212 UINT_32 pitch; ///< Pitch, in pixels 1213 UINT_32 height; ///< Height in pixels 1214 UINT_32 numSlices; ///< Number of slices 1215 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1216 ADDR_TILEINFO* pTileInfo; ///< Tile info 1217 1218 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1219 /// while the global useTileIndex is set to 1 1220 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1221 ///< README: When tileIndex is not -1, this must be valid 1222} ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1223 1224/** 1225**************************************************************************************************** 1226* ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1227* 1228* @brief 1229* Output structure for AddrComputeCmaskCoordFromAddr 1230**************************************************************************************************** 1231*/ 1232typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1233{ 1234 UINT_32 size; ///< Size of this structure in bytes 1235 1236 UINT_32 x; ///< X coordinate 1237 UINT_32 y; ///< Y coordinate 1238 UINT_32 slice; ///< Slice index 1239} ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1240 1241/** 1242**************************************************************************************************** 1243* AddrComputeCmaskCoordFromAddr 1244* 1245* @brief 1246* Compute coordinates within color buffer (1st pixel of a micro tile) according to 1247* Cmask address 1248**************************************************************************************************** 1249*/ 1250ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1251 ADDR_HANDLE hLib, 1252 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1253 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1254 1255//////////////////////////////////////////////////////////////////////////////////////////////////// 1256// F-mask functions 1257//////////////////////////////////////////////////////////////////////////////////////////////////// 1258 1259/** 1260**************************************************************************************************** 1261* ADDR_COMPUTE_FMASK_INFO_INPUT 1262* 1263* @brief 1264* Input structure for AddrComputeFmaskInfo 1265**************************************************************************************************** 1266*/ 1267typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1268{ 1269 UINT_32 size; ///< Size of this structure in bytes 1270 1271 AddrTileMode tileMode; ///< Tile mode 1272 UINT_32 pitch; ///< Surface pitch, in pixels 1273 UINT_32 height; ///< Surface height, in pixels 1274 UINT_32 numSlices; ///< Number of slice/depth 1275 UINT_32 numSamples; ///< Number of samples 1276 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1277 /// number of samples for normal AA; Set it to the 1278 /// number of fragments for EQAA 1279 /// r800 and later HWL parameters 1280 struct 1281 { 1282 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1283 /// by H/W clients. S/W should always set it to FALSE. 1284 UINT_32 reserved: 31; ///< Reserved for future use. 1285 }; 1286 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1287 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1288 /// while the global useTileIndex is set to 1 1289} ADDR_COMPUTE_FMASK_INFO_INPUT; 1290 1291/** 1292**************************************************************************************************** 1293* ADDR_COMPUTE_FMASK_INFO_OUTPUT 1294* 1295* @brief 1296* Output structure for AddrComputeFmaskInfo 1297**************************************************************************************************** 1298*/ 1299typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1300{ 1301 UINT_32 size; ///< Size of this structure in bytes 1302 1303 UINT_32 pitch; ///< Pitch of fmask in pixels 1304 UINT_32 height; ///< Height of fmask in pixels 1305 UINT_32 numSlices; ///< Slices of fmask 1306 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1307 UINT_32 baseAlign; ///< Base address alignment 1308 UINT_32 pitchAlign; ///< Pitch alignment 1309 UINT_32 heightAlign; ///< Height alignment 1310 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1311 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1312 /// may be changed in 9xx and above 1313 /// r800 and later HWL parameters 1314 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1315 /// bank_height from color buffer 1316 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1317 /// while the global useTileIndex is set to 1 1318 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1319 UINT_64 sliceSize; ///< Size of slice in bytes 1320} ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1321 1322/** 1323**************************************************************************************************** 1324* AddrComputeFmaskInfo 1325* 1326* @brief 1327* Compute Fmask pitch/height/depth/alignments and size in bytes 1328**************************************************************************************************** 1329*/ 1330ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1331 ADDR_HANDLE hLib, 1332 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1333 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1334 1335/** 1336**************************************************************************************************** 1337* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1338* 1339* @brief 1340* Input structure for AddrComputeFmaskAddrFromCoord 1341**************************************************************************************************** 1342*/ 1343typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1344{ 1345 UINT_32 size; ///< Size of this structure in bytes 1346 1347 UINT_32 x; ///< X coordinate 1348 UINT_32 y; ///< Y coordinate 1349 UINT_32 slice; ///< Slice index 1350 UINT_32 plane; ///< Plane number 1351 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1352 1353 UINT_32 pitch; ///< Surface pitch, in pixels 1354 UINT_32 height; ///< Surface height, in pixels 1355 UINT_32 numSamples; ///< Number of samples 1356 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1357 /// number of samples for normal AA; Set it to the 1358 /// number of fragments for EQAA 1359 1360 AddrTileMode tileMode; ///< Tile mode 1361 union 1362 { 1363 struct 1364 { 1365 UINT_32 bankSwizzle; ///< Bank swizzle 1366 UINT_32 pipeSwizzle; ///< Pipe swizzle 1367 }; 1368 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1369 }; 1370 1371 /// r800 and later HWL parameters 1372 struct 1373 { 1374 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1375 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1376 UINT_32 reserved: 30; ///< Reserved for future use. 1377 }; 1378 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1379 1380} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1381 1382/** 1383**************************************************************************************************** 1384* ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1385* 1386* @brief 1387* Output structure for AddrComputeFmaskAddrFromCoord 1388**************************************************************************************************** 1389*/ 1390typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1391{ 1392 UINT_32 size; ///< Size of this structure in bytes 1393 1394 UINT_64 addr; ///< Fmask address 1395 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1396} ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1397 1398/** 1399**************************************************************************************************** 1400* AddrComputeFmaskAddrFromCoord 1401* 1402* @brief 1403* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1404**************************************************************************************************** 1405*/ 1406ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1407 ADDR_HANDLE hLib, 1408 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1409 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1410 1411/** 1412**************************************************************************************************** 1413* ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1414* 1415* @brief 1416* Input structure for AddrComputeFmaskCoordFromAddr 1417**************************************************************************************************** 1418*/ 1419typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1420{ 1421 UINT_32 size; ///< Size of this structure in bytes 1422 1423 UINT_64 addr; ///< Address 1424 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1425 1426 UINT_32 pitch; ///< Pitch, in pixels 1427 UINT_32 height; ///< Height in pixels 1428 UINT_32 numSamples; ///< Number of samples 1429 UINT_32 numFrags; ///< Number of fragments 1430 AddrTileMode tileMode; ///< Tile mode 1431 union 1432 { 1433 struct 1434 { 1435 UINT_32 bankSwizzle; ///< Bank swizzle 1436 UINT_32 pipeSwizzle; ///< Pipe swizzle 1437 }; 1438 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1439 }; 1440 1441 /// r800 and later HWL parameters 1442 struct 1443 { 1444 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1445 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1446 UINT_32 reserved: 30; ///< Reserved for future use. 1447 }; 1448 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1449 1450} ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1451 1452/** 1453**************************************************************************************************** 1454* ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1455* 1456* @brief 1457* Output structure for AddrComputeFmaskCoordFromAddr 1458**************************************************************************************************** 1459*/ 1460typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1461{ 1462 UINT_32 size; ///< Size of this structure in bytes 1463 1464 UINT_32 x; ///< X coordinate 1465 UINT_32 y; ///< Y coordinate 1466 UINT_32 slice; ///< Slice index 1467 UINT_32 plane; ///< Plane number 1468 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1469} ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1470 1471/** 1472**************************************************************************************************** 1473* AddrComputeFmaskCoordFromAddr 1474* 1475* @brief 1476* Compute FMASK coordinate from an given address 1477**************************************************************************************************** 1478*/ 1479ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1480 ADDR_HANDLE hLib, 1481 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1482 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1483 1484//////////////////////////////////////////////////////////////////////////////////////////////////// 1485// Element/utility functions 1486//////////////////////////////////////////////////////////////////////////////////////////////////// 1487 1488/** 1489**************************************************************************************************** 1490* AddrGetVersion 1491* 1492* @brief 1493* Get AddrLib version number 1494**************************************************************************************************** 1495*/ 1496UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1497 1498/** 1499**************************************************************************************************** 1500* AddrUseTileIndex 1501* 1502* @brief 1503* Return TRUE if tileIndex is enabled in this address library 1504**************************************************************************************************** 1505*/ 1506BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1507 1508/** 1509**************************************************************************************************** 1510* AddrUseCombinedSwizzle 1511* 1512* @brief 1513* Return TRUE if combined swizzle is enabled in this address library 1514**************************************************************************************************** 1515*/ 1516BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1517 1518/** 1519**************************************************************************************************** 1520* ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1521* 1522* @brief 1523* Input structure of AddrExtractBankPipeSwizzle 1524**************************************************************************************************** 1525*/ 1526typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1527{ 1528 UINT_32 size; ///< Size of this structure in bytes 1529 1530 UINT_32 base256b; ///< Base256b value 1531 1532 /// r800 and later HWL parameters 1533 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1534 1535 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1536 /// while the global useTileIndex is set to 1 1537 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1538 ///< README: When tileIndex is not -1, this must be valid 1539} ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1540 1541/** 1542**************************************************************************************************** 1543* ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1544* 1545* @brief 1546* Output structure of AddrExtractBankPipeSwizzle 1547**************************************************************************************************** 1548*/ 1549typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1550{ 1551 UINT_32 size; ///< Size of this structure in bytes 1552 1553 UINT_32 bankSwizzle; ///< Bank swizzle 1554 UINT_32 pipeSwizzle; ///< Pipe swizzle 1555} ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1556 1557/** 1558**************************************************************************************************** 1559* AddrExtractBankPipeSwizzle 1560* 1561* @brief 1562* Extract Bank and Pipe swizzle from base256b 1563* @return 1564* ADDR_OK if no error 1565**************************************************************************************************** 1566*/ 1567ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1568 ADDR_HANDLE hLib, 1569 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1570 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1571 1572/** 1573**************************************************************************************************** 1574* ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1575* 1576* @brief 1577* Input structure of AddrCombineBankPipeSwizzle 1578**************************************************************************************************** 1579*/ 1580typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1581{ 1582 UINT_32 size; ///< Size of this structure in bytes 1583 1584 UINT_32 bankSwizzle; ///< Bank swizzle 1585 UINT_32 pipeSwizzle; ///< Pipe swizzle 1586 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1587 1588 /// r800 and later HWL parameters 1589 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1590 1591 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1592 /// while the global useTileIndex is set to 1 1593 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1594 ///< README: When tileIndex is not -1, this must be valid 1595} ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1596 1597/** 1598**************************************************************************************************** 1599* ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1600* 1601* @brief 1602* Output structure of AddrCombineBankPipeSwizzle 1603**************************************************************************************************** 1604*/ 1605typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1606{ 1607 UINT_32 size; ///< Size of this structure in bytes 1608 1609 UINT_32 tileSwizzle; ///< Combined swizzle 1610} ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1611 1612/** 1613**************************************************************************************************** 1614* AddrCombineBankPipeSwizzle 1615* 1616* @brief 1617* Combine Bank and Pipe swizzle 1618* @return 1619* ADDR_OK if no error 1620* @note 1621* baseAddr here is full MCAddress instead of base256b 1622**************************************************************************************************** 1623*/ 1624ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1625 ADDR_HANDLE hLib, 1626 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1627 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1628 1629/** 1630**************************************************************************************************** 1631* ADDR_COMPUTE_SLICESWIZZLE_INPUT 1632* 1633* @brief 1634* Input structure of AddrComputeSliceSwizzle 1635**************************************************************************************************** 1636*/ 1637typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1638{ 1639 UINT_32 size; ///< Size of this structure in bytes 1640 1641 AddrTileMode tileMode; ///< Tile Mode 1642 UINT_32 baseSwizzle; ///< Base tile swizzle 1643 UINT_32 slice; ///< Slice index 1644 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1645 1646 /// r800 and later HWL parameters 1647 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1648 1649 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1650 /// while the global useTileIndex is set to 1 1651 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1652 ///< README: When tileIndex is not -1, this must be valid 1653} ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1654 1655/** 1656**************************************************************************************************** 1657* ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1658* 1659* @brief 1660* Output structure of AddrComputeSliceSwizzle 1661**************************************************************************************************** 1662*/ 1663typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1664{ 1665 UINT_32 size; ///< Size of this structure in bytes 1666 1667 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1668} ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1669 1670/** 1671**************************************************************************************************** 1672* AddrComputeSliceSwizzle 1673* 1674* @brief 1675* Extract Bank and Pipe swizzle from base256b 1676* @return 1677* ADDR_OK if no error 1678**************************************************************************************************** 1679*/ 1680ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1681 ADDR_HANDLE hLib, 1682 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1683 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1684 1685/** 1686**************************************************************************************************** 1687* AddrSwizzleGenOption 1688* 1689* @brief 1690* Which swizzle generating options: legacy or linear 1691**************************************************************************************************** 1692*/ 1693typedef enum _AddrSwizzleGenOption 1694{ 1695 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1696 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1697} AddrSwizzleGenOption; 1698 1699/** 1700**************************************************************************************************** 1701* AddrSwizzleOption 1702* 1703* @brief 1704* Controls how swizzle is generated 1705**************************************************************************************************** 1706*/ 1707typedef union _ADDR_SWIZZLE_OPTION 1708{ 1709 struct 1710 { 1711 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1712 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1713 UINT_32 reserved :30; ///< Reserved bits 1714 }; 1715 1716 UINT_32 value; 1717 1718} ADDR_SWIZZLE_OPTION; 1719 1720/** 1721**************************************************************************************************** 1722* ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1723* 1724* @brief 1725* Input structure of AddrComputeBaseSwizzle 1726**************************************************************************************************** 1727*/ 1728typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1729{ 1730 UINT_32 size; ///< Size of this structure in bytes 1731 1732 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1733 UINT_32 surfIndex; ///< Index of this surface type 1734 AddrTileMode tileMode; ///< Tile Mode 1735 1736 /// r800 and later HWL parameters 1737 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1738 1739 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1740 /// while the global useTileIndex is set to 1 1741 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1742 ///< README: When tileIndex is not -1, this must be valid 1743} ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1744 1745/** 1746**************************************************************************************************** 1747* ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1748* 1749* @brief 1750* Output structure of AddrComputeBaseSwizzle 1751**************************************************************************************************** 1752*/ 1753typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1754{ 1755 UINT_32 size; ///< Size of this structure in bytes 1756 1757 UINT_32 tileSwizzle; ///< Combined swizzle 1758} ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1759 1760/** 1761**************************************************************************************************** 1762* AddrComputeBaseSwizzle 1763* 1764* @brief 1765* Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1766* @return 1767* ADDR_OK if no error 1768**************************************************************************************************** 1769*/ 1770ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1771 ADDR_HANDLE hLib, 1772 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1773 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1774 1775/** 1776**************************************************************************************************** 1777* ELEM_GETEXPORTNORM_INPUT 1778* 1779* @brief 1780* Input structure for ElemGetExportNorm 1781* 1782**************************************************************************************************** 1783*/ 1784typedef struct _ELEM_GETEXPORTNORM_INPUT 1785{ 1786 UINT_32 size; ///< Size of this structure in bytes 1787 1788 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1789 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1790 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1791 UINT_32 numSamples; ///< Number of samples 1792} ELEM_GETEXPORTNORM_INPUT; 1793 1794/** 1795**************************************************************************************************** 1796* ElemGetExportNorm 1797* 1798* @brief 1799* Helper function to check one format can be EXPORT_NUM, which is a register 1800* CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1801* family 1802* @note 1803* The implementation is only for r600. 1804* 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1805* clocks per export) 1806* 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1807* clock per export) 1808* 1809**************************************************************************************************** 1810*/ 1811BOOL_32 ADDR_API ElemGetExportNorm( 1812 ADDR_HANDLE hLib, 1813 const ELEM_GETEXPORTNORM_INPUT* pIn); 1814 1815/** 1816**************************************************************************************************** 1817* ELEM_FLT32TODEPTHPIXEL_INPUT 1818* 1819* @brief 1820* Input structure for addrFlt32ToDepthPixel 1821* 1822**************************************************************************************************** 1823*/ 1824typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1825{ 1826 UINT_32 size; ///< Size of this structure in bytes 1827 1828 AddrDepthFormat format; ///< Depth buffer format 1829 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1830} ELEM_FLT32TODEPTHPIXEL_INPUT; 1831 1832/** 1833**************************************************************************************************** 1834* ELEM_FLT32TODEPTHPIXEL_INPUT 1835* 1836* @brief 1837* Output structure for ElemFlt32ToDepthPixel 1838* 1839**************************************************************************************************** 1840*/ 1841typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1842{ 1843 UINT_32 size; ///< Size of this structure in bytes 1844 1845 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1846 /// Client must provide enough storage for this type. 1847 UINT_32 depthBase; ///< Tile base in bits for depth bits 1848 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1849 UINT_32 depthBits; ///< Bits for depth 1850 UINT_32 stencilBits; ///< Bits for stencil 1851} ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1852 1853/** 1854**************************************************************************************************** 1855* ElemFlt32ToDepthPixel 1856* 1857* @brief 1858* Convert a FLT_32 value to a depth/stencil pixel value 1859* 1860* @return 1861* Return code 1862* 1863**************************************************************************************************** 1864*/ 1865ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1866 ADDR_HANDLE hLib, 1867 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1868 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1869 1870/** 1871**************************************************************************************************** 1872* ELEM_FLT32TOCOLORPIXEL_INPUT 1873* 1874* @brief 1875* Input structure for addrFlt32ToColorPixel 1876* 1877**************************************************************************************************** 1878*/ 1879typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1880{ 1881 UINT_32 size; ///< Size of this structure in bytes 1882 1883 AddrColorFormat format; ///< Color buffer format 1884 AddrSurfaceNumber surfNum; ///< Surface number 1885 AddrSurfaceSwap surfSwap; ///< Surface swap 1886 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1887} ELEM_FLT32TOCOLORPIXEL_INPUT; 1888 1889/** 1890**************************************************************************************************** 1891* ELEM_FLT32TOCOLORPIXEL_INPUT 1892* 1893* @brief 1894* Output structure for ElemFlt32ToColorPixel 1895* 1896**************************************************************************************************** 1897*/ 1898typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1899{ 1900 UINT_32 size; ///< Size of this structure in bytes 1901 1902 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1903 /// Client must provide enough storage for this type. 1904} ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1905 1906/** 1907**************************************************************************************************** 1908* ElemFlt32ToColorPixel 1909* 1910* @brief 1911* Convert a FLT_32 value to a red/green/blue/alpha pixel value 1912* 1913* @return 1914* Return code 1915* 1916**************************************************************************************************** 1917*/ 1918ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1919 ADDR_HANDLE hLib, 1920 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1921 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1922 1923/** 1924**************************************************************************************************** 1925* ElemSize 1926* 1927* @brief 1928* Get bits-per-element for specified format 1929* 1930* @return 1931* Bits-per-element of specified format 1932* 1933**************************************************************************************************** 1934*/ 1935UINT_32 ADDR_API ElemSize( 1936 ADDR_HANDLE hLib, 1937 AddrFormat format); 1938 1939/** 1940**************************************************************************************************** 1941* ADDR_CONVERT_TILEINFOTOHW_INPUT 1942* 1943* @brief 1944* Input structure for AddrConvertTileInfoToHW 1945* @note 1946* When reverse is TRUE, indices are igonred 1947**************************************************************************************************** 1948*/ 1949typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 1950{ 1951 UINT_32 size; ///< Size of this structure in bytes 1952 BOOL_32 reverse; ///< Convert control flag. 1953 /// FALSE: convert from real value to HW value; 1954 /// TRUE: convert from HW value to real value. 1955 1956 /// r800 and later HWL parameters 1957 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 1958 1959 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1960 /// while the global useTileIndex is set to 1 1961 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1962 ///< README: When tileIndex is not -1, this must be valid 1963 UINT_32 bpp; ///< Bits per pixel 1964} ADDR_CONVERT_TILEINFOTOHW_INPUT; 1965 1966/** 1967**************************************************************************************************** 1968* ADDR_CONVERT_TILEINFOTOHW_OUTPUT 1969* 1970* @brief 1971* Output structure for AddrConvertTileInfoToHW 1972**************************************************************************************************** 1973*/ 1974typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 1975{ 1976 UINT_32 size; ///< Size of this structure in bytes 1977 1978 /// r800 and later HWL parameters 1979 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 1980 1981} ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 1982 1983/** 1984**************************************************************************************************** 1985* AddrConvertTileInfoToHW 1986* 1987* @brief 1988* Convert tile info from real value to hardware register value 1989**************************************************************************************************** 1990*/ 1991ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 1992 ADDR_HANDLE hLib, 1993 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 1994 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 1995 1996/** 1997**************************************************************************************************** 1998* ADDR_CONVERT_TILEINDEX_INPUT 1999* 2000* @brief 2001* Input structure for AddrConvertTileIndex 2002**************************************************************************************************** 2003*/ 2004typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2005{ 2006 UINT_32 size; ///< Size of this structure in bytes 2007 2008 INT_32 tileIndex; ///< Tile index 2009 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2010 UINT_32 bpp; ///< Bits per pixel 2011 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2012} ADDR_CONVERT_TILEINDEX_INPUT; 2013 2014/** 2015**************************************************************************************************** 2016* ADDR_CONVERT_TILEINDEX_OUTPUT 2017* 2018* @brief 2019* Output structure for AddrConvertTileIndex 2020**************************************************************************************************** 2021*/ 2022typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2023{ 2024 UINT_32 size; ///< Size of this structure in bytes 2025 2026 AddrTileMode tileMode; ///< Tile mode 2027 AddrTileType tileType; ///< Tile type 2028 ADDR_TILEINFO* pTileInfo; ///< Tile info 2029 2030} ADDR_CONVERT_TILEINDEX_OUTPUT; 2031 2032/** 2033**************************************************************************************************** 2034* AddrConvertTileIndex 2035* 2036* @brief 2037* Convert tile index to tile mode/type/info 2038**************************************************************************************************** 2039*/ 2040ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2041 ADDR_HANDLE hLib, 2042 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2043 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2044 2045/** 2046**************************************************************************************************** 2047* ADDR_GET_MACROMODEINDEX_INPUT 2048* 2049* @brief 2050* Input structure for AddrGetMacroModeIndex 2051**************************************************************************************************** 2052*/ 2053typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2054{ 2055 UINT_32 size; ///< Size of this structure in bytes 2056 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2057 INT_32 tileIndex; ///< Tile index 2058 UINT_32 bpp; ///< Bits per pixel 2059 UINT_32 numFrags; ///< Number of color fragments 2060} ADDR_GET_MACROMODEINDEX_INPUT; 2061 2062/** 2063**************************************************************************************************** 2064* ADDR_GET_MACROMODEINDEX_OUTPUT 2065* 2066* @brief 2067* Output structure for AddrGetMacroModeIndex 2068**************************************************************************************************** 2069*/ 2070typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2071{ 2072 UINT_32 size; ///< Size of this structure in bytes 2073 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2074} ADDR_GET_MACROMODEINDEX_OUTPUT; 2075 2076/** 2077**************************************************************************************************** 2078* AddrGetMacroModeIndex 2079* 2080* @brief 2081* Get macro mode index based on input parameters 2082**************************************************************************************************** 2083*/ 2084ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2085 ADDR_HANDLE hLib, 2086 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2087 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2088 2089/** 2090**************************************************************************************************** 2091* ADDR_CONVERT_TILEINDEX1_INPUT 2092* 2093* @brief 2094* Input structure for AddrConvertTileIndex1 (without macro mode index) 2095**************************************************************************************************** 2096*/ 2097typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2098{ 2099 UINT_32 size; ///< Size of this structure in bytes 2100 2101 INT_32 tileIndex; ///< Tile index 2102 UINT_32 bpp; ///< Bits per pixel 2103 UINT_32 numSamples; ///< Number of samples 2104 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2105} ADDR_CONVERT_TILEINDEX1_INPUT; 2106 2107/** 2108**************************************************************************************************** 2109* AddrConvertTileIndex1 2110* 2111* @brief 2112* Convert tile index to tile mode/type/info 2113**************************************************************************************************** 2114*/ 2115ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2116 ADDR_HANDLE hLib, 2117 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2118 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2119 2120/** 2121**************************************************************************************************** 2122* ADDR_GET_TILEINDEX_INPUT 2123* 2124* @brief 2125* Input structure for AddrGetTileIndex 2126**************************************************************************************************** 2127*/ 2128typedef struct _ADDR_GET_TILEINDEX_INPUT 2129{ 2130 UINT_32 size; ///< Size of this structure in bytes 2131 2132 AddrTileMode tileMode; ///< Tile mode 2133 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2134 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2135} ADDR_GET_TILEINDEX_INPUT; 2136 2137/** 2138**************************************************************************************************** 2139* ADDR_GET_TILEINDEX_OUTPUT 2140* 2141* @brief 2142* Output structure for AddrGetTileIndex 2143**************************************************************************************************** 2144*/ 2145typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2146{ 2147 UINT_32 size; ///< Size of this structure in bytes 2148 2149 INT_32 index; ///< index in table 2150} ADDR_GET_TILEINDEX_OUTPUT; 2151 2152/** 2153**************************************************************************************************** 2154* AddrGetTileIndex 2155* 2156* @brief 2157* Get the tiling mode index in table 2158**************************************************************************************************** 2159*/ 2160ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2161 ADDR_HANDLE hLib, 2162 const ADDR_GET_TILEINDEX_INPUT* pIn, 2163 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2164 2165/** 2166**************************************************************************************************** 2167* ADDR_PRT_INFO_INPUT 2168* 2169* @brief 2170* Input structure for AddrComputePrtInfo 2171**************************************************************************************************** 2172*/ 2173typedef struct _ADDR_PRT_INFO_INPUT 2174{ 2175 AddrFormat format; ///< Surface format 2176 UINT_32 baseMipWidth; ///< Base mipmap width 2177 UINT_32 baseMipHeight; ///< Base mipmap height 2178 UINT_32 baseMipDepth; ///< Base mipmap depth 2179 UINT_32 numFrags; ///< Number of fragments, 2180} ADDR_PRT_INFO_INPUT; 2181 2182/** 2183**************************************************************************************************** 2184* ADDR_PRT_INFO_OUTPUT 2185* 2186* @brief 2187* Input structure for AddrComputePrtInfo 2188**************************************************************************************************** 2189*/ 2190typedef struct _ADDR_PRT_INFO_OUTPUT 2191{ 2192 UINT_32 prtTileWidth; 2193 UINT_32 prtTileHeight; 2194} ADDR_PRT_INFO_OUTPUT; 2195 2196/** 2197**************************************************************************************************** 2198* AddrComputePrtInfo 2199* 2200* @brief 2201* Compute prt surface related information 2202**************************************************************************************************** 2203*/ 2204ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2205 ADDR_HANDLE hLib, 2206 const ADDR_PRT_INFO_INPUT* pIn, 2207 ADDR_PRT_INFO_OUTPUT* pOut); 2208 2209//////////////////////////////////////////////////////////////////////////////////////////////////// 2210// DCC key functions 2211//////////////////////////////////////////////////////////////////////////////////////////////////// 2212 2213/** 2214**************************************************************************************************** 2215* _ADDR_COMPUTE_DCCINFO_INPUT 2216* 2217* @brief 2218* Input structure of AddrComputeDccInfo 2219**************************************************************************************************** 2220*/ 2221typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2222{ 2223 UINT_32 size; ///< Size of this structure in bytes 2224 UINT_32 bpp; ///< BitPP of color surface 2225 UINT_32 numSamples; ///< Sample number of color surface 2226 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2227 AddrTileMode tileMode; ///< Tile mode of color surface 2228 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2229 UINT_32 tileSwizzle; ///< Tile swizzle 2230 INT_32 tileIndex; ///< Tile index of color surface, 2231 ///< MUST be -1 if you don't want to use it 2232 ///< while the global useTileIndex is set to 1 2233 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2234 ///< README: When tileIndex is not -1, this must be valid 2235} ADDR_COMPUTE_DCCINFO_INPUT; 2236 2237/** 2238**************************************************************************************************** 2239* ADDR_COMPUTE_DCCINFO_OUTPUT 2240* 2241* @brief 2242* Output structure of AddrComputeDccInfo 2243**************************************************************************************************** 2244*/ 2245typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2246{ 2247 UINT_32 size; ///< Size of this structure in bytes 2248 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2249 UINT_64 dccRamSize; ///< Size of dcc key 2250 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2251 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2252 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2253} ADDR_COMPUTE_DCCINFO_OUTPUT; 2254 2255/** 2256**************************************************************************************************** 2257* AddrComputeDccInfo 2258* 2259* @brief 2260* Compute DCC key size, base alignment 2261* info 2262**************************************************************************************************** 2263*/ 2264ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2265 ADDR_HANDLE hLib, 2266 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2267 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2268 2269/** 2270**************************************************************************************************** 2271* ADDR_GET_MAX_ALINGMENTS_OUTPUT 2272* 2273* @brief 2274* Output structure of AddrGetMaxAlignments 2275**************************************************************************************************** 2276*/ 2277typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT 2278{ 2279 UINT_32 size; ///< Size of this structure in bytes 2280 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2281} ADDR_GET_MAX_ALINGMENTS_OUTPUT; 2282 2283/** 2284**************************************************************************************************** 2285* AddrGetMaxAlignments 2286* 2287* @brief 2288* Gets maximnum alignments 2289**************************************************************************************************** 2290*/ 2291ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2292 ADDR_HANDLE hLib, 2293 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut); 2294 2295/** 2296**************************************************************************************************** 2297* AddrGetMaxMetaAlignments 2298* 2299* @brief 2300* Gets maximnum alignments for metadata 2301**************************************************************************************************** 2302*/ 2303ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2304 ADDR_HANDLE hLib, 2305 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut); 2306 2307/** 2308**************************************************************************************************** 2309* Address library interface version 2 2310* available from Gfx9 hardware 2311**************************************************************************************************** 2312* Addr2ComputeSurfaceInfo() 2313* Addr2ComputeSurfaceAddrFromCoord() 2314* Addr2ComputeSurfaceCoordFromAddr() 2315 2316* Addr2ComputeHtileInfo() 2317* Addr2ComputeHtileAddrFromCoord() 2318* Addr2ComputeHtileCoordFromAddr() 2319* 2320* Addr2ComputeCmaskInfo() 2321* Addr2ComputeCmaskAddrFromCoord() 2322* Addr2ComputeCmaskCoordFromAddr() 2323* 2324* Addr2ComputeFmaskInfo() 2325* Addr2ComputeFmaskAddrFromCoord() 2326* Addr2ComputeFmaskCoordFromAddr() 2327* 2328* Addr2ComputeDccInfo() 2329* 2330**/ 2331 2332//////////////////////////////////////////////////////////////////////////////////////////////////// 2333// Surface functions for Gfx9 2334//////////////////////////////////////////////////////////////////////////////////////////////////// 2335 2336/** 2337**************************************************************************************************** 2338* ADDR2_SURFACE_FLAGS 2339* 2340* @brief 2341* Surface flags 2342**************************************************************************************************** 2343*/ 2344typedef union _ADDR2_SURFACE_FLAGS 2345{ 2346 struct 2347 { 2348 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2349 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2350 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2351 UINT_32 fmask : 1; ///< This is an fmask surface 2352 UINT_32 overlay : 1; ///< This is an overlay surface 2353 UINT_32 display : 1; ///< This resource is displable, can be used with DRV 2354 UINT_32 prt : 1; ///< This is a partially resident texture 2355 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2356 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2357 UINT_32 texture : 1; ///< This resource can be used with SRV 2358 UINT_32 unordered : 1; ///< This resource can be used with UAV 2359 UINT_32 rotated : 1; ///< This resource is rotated and displable 2360 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2361 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2362 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2363 UINT_32 noMetadata : 1; ///< This resource has no metadata 2364 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2365 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2366 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2367 UINT_32 reserved : 13; ///< Reserved bits 2368 }; 2369 2370 UINT_32 value; 2371} ADDR2_SURFACE_FLAGS; 2372 2373/** 2374**************************************************************************************************** 2375* ADDR2_COMPUTE_SURFACE_INFO_INPUT 2376* 2377* @brief 2378* Input structure for Addr2ComputeSurfaceInfo 2379**************************************************************************************************** 2380*/ 2381typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2382{ 2383 UINT_32 size; ///< Size of this structure in bytes 2384 2385 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2386 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 2387 AddrResourceType resourceType; ///< Surface type 2388 AddrFormat format; ///< Surface format 2389 UINT_32 bpp; ///< bits per pixel 2390 UINT_32 width; ///< Width (of mip0), in pixels 2391 UINT_32 height; ///< Height (of mip0), in pixels 2392 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2393 UINT_32 numMipLevels; ///< Total mipmap levels. 2394 UINT_32 numSamples; ///< Number of samples 2395 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2396 /// number of samples for normal AA; Set it to the 2397 /// number of fragments for EQAA 2398 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2399 UINT_32 sliceAlign; ///< Required slice size in bytes 2400} ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2401 2402/** 2403**************************************************************************************************** 2404* ADDR2_MIP_INFO 2405* 2406* @brief 2407* Structure that contains information for mip level 2408* 2409**************************************************************************************************** 2410*/ 2411typedef struct _ADDR2_MIP_INFO 2412{ 2413 UINT_32 pitch; ///< Pitch in elements 2414 UINT_32 height; ///< Padded height in elements 2415 UINT_32 depth; ///< Padded depth 2416 UINT_32 pixelPitch; ///< Pitch in pixels 2417 UINT_32 pixelHeight; ///< Padded height in pixels 2418 UINT_32 equationIndex; ///< Equation index in the equation table 2419 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2420 ///< to setup vam surface descriptor, can't be used 2421 ///< to setup swizzle pattern 2422 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2423 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2424 UINT_32 mipTailCoordX; ///< mip tail coord x 2425 UINT_32 mipTailCoordY; ///< mip tail coord y 2426 UINT_32 mipTailCoordZ; ///< mip tail coord z 2427} ADDR2_MIP_INFO; 2428 2429/** 2430**************************************************************************************************** 2431* ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2432* 2433* @brief 2434* Output structure for Addr2ComputeSurfInfo 2435* @note 2436 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2437 Pixel: Original pixel 2438**************************************************************************************************** 2439*/ 2440typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2441{ 2442 UINT_32 size; ///< Size of this structure in bytes 2443 2444 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2445 UINT_32 height; ///< Padded height (of mip0) in elements 2446 UINT_32 numSlices; ///< Padded depth for 3d resource 2447 ///< or padded number of slices for 2d array resource 2448 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2449 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2450 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2451 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2452 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2453 UINT_32 baseAlign; ///< Base address alignment 2454 UINT_32 bpp; ///< Bits per elements 2455 /// (e.g. blocks for BCn, 1/3 for 96bit) 2456 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2457 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2458 UINT_32 pixelPitch; ///< Pitch in original pixels 2459 UINT_32 pixelHeight; ///< Height in original pixels 2460 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2461 2462 UINT_32 blockWidth; ///< Width in element inside one block 2463 UINT_32 blockHeight; ///< Height in element inside one block 2464 UINT_32 blockSlices; ///< Slice number inside one block 2465 ///< Prt tile is one block, its width/height/slice 2466 ///< equals to blcok width/height/slice 2467 2468 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2469 /// Stereo info 2470 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2471 /// Mip info 2472 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2473 /// if it is not NULL, the array is assumed to 2474 /// contain numMipLevels entries 2475 2476 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2477 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2478 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2479 /// in tail, it will be set to number of mip levels 2480} ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2481 2482/** 2483**************************************************************************************************** 2484* Addr2ComputeSurfaceInfo 2485* 2486* @brief 2487* Compute surface width/height/slices/alignments and suitable tiling mode 2488**************************************************************************************************** 2489*/ 2490ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2491 ADDR_HANDLE hLib, 2492 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2493 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2494 2495/** 2496**************************************************************************************************** 2497* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2498* 2499* @brief 2500* Input structure for Addr2ComputeSurfaceAddrFromCoord 2501**************************************************************************************************** 2502*/ 2503typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2504{ 2505 UINT_32 size; ///< Size of this structure in bytes 2506 2507 UINT_32 x; ///< X coordinate 2508 UINT_32 y; ///< Y coordinate 2509 UINT_32 slice; ///< Slice index 2510 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2511 UINT_32 mipId; ///< the mip ID in mip chain 2512 2513 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2514 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2515 AddrResourceType resourceType; ///< Surface type 2516 UINT_32 bpp; ///< Bits per pixel 2517 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2518 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2519 UINT_32 numSlices; ///< Surface original slices (of mip0) 2520 UINT_32 numMipLevels; ///< Total mipmap levels 2521 UINT_32 numSamples; ///< Number of samples 2522 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2523 /// number of samples for normal AA; Set it to the 2524 /// number of fragments for EQAA 2525 2526 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2527 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2528} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2529 2530/** 2531**************************************************************************************************** 2532* ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2533* 2534* @brief 2535* Output structure for Addr2ComputeSurfaceAddrFromCoord 2536**************************************************************************************************** 2537*/ 2538typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2539{ 2540 UINT_32 size; ///< Size of this structure in bytes 2541 2542 UINT_64 addr; ///< Byte address 2543 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2544 /// For surface bpp < 8, e.g. FMT_1. 2545 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2546} ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2547 2548/** 2549**************************************************************************************************** 2550* Addr2ComputeSurfaceAddrFromCoord 2551* 2552* @brief 2553* Compute surface address from a given coordinate. 2554**************************************************************************************************** 2555*/ 2556ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2557 ADDR_HANDLE hLib, 2558 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2559 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2560 2561/** 2562**************************************************************************************************** 2563* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2564* 2565* @brief 2566* Input structure for Addr2ComputeSurfaceCoordFromAddr 2567**************************************************************************************************** 2568*/ 2569typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2570{ 2571 UINT_32 size; ///< Size of this structure in bytes 2572 2573 UINT_64 addr; ///< Address in bytes 2574 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2575 /// e.g. FMT_1; 2576 2577 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2578 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2579 AddrResourceType resourceType; ///< Surface type 2580 UINT_32 bpp; ///< Bits per pixel 2581 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2582 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2583 UINT_32 numSlices; ///< Surface original slices (of mip0) 2584 UINT_32 numMipLevels; ///< Total mipmap levels. 2585 UINT_32 numSamples; ///< Number of samples 2586 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2587 /// number of samples for normal AA; Set it to the 2588 /// number of fragments for EQAA 2589 2590 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2591 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2592} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2593 2594/** 2595**************************************************************************************************** 2596* ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2597* 2598* @brief 2599* Output structure for Addr2ComputeSurfaceCoordFromAddr 2600**************************************************************************************************** 2601*/ 2602typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2603{ 2604 UINT_32 size; ///< Size of this structure in bytes 2605 2606 UINT_32 x; ///< X coordinate 2607 UINT_32 y; ///< Y coordinate 2608 UINT_32 slice; ///< Index of slices 2609 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2610 UINT_32 mipId; ///< mipmap level id 2611} ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2612 2613/** 2614**************************************************************************************************** 2615* Addr2ComputeSurfaceCoordFromAddr 2616* 2617* @brief 2618* Compute coordinate from a given surface address 2619**************************************************************************************************** 2620*/ 2621ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2622 ADDR_HANDLE hLib, 2623 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2624 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2625 2626//////////////////////////////////////////////////////////////////////////////////////////////////// 2627// HTile functions for Gfx9 2628//////////////////////////////////////////////////////////////////////////////////////////////////// 2629 2630/** 2631**************************************************************************************************** 2632* ADDR2_META_FLAGS 2633* 2634* @brief 2635* Metadata flags 2636**************************************************************************************************** 2637*/ 2638typedef union _ADDR2_META_FLAGS 2639{ 2640 struct 2641 { 2642 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2643 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2644 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2645 UINT_32 reserved : 29; ///< Reserved bits 2646 }; 2647 2648 UINT_32 value; 2649} ADDR2_META_FLAGS; 2650 2651/** 2652**************************************************************************************************** 2653* ADDR2_META_MIP_INFO 2654* 2655* @brief 2656* Structure to store per mip metadata information 2657**************************************************************************************************** 2658*/ 2659typedef struct _ADDR2_META_MIP_INFO 2660{ 2661 BOOL_32 inMiptail; 2662 union 2663 { 2664 struct 2665 { 2666 UINT_32 startX; 2667 UINT_32 startY; 2668 UINT_32 startZ; 2669 UINT_32 width; 2670 UINT_32 height; 2671 UINT_32 depth; 2672 }; 2673 2674 struct 2675 { 2676 UINT_32 offset; ///< Metadata offset within one slice, 2677 /// the thickness of a slice is meta block depth. 2678 UINT_32 sliceSize; ///< Metadata size within one slice, 2679 /// the thickness of a slice is meta block depth. 2680 }; 2681 }; 2682} ADDR2_META_MIP_INFO; 2683 2684/** 2685**************************************************************************************************** 2686* ADDR2_COMPUTE_HTILE_INFO_INPUT 2687* 2688* @brief 2689* Input structure of Addr2ComputeHtileInfo 2690**************************************************************************************************** 2691*/ 2692typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2693{ 2694 UINT_32 size; ///< Size of this structure in bytes 2695 2696 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2697 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2698 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2699 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2700 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2701 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2702 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2703 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2704 /// if no mip is in tail, it should be set to 2705 /// number of mip levels 2706} ADDR2_COMPUTE_HTILE_INFO_INPUT; 2707 2708/** 2709**************************************************************************************************** 2710* ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2711* 2712* @brief 2713* Output structure of Addr2ComputeHtileInfo 2714**************************************************************************************************** 2715*/ 2716typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2717{ 2718 UINT_32 size; ///< Size of this structure in bytes 2719 2720 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2721 /// HTile buffer. This might be larger than original depth 2722 /// buffer pitch when called with an unaligned pitch. 2723 UINT_32 height; ///< Height in pixels, as above 2724 UINT_32 baseAlign; ///< Base alignment 2725 UINT_32 sliceSize; ///< Slice size, in bytes. 2726 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2727 UINT_32 metaBlkWidth; ///< Meta block width 2728 UINT_32 metaBlkHeight; ///< Meta block height 2729 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2730 2731 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2732} ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2733 2734/** 2735**************************************************************************************************** 2736* Addr2ComputeHtileInfo 2737* 2738* @brief 2739* Compute Htile pitch, height, base alignment and size in bytes 2740**************************************************************************************************** 2741*/ 2742ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2743 ADDR_HANDLE hLib, 2744 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2745 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2746 2747/** 2748**************************************************************************************************** 2749* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2750* 2751* @brief 2752* Input structure for Addr2ComputeHtileAddrFromCoord 2753**************************************************************************************************** 2754*/ 2755typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2756{ 2757 UINT_32 size; ///< Size of this structure in bytes 2758 2759 UINT_32 x; ///< X coordinate 2760 UINT_32 y; ///< Y coordinate 2761 UINT_32 slice; ///< Index of slices 2762 UINT_32 mipId; ///< mipmap level id 2763 2764 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2765 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2766 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2767 UINT_32 bpp; ///< Depth surface bits per pixel 2768 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2769 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2770 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2771 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2772 UINT_32 numSamples; ///< Depth surface number of samples 2773 UINT_32 pipeXor; ///< Pipe xor setting 2774} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2775 2776/** 2777**************************************************************************************************** 2778* ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2779* 2780* @brief 2781* Output structure for Addr2ComputeHtileAddrFromCoord 2782**************************************************************************************************** 2783*/ 2784typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2785{ 2786 UINT_32 size; ///< Size of this structure in bytes 2787 2788 UINT_64 addr; ///< Address in bytes 2789} ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2790 2791/** 2792**************************************************************************************************** 2793* Addr2ComputeHtileAddrFromCoord 2794* 2795* @brief 2796* Compute Htile address according to coordinates (of depth buffer) 2797**************************************************************************************************** 2798*/ 2799ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2800 ADDR_HANDLE hLib, 2801 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2802 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2803 2804/** 2805**************************************************************************************************** 2806* ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2807* 2808* @brief 2809* Input structure for Addr2ComputeHtileCoordFromAddr 2810**************************************************************************************************** 2811*/ 2812typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2813{ 2814 UINT_32 size; ///< Size of this structure in bytes 2815 2816 UINT_64 addr; ///< Address 2817 2818 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2819 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2820 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2821 UINT_32 bpp; ///< Depth surface bits per pixel 2822 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2823 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2824 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2825 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2826 UINT_32 numSamples; ///< Depth surface number of samples 2827 UINT_32 pipeXor; ///< Pipe xor setting 2828} ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2829 2830/** 2831**************************************************************************************************** 2832* ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2833* 2834* @brief 2835* Output structure for Addr2ComputeHtileCoordFromAddr 2836**************************************************************************************************** 2837*/ 2838typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2839{ 2840 UINT_32 size; ///< Size of this structure in bytes 2841 2842 UINT_32 x; ///< X coordinate 2843 UINT_32 y; ///< Y coordinate 2844 UINT_32 slice; ///< Index of slices 2845 UINT_32 mipId; ///< mipmap level id 2846} ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2847 2848/** 2849**************************************************************************************************** 2850* Addr2ComputeHtileCoordFromAddr 2851* 2852* @brief 2853* Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2854* Htile address 2855**************************************************************************************************** 2856*/ 2857ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2858 ADDR_HANDLE hLib, 2859 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2860 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2861 2862//////////////////////////////////////////////////////////////////////////////////////////////////// 2863// C-mask functions for Gfx9 2864//////////////////////////////////////////////////////////////////////////////////////////////////// 2865 2866/** 2867**************************************************************************************************** 2868* ADDR2_COMPUTE_CMASK_INFO_INPUT 2869* 2870* @brief 2871* Input structure of Addr2ComputeCmaskInfo 2872**************************************************************************************************** 2873*/ 2874typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2875{ 2876 UINT_32 size; ///< Size of this structure in bytes 2877 2878 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2879 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2880 AddrResourceType resourceType; ///< Color surface type 2881 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2882 UINT_32 unalignedWidth; ///< Color surface original width 2883 UINT_32 unalignedHeight; ///< Color surface original height 2884 UINT_32 numSlices; ///< Number of slices of color buffer 2885} ADDR2_COMPUTE_CMASK_INFO_INPUT; 2886 2887/** 2888**************************************************************************************************** 2889* ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2890* 2891* @brief 2892* Output structure of Addr2ComputeCmaskInfo 2893**************************************************************************************************** 2894*/ 2895typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2896{ 2897 UINT_32 size; ///< Size of this structure in bytes 2898 2899 UINT_32 pitch; ///< Pitch in pixels of color buffer which 2900 /// this Cmask matches. The size might be larger than 2901 /// original color buffer pitch when called with 2902 /// an unaligned pitch. 2903 UINT_32 height; ///< Height in pixels, as above 2904 UINT_32 baseAlign; ///< Base alignment 2905 UINT_32 sliceSize; ///< Slice size, in bytes. 2906 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 2907 UINT_32 metaBlkWidth; ///< Meta block width 2908 UINT_32 metaBlkHeight; ///< Meta block height 2909 2910 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2911} ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 2912 2913/** 2914**************************************************************************************************** 2915* Addr2ComputeCmaskInfo 2916* 2917* @brief 2918* Compute Cmask pitch, height, base alignment and size in bytes from color buffer 2919* info 2920**************************************************************************************************** 2921*/ 2922ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 2923 ADDR_HANDLE hLib, 2924 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 2925 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 2926 2927/** 2928**************************************************************************************************** 2929* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 2930* 2931* @brief 2932* Input structure for Addr2ComputeCmaskAddrFromCoord 2933* 2934**************************************************************************************************** 2935*/ 2936typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 2937{ 2938 UINT_32 size; ///< Size of this structure in bytes 2939 2940 UINT_32 x; ///< X coordinate 2941 UINT_32 y; ///< Y coordinate 2942 UINT_32 slice; ///< Index of slices 2943 2944 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2945 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2946 AddrResourceType resourceType; ///< Color surface type 2947 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2948 2949 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 2950 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 2951 UINT_32 numSlices; ///< Color surface original slices (of mip0) 2952 2953 UINT_32 numSamples; ///< Color surfae sample number 2954 UINT_32 numFrags; ///< Color surface fragment number 2955 2956 UINT_32 pipeXor; ///< pipe Xor setting 2957} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 2958 2959/** 2960**************************************************************************************************** 2961* ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 2962* 2963* @brief 2964* Output structure for Addr2ComputeCmaskAddrFromCoord 2965**************************************************************************************************** 2966*/ 2967typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 2968{ 2969 UINT_32 size; ///< Size of this structure in bytes 2970 2971 UINT_64 addr; ///< CMASK address in bytes 2972 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 2973} ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 2974 2975/** 2976**************************************************************************************************** 2977* Addr2ComputeCmaskAddrFromCoord 2978* 2979* @brief 2980* Compute Cmask address according to coordinates (of MSAA color buffer) 2981**************************************************************************************************** 2982*/ 2983ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 2984 ADDR_HANDLE hLib, 2985 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 2986 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 2987 2988/** 2989**************************************************************************************************** 2990* ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 2991* 2992* @brief 2993* Input structure for Addr2ComputeCmaskCoordFromAddr 2994**************************************************************************************************** 2995*/ 2996typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 2997{ 2998 UINT_32 size; ///< Size of this structure in bytes 2999 3000 UINT_64 addr; ///< CMASK address in bytes 3001 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3002 3003 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3004 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3005 AddrResourceType resourceType; ///< Color surface type 3006 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3007 3008 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3009 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3010 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3011 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3012} ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3013 3014/** 3015**************************************************************************************************** 3016* ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3017* 3018* @brief 3019* Output structure for Addr2ComputeCmaskCoordFromAddr 3020**************************************************************************************************** 3021*/ 3022typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3023{ 3024 UINT_32 size; ///< Size of this structure in bytes 3025 3026 UINT_32 x; ///< X coordinate 3027 UINT_32 y; ///< Y coordinate 3028 UINT_32 slice; ///< Index of slices 3029 UINT_32 mipId; ///< mipmap level id 3030} ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3031 3032/** 3033**************************************************************************************************** 3034* Addr2ComputeCmaskCoordFromAddr 3035* 3036* @brief 3037* Compute coordinates within color buffer (1st pixel of a micro tile) according to 3038* Cmask address 3039**************************************************************************************************** 3040*/ 3041ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3042 ADDR_HANDLE hLib, 3043 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3044 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3045 3046//////////////////////////////////////////////////////////////////////////////////////////////////// 3047// F-mask functions for Gfx9 3048//////////////////////////////////////////////////////////////////////////////////////////////////// 3049 3050/** 3051**************************************************************************************************** 3052* ADDR2_FMASK_FLAGS 3053* 3054* @brief 3055* FMASK flags 3056**************************************************************************************************** 3057*/ 3058typedef union _ADDR2_FMASK_FLAGS 3059{ 3060 struct 3061 { 3062 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3063 /// by H/W clients. S/W should always set it to FALSE. 3064 UINT_32 reserved : 31; ///< Reserved for future use. 3065 }; 3066 3067 UINT_32 value; 3068} ADDR2_FMASK_FLAGS; 3069 3070/** 3071**************************************************************************************************** 3072* ADDR2_COMPUTE_FMASK_INFO_INPUT 3073* 3074* @brief 3075* Input structure for Addr2ComputeFmaskInfo 3076**************************************************************************************************** 3077*/ 3078typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3079{ 3080 UINT_32 size; ///< Size of this structure in bytes 3081 3082 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3083 UINT_32 unalignedWidth; ///< Color surface original width 3084 UINT_32 unalignedHeight; ///< Color surface original height 3085 UINT_32 numSlices; ///< Number of slices/depth 3086 UINT_32 numSamples; ///< Number of samples 3087 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3088 /// number of samples for normal AA; Set it to the 3089 /// number of fragments for EQAA 3090 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3091} ADDR2_COMPUTE_FMASK_INFO_INPUT; 3092 3093/** 3094**************************************************************************************************** 3095* ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3096* 3097* @brief 3098* Output structure for Addr2ComputeFmaskInfo 3099**************************************************************************************************** 3100*/ 3101typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3102{ 3103 UINT_32 size; ///< Size of this structure in bytes 3104 3105 UINT_32 pitch; ///< Pitch of fmask in pixels 3106 UINT_32 height; ///< Height of fmask in pixels 3107 UINT_32 baseAlign; ///< Base alignment 3108 UINT_32 numSlices; ///< Slices of fmask 3109 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3110 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3111 UINT_32 numSamples; ///< Number of samples 3112 UINT_32 sliceSize; ///< Size of slice in bytes 3113} ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3114 3115/** 3116**************************************************************************************************** 3117* Addr2ComputeFmaskInfo 3118* 3119* @brief 3120* Compute Fmask pitch/height/slices/alignments and size in bytes 3121**************************************************************************************************** 3122*/ 3123ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3124 ADDR_HANDLE hLib, 3125 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3126 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3127 3128/** 3129**************************************************************************************************** 3130* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3131* 3132* @brief 3133* Input structure for Addr2ComputeFmaskAddrFromCoord 3134**************************************************************************************************** 3135*/ 3136typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3137{ 3138 UINT_32 size; ///< Size of this structure in bytes 3139 3140 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3141 UINT_32 x; ///< X coordinate 3142 UINT_32 y; ///< Y coordinate 3143 UINT_32 slice; ///< Slice index 3144 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3145 UINT_32 plane; ///< Plane number 3146 3147 UINT_32 unalignedWidth; ///< Color surface original width 3148 UINT_32 unalignedHeight; ///< Color surface original height 3149 UINT_32 numSamples; ///< Number of samples 3150 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3151 /// number of samples for normal AA; Set it to the 3152 /// number of fragments for EQAA 3153 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3154 3155 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3156} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3157 3158/** 3159**************************************************************************************************** 3160* ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3161* 3162* @brief 3163* Output structure for Addr2ComputeFmaskAddrFromCoord 3164**************************************************************************************************** 3165*/ 3166typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3167{ 3168 UINT_32 size; ///< Size of this structure in bytes 3169 3170 UINT_64 addr; ///< Fmask address 3171 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3172} ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3173 3174/** 3175**************************************************************************************************** 3176* Addr2ComputeFmaskAddrFromCoord 3177* 3178* @brief 3179* Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3180**************************************************************************************************** 3181*/ 3182ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3183 ADDR_HANDLE hLib, 3184 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3185 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3186 3187/** 3188**************************************************************************************************** 3189* ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3190* 3191* @brief 3192* Input structure for Addr2ComputeFmaskCoordFromAddr 3193**************************************************************************************************** 3194*/ 3195typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3196{ 3197 UINT_32 size; ///< Size of this structure in bytes 3198 3199 UINT_64 addr; ///< Address 3200 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3201 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3202 3203 UINT_32 unalignedWidth; ///< Color surface original width 3204 UINT_32 unalignedHeight; ///< Color surface original height 3205 UINT_32 numSamples; ///< Number of samples 3206 UINT_32 numFrags; ///< Number of fragments 3207 3208 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3209 3210 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3211} ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3212 3213/** 3214**************************************************************************************************** 3215* ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3216* 3217* @brief 3218* Output structure for Addr2ComputeFmaskCoordFromAddr 3219**************************************************************************************************** 3220*/ 3221typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3222{ 3223 UINT_32 size; ///< Size of this structure in bytes 3224 3225 UINT_32 x; ///< X coordinate 3226 UINT_32 y; ///< Y coordinate 3227 UINT_32 slice; ///< Slice index 3228 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3229 UINT_32 plane; ///< Plane number 3230} ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3231 3232/** 3233**************************************************************************************************** 3234* Addr2ComputeFmaskCoordFromAddr 3235* 3236* @brief 3237* Compute FMASK coordinate from an given address 3238**************************************************************************************************** 3239*/ 3240ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3241 ADDR_HANDLE hLib, 3242 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3243 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3244 3245//////////////////////////////////////////////////////////////////////////////////////////////////// 3246// DCC key functions for Gfx9 3247//////////////////////////////////////////////////////////////////////////////////////////////////// 3248 3249/** 3250**************************************************************************************************** 3251* _ADDR2_COMPUTE_DCCINFO_INPUT 3252* 3253* @brief 3254* Input structure of Addr2ComputeDccInfo 3255**************************************************************************************************** 3256*/ 3257typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3258{ 3259 UINT_32 size; ///< Size of this structure in bytes 3260 3261 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3262 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3263 AddrResourceType resourceType; ///< Color surface type 3264 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3265 UINT_32 bpp; ///< bits per pixel 3266 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3267 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3268 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3269 UINT_32 numFrags; ///< Fragment number of color surface 3270 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3271 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3272 ///< useful in meta linear case 3273 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3274 /// it should be number of mip levels 3275} ADDR2_COMPUTE_DCCINFO_INPUT; 3276 3277/** 3278**************************************************************************************************** 3279* ADDR2_COMPUTE_DCCINFO_OUTPUT 3280* 3281* @brief 3282* Output structure of Addr2ComputeDccInfo 3283**************************************************************************************************** 3284*/ 3285typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3286{ 3287 UINT_32 size; ///< Size of this structure in bytes 3288 3289 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3290 UINT_32 dccRamSize; ///< Size of dcc key 3291 3292 UINT_32 pitch; ///< DCC surface mip chain pitch 3293 UINT_32 height; ///< DCC surface mip chain height 3294 UINT_32 depth; ///< DCC surface mip chain depth 3295 3296 UINT_32 compressBlkWidth; ///< DCC compress block width 3297 UINT_32 compressBlkHeight; ///< DCC compress block height 3298 UINT_32 compressBlkDepth; ///< DCC compress block depth 3299 3300 UINT_32 metaBlkWidth; ///< DCC meta block width 3301 UINT_32 metaBlkHeight; ///< DCC meta block height 3302 UINT_32 metaBlkDepth; ///< DCC meta block depth 3303 3304 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3305 3306 union 3307 { 3308 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3309 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3310 /// the slize size of a mip chain, the thickness of a 3311 /// a slice is meta block depth 3312 }; 3313 3314 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3315} ADDR2_COMPUTE_DCCINFO_OUTPUT; 3316 3317/** 3318**************************************************************************************************** 3319* Addr2ComputeDccInfo 3320* 3321* @brief 3322* Compute DCC key size, base alignment 3323* info 3324**************************************************************************************************** 3325*/ 3326ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3327 ADDR_HANDLE hLib, 3328 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3329 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3330 3331/** 3332**************************************************************************************************** 3333* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3334* 3335* @brief 3336* Input structure for Addr2ComputeDccAddrFromCoord 3337* 3338**************************************************************************************************** 3339*/ 3340typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3341{ 3342 UINT_32 size; ///< Size of this structure in bytes 3343 3344 UINT_32 x; ///< X coordinate 3345 UINT_32 y; ///< Y coordinate 3346 UINT_32 slice; ///< Index of slices 3347 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3348 UINT_32 mipId; ///< mipmap level id 3349 3350 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3351 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3352 AddrResourceType resourceType; ///< Color surface type 3353 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3354 UINT_32 bpp; ///< Color surface bits per pixel 3355 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3356 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3357 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3358 UINT_32 numMipLevels; ///< Color surface mipmap levels 3359 UINT_32 numFrags; ///< Color surface fragment number 3360 3361 UINT_32 pipeXor; ///< pipe Xor setting 3362} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3363 3364/** 3365**************************************************************************************************** 3366* ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3367* 3368* @brief 3369* Output structure for Addr2ComputeDccAddrFromCoord 3370**************************************************************************************************** 3371*/ 3372typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3373{ 3374 UINT_32 size; ///< Size of this structure in bytes 3375 3376 UINT_64 addr; ///< DCC address in bytes 3377} ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3378 3379/** 3380**************************************************************************************************** 3381* Addr2ComputeDccAddrFromCoord 3382* 3383* @brief 3384* Compute DCC address according to coordinates (of MSAA color buffer) 3385**************************************************************************************************** 3386*/ 3387ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3388 ADDR_HANDLE hLib, 3389 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3390 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3391 3392//////////////////////////////////////////////////////////////////////////////////////////////////// 3393// Misc functions for Gfx9 3394//////////////////////////////////////////////////////////////////////////////////////////////////// 3395 3396/** 3397**************************************************************************************************** 3398* ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3399* 3400* @brief 3401* Input structure of Addr2ComputePipebankXor 3402**************************************************************************************************** 3403*/ 3404typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3405{ 3406 UINT_32 size; ///< Size of this structure in bytes 3407 UINT_32 surfIndex; ///< Input surface index 3408 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3409 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3410 AddrResourceType resourceType; ///< Surface resource type 3411 AddrFormat format; ///< Surface format 3412 UINT_32 numSamples; ///< Number of samples 3413 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3414 /// number of samples for normal AA; Set it to the 3415 /// number of fragments for EQAA 3416} ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3417 3418/** 3419**************************************************************************************************** 3420* ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3421* 3422* @brief 3423* Output structure of Addr2ComputePipebankXor 3424**************************************************************************************************** 3425*/ 3426typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3427{ 3428 UINT_32 size; ///< Size of this structure in bytes 3429 UINT_32 pipeBankXor; ///< Pipe bank xor 3430} ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3431 3432/** 3433**************************************************************************************************** 3434* Addr2ComputePipeBankXor 3435* 3436* @brief 3437* Calculate a valid bank pipe xor value for client to use. 3438**************************************************************************************************** 3439*/ 3440ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3441 ADDR_HANDLE hLib, 3442 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3443 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3444 3445/** 3446**************************************************************************************************** 3447* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3448* 3449* @brief 3450* Input structure of Addr2ComputeSlicePipeBankXor 3451**************************************************************************************************** 3452*/ 3453typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3454{ 3455 UINT_32 size; ///< Size of this structure in bytes 3456 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3457 AddrResourceType resourceType; ///< Surface resource type 3458 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3459 UINT_32 slice; ///< Slice id 3460 UINT_32 numSamples; ///< Number of samples 3461} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3462 3463/** 3464**************************************************************************************************** 3465* ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3466* 3467* @brief 3468* Output structure of Addr2ComputeSlicePipeBankXor 3469**************************************************************************************************** 3470*/ 3471typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3472{ 3473 UINT_32 size; ///< Size of this structure in bytes 3474 UINT_32 pipeBankXor; ///< Pipe bank xor 3475} ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3476 3477/** 3478**************************************************************************************************** 3479* Addr2ComputeSlicePipeBankXor 3480* 3481* @brief 3482* Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3483**************************************************************************************************** 3484*/ 3485ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3486 ADDR_HANDLE hLib, 3487 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3488 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3489 3490/** 3491**************************************************************************************************** 3492* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3493* 3494* @brief 3495* Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3496**************************************************************************************************** 3497*/ 3498typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3499{ 3500 UINT_32 size; ///< Size of this structure in bytes 3501 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3502 AddrResourceType resourceType; ///< Surface resource type 3503 UINT_32 pipeBankXor; ///< Per resource xor 3504 UINT_32 slice; ///< Slice id 3505 UINT_64 sliceSize; ///< Slice size of a mip chain 3506 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3507 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3508} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3509 3510/** 3511**************************************************************************************************** 3512* ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3513* 3514* @brief 3515* Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3516**************************************************************************************************** 3517*/ 3518typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3519{ 3520 UINT_32 size; ///< Size of this structure in bytes 3521 UINT_64 offset; ///< offset 3522} ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3523 3524/** 3525**************************************************************************************************** 3526* Addr2ComputeSubResourceOffsetForSwizzlePattern 3527* 3528* @brief 3529* Calculate sub resource offset to support swizzle pattern. 3530**************************************************************************************************** 3531*/ 3532ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3533 ADDR_HANDLE hLib, 3534 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3535 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3536 3537/** 3538**************************************************************************************************** 3539* ADDR2_BLOCK_SET 3540* 3541* @brief 3542* Bit field that defines block type 3543**************************************************************************************************** 3544*/ 3545typedef union _ADDR2_BLOCK_SET 3546{ 3547 struct 3548 { 3549 UINT_32 micro : 1; // 256B block for 2D resource 3550 UINT_32 macro4KB : 1; // 4KB for 2D/3D resource 3551 UINT_32 macro64KB : 1; // 64KB for 2D/3D resource 3552 UINT_32 var : 1; // VAR block 3553 UINT_32 linear : 1; // Linear block 3554 UINT_32 reserved : 27; 3555 }; 3556 3557 UINT_32 value; 3558} ADDR2_BLOCK_SET; 3559 3560/** 3561**************************************************************************************************** 3562* ADDR2_SWTYPE_SET 3563* 3564* @brief 3565* Bit field that defines swizzle type 3566**************************************************************************************************** 3567*/ 3568typedef union _ADDR2_SWTYPE_SET 3569{ 3570 struct 3571 { 3572 UINT_32 sw_Z : 1; // SW_*_Z_* 3573 UINT_32 sw_S : 1; // SW_*_S_* 3574 UINT_32 sw_D : 1; // SW_*_D_* 3575 UINT_32 sw_R : 1; // SW_*_R_* 3576 UINT_32 reserved : 28; 3577 }; 3578 3579 UINT_32 value; 3580} ADDR2_SWTYPE_SET; 3581 3582/** 3583**************************************************************************************************** 3584* ADDR2_SWMODE_SET 3585* 3586* @brief 3587* Bit field that defines swizzle type 3588**************************************************************************************************** 3589*/ 3590typedef union _ADDR2_SWMODE_SET 3591{ 3592 struct 3593 { 3594 UINT_32 swLinear : 1; 3595 UINT_32 sw256B_S : 1; 3596 UINT_32 sw256B_D : 1; 3597 UINT_32 sw256B_R : 1; 3598 UINT_32 sw4KB_Z : 1; 3599 UINT_32 sw4KB_S : 1; 3600 UINT_32 sw4KB_D : 1; 3601 UINT_32 sw4KB_R : 1; 3602 UINT_32 sw64KB_Z : 1; 3603 UINT_32 sw64KB_S : 1; 3604 UINT_32 sw64KB_D : 1; 3605 UINT_32 sw64KB_R : 1; 3606 UINT_32 swVar_Z : 1; 3607 UINT_32 swVar_S : 1; 3608 UINT_32 swVar_D : 1; 3609 UINT_32 swVar_R : 1; 3610 UINT_32 sw64KB_Z_T : 1; 3611 UINT_32 sw64KB_S_T : 1; 3612 UINT_32 sw64KB_D_T : 1; 3613 UINT_32 sw64KB_R_T : 1; 3614 UINT_32 sw4KB_Z_X : 1; 3615 UINT_32 sw4KB_S_X : 1; 3616 UINT_32 sw4KB_D_X : 1; 3617 UINT_32 sw4KB_R_X : 1; 3618 UINT_32 sw64KB_Z_X : 1; 3619 UINT_32 sw64KB_S_X : 1; 3620 UINT_32 sw64KB_D_X : 1; 3621 UINT_32 sw64KB_R_X : 1; 3622 UINT_32 swVar_Z_X : 1; 3623 UINT_32 swVar_S_X : 1; 3624 UINT_32 swVar_D_X : 1; 3625 UINT_32 swVar_R_X : 1; 3626 }; 3627 3628 UINT_32 value; 3629} ADDR2_SWMODE_SET; 3630 3631/** 3632**************************************************************************************************** 3633* ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3634* 3635* @brief 3636* Input structure of Addr2GetPreferredSurfaceSetting 3637**************************************************************************************************** 3638*/ 3639typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3640{ 3641 UINT_32 size; ///< Size of this structure in bytes 3642 3643 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3644 AddrResourceType resourceType; ///< Surface type 3645 AddrFormat format; ///< Surface format 3646 AddrResrouceLocation resourceLoction; ///< Surface heap choice 3647 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3648 ///< such as linear for DXTn, tiled for YUV 3649 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3650 BOOL_32 noXor; ///< Do not use xor mode for this resource 3651 UINT_32 bpp; ///< bits per pixel 3652 UINT_32 width; ///< Width (of mip0), in pixels 3653 UINT_32 height; ///< Height (of mip0), in pixels 3654 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3655 UINT_32 numMipLevels; ///< Total mipmap levels. 3656 UINT_32 numSamples; ///< Number of samples 3657 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3658 /// number of samples for normal AA; Set it to the 3659 /// number of fragments for EQAA 3660 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3661 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3662 /// be padded to multiple of this value (in bytes) 3663} ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3664 3665/** 3666**************************************************************************************************** 3667* ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3668* 3669* @brief 3670* Output structure of Addr2GetPreferredSurfaceSetting 3671**************************************************************************************************** 3672*/ 3673typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3674{ 3675 UINT_32 size; ///< Size of this structure in bytes 3676 3677 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3678 AddrResourceType resourceType; ///< Suggested resource type to program HW 3679 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3680 BOOL_32 canXor; ///< If client can use xor on a valid macro block 3681 /// type 3682 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3683 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3684 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3685} ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3686 3687/** 3688**************************************************************************************************** 3689* Addr2GetPreferredSurfaceSetting 3690* 3691* @brief 3692* Suggest a preferred setting for client driver to program HW register 3693**************************************************************************************************** 3694*/ 3695ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3696 ADDR_HANDLE hLib, 3697 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3698 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3699 3700/** 3701**************************************************************************************************** 3702* Addr2IsValidDisplaySwizzleMode 3703* 3704* @brief 3705* Return whether the swizzle mode is supported by DCE / DCN. 3706**************************************************************************************************** 3707*/ 3708ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3709 ADDR_HANDLE hLib, 3710 AddrSwizzleMode swizzleMode, 3711 UINT_32 bpp, 3712 bool *result); 3713 3714#if defined(__cplusplus) 3715} 3716#endif 3717 3718#endif // __ADDR_INTERFACE_H__ 3719