1/* 2 * Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#define GPU 600 28 29#include "ir3_context.h" 30#include "ir3_image.h" 31 32/* 33 * Handlers for instructions changed/added in a6xx: 34 * 35 * Starting with a6xx, isam and stbi is used for SSBOs as well; stbi and the 36 * atomic instructions (used for both SSBO and image) use a new instruction 37 * encoding compared to a4xx/a5xx. 38 */ 39 40 41/* src[] = { buffer_index, offset }. No const_index */ 42static void 43emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr, 44 struct ir3_instruction **dst) 45{ 46 struct ir3_block *b = ctx->block; 47 struct ir3_instruction *offset; 48 struct ir3_instruction *ldib; 49 50 /* can this be non-const buffer_index? how do we handle that? */ 51 int ibo_idx = ir3_ssbo_to_ibo(&ctx->so->image_mapping, nir_src_as_uint(intr->src[0])); 52 53 offset = ir3_get_src(ctx, &intr->src[2])[0]; 54 55 ldib = ir3_LDIB(b, create_immed(b, ibo_idx), 0, offset, 0); 56 ldib->regs[0]->wrmask = MASK(intr->num_components); 57 ldib->cat6.iim_val = intr->num_components; 58 ldib->cat6.d = 1; 59 ldib->cat6.type = TYPE_U32; 60 ldib->barrier_class = IR3_BARRIER_BUFFER_R; 61 ldib->barrier_conflict = IR3_BARRIER_BUFFER_W; 62 63 ir3_split_dest(b, dst, ldib, 0, intr->num_components); 64} 65 66/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */ 67static void 68emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) 69{ 70 struct ir3_block *b = ctx->block; 71 struct ir3_instruction *stib, *val, *offset; 72 /* TODO handle wrmask properly, see _store_shared().. but I think 73 * it is more a PITA than that, since blob ends up loading the 74 * masked components and writing them back out. 75 */ 76 unsigned wrmask = intr->const_index[0]; 77 unsigned ncomp = ffs(~wrmask) - 1; 78 79 /* can this be non-const buffer_index? how do we handle that? */ 80 int ibo_idx = ir3_ssbo_to_ibo(&ctx->so->image_mapping, nir_src_as_uint(intr->src[1])); 81 82 /* src0 is offset, src1 is value: 83 */ 84 val = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp); 85 offset = ir3_get_src(ctx, &intr->src[3])[0]; 86 87 stib = ir3_STIB(b, create_immed(b, ibo_idx), 0, offset, 0, val, 0); 88 stib->cat6.iim_val = ncomp; 89 stib->cat6.d = 1; 90 stib->cat6.type = TYPE_U32; 91 stib->barrier_class = IR3_BARRIER_BUFFER_W; 92 stib->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; 93 94 array_insert(b, b->keeps, stib); 95} 96 97/* 98 * SSBO atomic intrinsics 99 * 100 * All of the SSBO atomic memory operations read a value from memory, 101 * compute a new value using one of the operations below, write the new 102 * value to memory, and return the original value read. 103 * 104 * All operations take 3 sources except CompSwap that takes 4. These 105 * sources represent: 106 * 107 * 0: The SSBO buffer index. 108 * 1: The offset into the SSBO buffer of the variable that the atomic 109 * operation will operate on. 110 * 2: The data parameter to the atomic function (i.e. the value to add 111 * in ssbo_atomic_add, etc). 112 * 3: For CompSwap only: the second data parameter. 113 */ 114static struct ir3_instruction * 115emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) 116{ 117 struct ir3_block *b = ctx->block; 118 struct ir3_instruction *atomic, *ibo, *src0, *src1, *data, *dummy; 119 type_t type = TYPE_U32; 120 121 /* can this be non-const buffer_index? how do we handle that? */ 122 int ibo_idx = ir3_ssbo_to_ibo(&ctx->so->image_mapping, nir_src_as_uint(intr->src[0])); 123 ibo = create_immed(b, ibo_idx); 124 125 data = ir3_get_src(ctx, &intr->src[2])[0]; 126 127 /* So this gets a bit creative: 128 * 129 * src0 - vecN offset/coords 130 * src1.x - is actually destination register 131 * src1.y - is 'data' except for cmpxchg where src2.y is 'compare' 132 * src1.z - is 'data' for cmpxchg 133 * 134 * The combining src and dest kinda doesn't work out so well with how 135 * scheduling and RA work. So for now we create a dummy src2.x, and 136 * then in a later fixup path, insert an extra MOV out of src1.x. 137 * See ir3_a6xx_fixup_atomic_dests(). 138 * 139 * Note that nir already multiplies the offset by four 140 */ 141 dummy = create_immed(b, 0); 142 143 if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap_ir3) { 144 src0 = ir3_get_src(ctx, &intr->src[4])[0]; 145 struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0]; 146 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 147 dummy, compare, data 148 }, 3); 149 } else { 150 src0 = ir3_get_src(ctx, &intr->src[3])[0]; 151 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 152 dummy, data 153 }, 2); 154 } 155 156 switch (intr->intrinsic) { 157 case nir_intrinsic_ssbo_atomic_add_ir3: 158 atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0); 159 break; 160 case nir_intrinsic_ssbo_atomic_imin_ir3: 161 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0); 162 type = TYPE_S32; 163 break; 164 case nir_intrinsic_ssbo_atomic_umin_ir3: 165 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0); 166 break; 167 case nir_intrinsic_ssbo_atomic_imax_ir3: 168 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0); 169 type = TYPE_S32; 170 break; 171 case nir_intrinsic_ssbo_atomic_umax_ir3: 172 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0); 173 break; 174 case nir_intrinsic_ssbo_atomic_and_ir3: 175 atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0); 176 break; 177 case nir_intrinsic_ssbo_atomic_or_ir3: 178 atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0); 179 break; 180 case nir_intrinsic_ssbo_atomic_xor_ir3: 181 atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0); 182 break; 183 case nir_intrinsic_ssbo_atomic_exchange_ir3: 184 atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0); 185 break; 186 case nir_intrinsic_ssbo_atomic_comp_swap_ir3: 187 atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0); 188 break; 189 default: 190 unreachable("boo"); 191 } 192 193 atomic->cat6.iim_val = 1; 194 atomic->cat6.d = 1; 195 atomic->cat6.type = type; 196 atomic->barrier_class = IR3_BARRIER_BUFFER_W; 197 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; 198 199 /* even if nothing consume the result, we can't DCE the instruction: */ 200 array_insert(b, b->keeps, atomic); 201 202 return atomic; 203} 204 205/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */ 206static void 207emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) 208{ 209 struct ir3_block *b = ctx->block; 210 const nir_variable *var = nir_intrinsic_get_var(intr, 0); 211 struct ir3_instruction *stib; 212 struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]); 213 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); 214 unsigned ncoords = ir3_get_image_coords(var, NULL); 215 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0])); 216 unsigned ibo_idx = ir3_image_to_ibo(&ctx->so->image_mapping, slot); 217 unsigned ncomp = ir3_get_num_components_for_glformat(var->data.image.format); 218 219 /* src0 is offset, src1 is value: 220 */ 221 stib = ir3_STIB(b, create_immed(b, ibo_idx), 0, 222 ir3_create_collect(ctx, coords, ncoords), 0, 223 ir3_create_collect(ctx, value, ncomp), 0); 224 stib->cat6.iim_val = ncomp; 225 stib->cat6.d = ncoords; 226 stib->cat6.type = ir3_get_image_type(var); 227 stib->cat6.typed = true; 228 stib->barrier_class = IR3_BARRIER_IMAGE_W; 229 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; 230 231 array_insert(b, b->keeps, stib); 232} 233 234/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */ 235static struct ir3_instruction * 236emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) 237{ 238 struct ir3_block *b = ctx->block; 239 const nir_variable *var = nir_intrinsic_get_var(intr, 0); 240 struct ir3_instruction *atomic, *ibo, *src0, *src1, *dummy; 241 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); 242 struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[3])[0]; 243 unsigned ncoords = ir3_get_image_coords(var, NULL); 244 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0])); 245 unsigned ibo_idx = ir3_image_to_ibo(&ctx->so->image_mapping, slot); 246 247 ibo = create_immed(b, ibo_idx); 248 249 /* So this gets a bit creative: 250 * 251 * src0 - vecN offset/coords 252 * src1.x - is actually destination register 253 * src1.y - is 'value' except for cmpxchg where src2.y is 'compare' 254 * src1.z - is 'value' for cmpxchg 255 * 256 * The combining src and dest kinda doesn't work out so well with how 257 * scheduling and RA work. So for now we create a dummy src2.x, and 258 * then in a later fixup path, insert an extra MOV out of src1.x. 259 * See ir3_a6xx_fixup_atomic_dests(). 260 */ 261 dummy = create_immed(b, 0); 262 src0 = ir3_create_collect(ctx, coords, ncoords); 263 264 if (intr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) { 265 struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0]; 266 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 267 dummy, compare, value 268 }, 3); 269 } else { 270 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 271 dummy, value 272 }, 2); 273 } 274 275 switch (intr->intrinsic) { 276 case nir_intrinsic_image_deref_atomic_add: 277 atomic = ir3_ATOMIC_ADD_G(b, ibo, 0, src0, 0, src1, 0); 278 break; 279 case nir_intrinsic_image_deref_atomic_min: 280 atomic = ir3_ATOMIC_MIN_G(b, ibo, 0, src0, 0, src1, 0); 281 break; 282 case nir_intrinsic_image_deref_atomic_max: 283 atomic = ir3_ATOMIC_MAX_G(b, ibo, 0, src0, 0, src1, 0); 284 break; 285 case nir_intrinsic_image_deref_atomic_and: 286 atomic = ir3_ATOMIC_AND_G(b, ibo, 0, src0, 0, src1, 0); 287 break; 288 case nir_intrinsic_image_deref_atomic_or: 289 atomic = ir3_ATOMIC_OR_G(b, ibo, 0, src0, 0, src1, 0); 290 break; 291 case nir_intrinsic_image_deref_atomic_xor: 292 atomic = ir3_ATOMIC_XOR_G(b, ibo, 0, src0, 0, src1, 0); 293 break; 294 case nir_intrinsic_image_deref_atomic_exchange: 295 atomic = ir3_ATOMIC_XCHG_G(b, ibo, 0, src0, 0, src1, 0); 296 break; 297 case nir_intrinsic_image_deref_atomic_comp_swap: 298 atomic = ir3_ATOMIC_CMPXCHG_G(b, ibo, 0, src0, 0, src1, 0); 299 break; 300 default: 301 unreachable("boo"); 302 } 303 304 atomic->cat6.iim_val = 1; 305 atomic->cat6.d = ncoords; 306 atomic->cat6.type = ir3_get_image_type(var); 307 atomic->cat6.typed = true; 308 atomic->barrier_class = IR3_BARRIER_IMAGE_W; 309 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; 310 311 /* even if nothing consume the result, we can't DCE the instruction: */ 312 array_insert(b, b->keeps, atomic); 313 314 return atomic; 315} 316 317const struct ir3_context_funcs ir3_a6xx_funcs = { 318 .emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo, 319 .emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo, 320 .emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo, 321 .emit_intrinsic_store_image = emit_intrinsic_store_image, 322 .emit_intrinsic_atomic_image = emit_intrinsic_atomic_image, 323}; 324 325/* 326 * Special pass to run after instruction scheduling to insert an 327 * extra mov from src1.x to dst. This way the other compiler passes 328 * can ignore this quirk of the new instruction encoding. 329 * 330 * This might cause extra complication in the future when we support 331 * spilling, as I think we'd want to re-run the scheduling pass. One 332 * possible alternative might be to do this in the RA pass after 333 * ra_allocate() but before destroying the SSA links. (Ie. we do 334 * want to know if anything consumes the result of the atomic instr, 335 * if there is no consumer then inserting the extra mov is pointless. 336 */ 337 338static struct ir3_instruction * 339get_atomic_dest_mov(struct ir3_instruction *atomic) 340{ 341 /* if we've already created the mov-out, then re-use it: */ 342 if (atomic->data) 343 return atomic->data; 344 345 /* extract back out the 'dummy' which serves as stand-in for dest: */ 346 struct ir3_instruction *src = ssa(atomic->regs[3]); 347 debug_assert(src->opc == OPC_META_FI); 348 struct ir3_instruction *dummy = ssa(src->regs[1]); 349 350 struct ir3_instruction *mov = ir3_MOV(atomic->block, dummy, TYPE_U32); 351 352 mov->flags |= IR3_INSTR_SY; 353 354 if (atomic->regs[0]->flags & IR3_REG_ARRAY) { 355 mov->regs[0]->flags |= IR3_REG_ARRAY; 356 mov->regs[0]->array = atomic->regs[0]->array; 357 } 358 359 /* it will have already been appended to the end of the block, which 360 * isn't where we want it, so fix-up the location: 361 */ 362 list_delinit(&mov->node); 363 list_add(&mov->node, &atomic->node); 364 365 /* And because this is after instruction scheduling, we don't really 366 * have a good way to know if extra delay slots are needed. For 367 * example, if the result is consumed by an stib (storeImage()) there 368 * would be no extra delay slots in place already, but 5 are needed. 369 * Just plan for the worst and hope nobody looks at the resulting 370 * code that is generated :-( 371 */ 372 struct ir3_instruction *nop = ir3_NOP(atomic->block); 373 nop->repeat = 5; 374 375 list_delinit(&nop->node); 376 list_add(&nop->node, &mov->node); 377 378 return atomic->data = mov; 379} 380 381void 382ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so) 383{ 384 if (so->image_mapping.num_ibo == 0) 385 return; 386 387 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { 388 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { 389 instr->data = NULL; 390 } 391 } 392 393 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { 394 list_for_each_entry_safe (struct ir3_instruction, instr, &block->instr_list, node) { 395 struct ir3_register *reg; 396 397 foreach_src(reg, instr) { 398 struct ir3_instruction *src = ssa(reg); 399 400 if (!src) 401 continue; 402 403 if (is_atomic(src->opc) && (src->flags & IR3_INSTR_G)) 404 reg->instr = get_atomic_dest_mov(src); 405 } 406 } 407 408 /* we also need to fixup shader outputs: */ 409 for (unsigned i = 0; i < ir->noutputs; i++) { 410 if (!ir->outputs[i]) 411 continue; 412 if (is_atomic(ir->outputs[i]->opc) && (ir->outputs[i]->flags & IR3_INSTR_G)) 413 ir->outputs[i] = get_atomic_dest_mov(ir->outputs[i]); 414 } 415 } 416 417} 418