1/* 2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include <stdarg.h> 28 29#include "util/u_string.h" 30#include "util/u_memory.h" 31#include "util/u_math.h" 32 33#include "ir3_compiler.h" 34#include "ir3_image.h" 35#include "ir3_shader.h" 36#include "ir3_nir.h" 37 38#include "instr-a3xx.h" 39#include "ir3.h" 40#include "ir3_context.h" 41 42 43static struct ir3_instruction * 44create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n, 45 struct ir3_instruction *address, struct ir3_instruction *collect) 46{ 47 struct ir3_block *block = ctx->block; 48 struct ir3_instruction *mov; 49 struct ir3_register *src; 50 51 mov = ir3_instr_create(block, OPC_MOV); 52 mov->cat1.src_type = TYPE_U32; 53 mov->cat1.dst_type = TYPE_U32; 54 ir3_reg_create(mov, 0, 0); 55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV); 56 src->instr = collect; 57 src->size = arrsz; 58 src->array.offset = n; 59 60 ir3_instr_set_address(mov, address); 61 62 return mov; 63} 64 65static struct ir3_instruction * 66create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask) 67{ 68 struct ir3_instruction *in; 69 70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT); 71 in->inout.block = ctx->in_block; 72 ir3_reg_create(in, n, 0); 73 74 in->regs[0]->wrmask = compmask; 75 76 return in; 77} 78 79static struct ir3_instruction * 80create_input(struct ir3_context *ctx, unsigned n) 81{ 82 return create_input_compmask(ctx, n, 0x1); 83} 84 85static struct ir3_instruction * 86create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n) 87{ 88 struct ir3_block *block = ctx->block; 89 struct ir3_instruction *instr; 90 /* packed inloc is fixed up later: */ 91 struct ir3_instruction *inloc = create_immed(block, n); 92 93 if (use_ldlv) { 94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0); 95 instr->cat6.type = TYPE_U32; 96 instr->cat6.iim_val = 1; 97 } else { 98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0); 99 instr->regs[2]->wrmask = 0x3; 100 } 101 102 return instr; 103} 104 105static struct ir3_instruction * 106create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp) 107{ 108 /* first four vec4 sysval's reserved for UBOs: */ 109 /* NOTE: dp is in scalar, but there can be >4 dp components: */ 110 unsigned n = ctx->so->constbase.driver_param; 111 unsigned r = regid(n + dp / 4, dp % 4); 112 return create_uniform(ctx->block, r); 113} 114 115/* 116 * Adreno uses uint rather than having dedicated bool type, 117 * which (potentially) requires some conversion, in particular 118 * when using output of an bool instr to int input, or visa 119 * versa. 120 * 121 * | Adreno | NIR | 122 * -------+---------+-------+- 123 * true | 1 | ~0 | 124 * false | 0 | 0 | 125 * 126 * To convert from an adreno bool (uint) to nir, use: 127 * 128 * absneg.s dst, (neg)src 129 * 130 * To convert back in the other direction: 131 * 132 * absneg.s dst, (abs)arc 133 * 134 * The CP step can clean up the absneg.s that cancel each other 135 * out, and with a slight bit of extra cleverness (to recognize 136 * the instructions which produce either a 0 or 1) can eliminate 137 * the absneg.s's completely when an instruction that wants 138 * 0/1 consumes the result. For example, when a nir 'bcsel' 139 * consumes the result of 'feq'. So we should be able to get by 140 * without a boolean resolve step, and without incuring any 141 * extra penalty in instruction count. 142 */ 143 144/* NIR bool -> native (adreno): */ 145static struct ir3_instruction * 146ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr) 147{ 148 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS); 149} 150 151/* native (adreno) -> NIR bool: */ 152static struct ir3_instruction * 153ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr) 154{ 155 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG); 156} 157 158/* 159 * alu/sfu instructions: 160 */ 161 162static struct ir3_instruction * 163create_cov(struct ir3_context *ctx, struct ir3_instruction *src, 164 unsigned src_bitsize, nir_op op) 165{ 166 type_t src_type, dst_type; 167 168 switch (op) { 169 case nir_op_f2f32: 170 case nir_op_f2f16_rtne: 171 case nir_op_f2f16_rtz: 172 case nir_op_f2f16: 173 case nir_op_f2i32: 174 case nir_op_f2i16: 175 case nir_op_f2i8: 176 case nir_op_f2u32: 177 case nir_op_f2u16: 178 case nir_op_f2u8: 179 switch (src_bitsize) { 180 case 32: 181 src_type = TYPE_F32; 182 break; 183 case 16: 184 src_type = TYPE_F16; 185 break; 186 default: 187 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize); 188 } 189 break; 190 191 case nir_op_i2f32: 192 case nir_op_i2f16: 193 case nir_op_i2i32: 194 case nir_op_i2i16: 195 case nir_op_i2i8: 196 switch (src_bitsize) { 197 case 32: 198 src_type = TYPE_S32; 199 break; 200 case 16: 201 src_type = TYPE_S16; 202 break; 203 case 8: 204 src_type = TYPE_S8; 205 break; 206 default: 207 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize); 208 } 209 break; 210 211 case nir_op_u2f32: 212 case nir_op_u2f16: 213 case nir_op_u2u32: 214 case nir_op_u2u16: 215 case nir_op_u2u8: 216 switch (src_bitsize) { 217 case 32: 218 src_type = TYPE_U32; 219 break; 220 case 16: 221 src_type = TYPE_U16; 222 break; 223 case 8: 224 src_type = TYPE_U8; 225 break; 226 default: 227 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize); 228 } 229 break; 230 231 default: 232 ir3_context_error(ctx, "invalid conversion op: %u", op); 233 } 234 235 switch (op) { 236 case nir_op_f2f32: 237 case nir_op_i2f32: 238 case nir_op_u2f32: 239 dst_type = TYPE_F32; 240 break; 241 242 case nir_op_f2f16_rtne: 243 case nir_op_f2f16_rtz: 244 case nir_op_f2f16: 245 /* TODO how to handle rounding mode? */ 246 case nir_op_i2f16: 247 case nir_op_u2f16: 248 dst_type = TYPE_F16; 249 break; 250 251 case nir_op_f2i32: 252 case nir_op_i2i32: 253 dst_type = TYPE_S32; 254 break; 255 256 case nir_op_f2i16: 257 case nir_op_i2i16: 258 dst_type = TYPE_S16; 259 break; 260 261 case nir_op_f2i8: 262 case nir_op_i2i8: 263 dst_type = TYPE_S8; 264 break; 265 266 case nir_op_f2u32: 267 case nir_op_u2u32: 268 dst_type = TYPE_U32; 269 break; 270 271 case nir_op_f2u16: 272 case nir_op_u2u16: 273 dst_type = TYPE_U16; 274 break; 275 276 case nir_op_f2u8: 277 case nir_op_u2u8: 278 dst_type = TYPE_U8; 279 break; 280 281 default: 282 ir3_context_error(ctx, "invalid conversion op: %u", op); 283 } 284 285 return ir3_COV(ctx->block, src, src_type, dst_type); 286} 287 288static void 289emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) 290{ 291 const nir_op_info *info = &nir_op_infos[alu->op]; 292 struct ir3_instruction **dst, *src[info->num_inputs]; 293 unsigned bs[info->num_inputs]; /* bit size */ 294 struct ir3_block *b = ctx->block; 295 unsigned dst_sz, wrmask; 296 297 if (alu->dest.dest.is_ssa) { 298 dst_sz = alu->dest.dest.ssa.num_components; 299 wrmask = (1 << dst_sz) - 1; 300 } else { 301 dst_sz = alu->dest.dest.reg.reg->num_components; 302 wrmask = alu->dest.write_mask; 303 } 304 305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz); 306 307 /* Vectors are special in that they have non-scalarized writemasks, 308 * and just take the first swizzle channel for each argument in 309 * order into each writemask channel. 310 */ 311 if ((alu->op == nir_op_vec2) || 312 (alu->op == nir_op_vec3) || 313 (alu->op == nir_op_vec4)) { 314 315 for (int i = 0; i < info->num_inputs; i++) { 316 nir_alu_src *asrc = &alu->src[i]; 317 318 compile_assert(ctx, !asrc->abs); 319 compile_assert(ctx, !asrc->negate); 320 321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]]; 322 if (!src[i]) 323 src[i] = create_immed(ctx->block, 0); 324 dst[i] = ir3_MOV(b, src[i], TYPE_U32); 325 } 326 327 ir3_put_dst(ctx, &alu->dest.dest); 328 return; 329 } 330 331 /* We also get mov's with more than one component for mov's so 332 * handle those specially: 333 */ 334 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) { 335 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32; 336 nir_alu_src *asrc = &alu->src[0]; 337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src); 338 339 for (unsigned i = 0; i < dst_sz; i++) { 340 if (wrmask & (1 << i)) { 341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type); 342 } else { 343 dst[i] = NULL; 344 } 345 } 346 347 ir3_put_dst(ctx, &alu->dest.dest); 348 return; 349 } 350 351 /* General case: We can just grab the one used channel per src. */ 352 for (int i = 0; i < info->num_inputs; i++) { 353 unsigned chan = ffs(alu->dest.write_mask) - 1; 354 nir_alu_src *asrc = &alu->src[i]; 355 356 compile_assert(ctx, !asrc->abs); 357 compile_assert(ctx, !asrc->negate); 358 359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]]; 360 bs[i] = nir_src_bit_size(asrc->src); 361 362 compile_assert(ctx, src[i]); 363 } 364 365 switch (alu->op) { 366 case nir_op_f2f32: 367 case nir_op_f2f16_rtne: 368 case nir_op_f2f16_rtz: 369 case nir_op_f2f16: 370 case nir_op_f2i32: 371 case nir_op_f2i16: 372 case nir_op_f2i8: 373 case nir_op_f2u32: 374 case nir_op_f2u16: 375 case nir_op_f2u8: 376 case nir_op_i2f32: 377 case nir_op_i2f16: 378 case nir_op_i2i32: 379 case nir_op_i2i16: 380 case nir_op_i2i8: 381 case nir_op_u2f32: 382 case nir_op_u2f16: 383 case nir_op_u2u32: 384 case nir_op_u2u16: 385 case nir_op_u2u8: 386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op); 387 break; 388 case nir_op_f2b32: 389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0); 390 dst[0]->cat2.condition = IR3_COND_NE; 391 dst[0] = ir3_n2b(b, dst[0]); 392 break; 393 case nir_op_b2f16: 394 case nir_op_b2f32: 395 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32); 396 break; 397 case nir_op_b2i8: 398 case nir_op_b2i16: 399 case nir_op_b2i32: 400 dst[0] = ir3_b2n(b, src[0]); 401 break; 402 case nir_op_i2b32: 403 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0); 404 dst[0]->cat2.condition = IR3_COND_NE; 405 dst[0] = ir3_n2b(b, dst[0]); 406 break; 407 408 case nir_op_fneg: 409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG); 410 break; 411 case nir_op_fabs: 412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS); 413 break; 414 case nir_op_fmax: 415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0); 416 break; 417 case nir_op_fmin: 418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0); 419 break; 420 case nir_op_fsat: 421 /* if there is just a single use of the src, and it supports 422 * (sat) bit, we can just fold the (sat) flag back to the 423 * src instruction and create a mov. This is easier for cp 424 * to eliminate. 425 * 426 * TODO probably opc_cat==4 is ok too 427 */ 428 if (alu->src[0].src.is_ssa && 429 (list_length(&alu->src[0].src.ssa->uses) == 1) && 430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) { 431 src[0]->flags |= IR3_INSTR_SAT; 432 dst[0] = ir3_MOV(b, src[0], TYPE_U32); 433 } else { 434 /* otherwise generate a max.f that saturates.. blob does 435 * similar (generating a cat2 mov using max.f) 436 */ 437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0); 438 dst[0]->flags |= IR3_INSTR_SAT; 439 } 440 break; 441 case nir_op_fmul: 442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0); 443 break; 444 case nir_op_fadd: 445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0); 446 break; 447 case nir_op_fsub: 448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG); 449 break; 450 case nir_op_ffma: 451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0); 452 break; 453 case nir_op_fddx: 454 dst[0] = ir3_DSX(b, src[0], 0); 455 dst[0]->cat5.type = TYPE_F32; 456 break; 457 case nir_op_fddy: 458 dst[0] = ir3_DSY(b, src[0], 0); 459 dst[0]->cat5.type = TYPE_F32; 460 break; 461 break; 462 case nir_op_flt32: 463 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); 464 dst[0]->cat2.condition = IR3_COND_LT; 465 dst[0] = ir3_n2b(b, dst[0]); 466 break; 467 case nir_op_fge32: 468 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); 469 dst[0]->cat2.condition = IR3_COND_GE; 470 dst[0] = ir3_n2b(b, dst[0]); 471 break; 472 case nir_op_feq32: 473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); 474 dst[0]->cat2.condition = IR3_COND_EQ; 475 dst[0] = ir3_n2b(b, dst[0]); 476 break; 477 case nir_op_fne32: 478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); 479 dst[0]->cat2.condition = IR3_COND_NE; 480 dst[0] = ir3_n2b(b, dst[0]); 481 break; 482 case nir_op_fceil: 483 dst[0] = ir3_CEIL_F(b, src[0], 0); 484 break; 485 case nir_op_ffloor: 486 dst[0] = ir3_FLOOR_F(b, src[0], 0); 487 break; 488 case nir_op_ftrunc: 489 dst[0] = ir3_TRUNC_F(b, src[0], 0); 490 break; 491 case nir_op_fround_even: 492 dst[0] = ir3_RNDNE_F(b, src[0], 0); 493 break; 494 case nir_op_fsign: 495 dst[0] = ir3_SIGN_F(b, src[0], 0); 496 break; 497 498 case nir_op_fsin: 499 dst[0] = ir3_SIN(b, src[0], 0); 500 break; 501 case nir_op_fcos: 502 dst[0] = ir3_COS(b, src[0], 0); 503 break; 504 case nir_op_frsq: 505 dst[0] = ir3_RSQ(b, src[0], 0); 506 break; 507 case nir_op_frcp: 508 dst[0] = ir3_RCP(b, src[0], 0); 509 break; 510 case nir_op_flog2: 511 dst[0] = ir3_LOG2(b, src[0], 0); 512 break; 513 case nir_op_fexp2: 514 dst[0] = ir3_EXP2(b, src[0], 0); 515 break; 516 case nir_op_fsqrt: 517 dst[0] = ir3_SQRT(b, src[0], 0); 518 break; 519 520 case nir_op_iabs: 521 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS); 522 break; 523 case nir_op_iadd: 524 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0); 525 break; 526 case nir_op_iand: 527 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0); 528 break; 529 case nir_op_imax: 530 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0); 531 break; 532 case nir_op_umax: 533 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0); 534 break; 535 case nir_op_imin: 536 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0); 537 break; 538 case nir_op_umin: 539 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0); 540 break; 541 case nir_op_imul: 542 /* 543 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16) 544 * mull.u tmp0, a, b ; mul low, i.e. al * bl 545 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16 546 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16 547 */ 548 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0, 549 ir3_MADSH_M16(b, src[0], 0, src[1], 0, 550 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0); 551 break; 552 case nir_op_ineg: 553 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG); 554 break; 555 case nir_op_inot: 556 dst[0] = ir3_NOT_B(b, src[0], 0); 557 break; 558 case nir_op_ior: 559 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0); 560 break; 561 case nir_op_ishl: 562 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0); 563 break; 564 case nir_op_ishr: 565 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0); 566 break; 567 case nir_op_isub: 568 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0); 569 break; 570 case nir_op_ixor: 571 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0); 572 break; 573 case nir_op_ushr: 574 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0); 575 break; 576 case nir_op_ilt32: 577 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); 578 dst[0]->cat2.condition = IR3_COND_LT; 579 dst[0] = ir3_n2b(b, dst[0]); 580 break; 581 case nir_op_ige32: 582 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); 583 dst[0]->cat2.condition = IR3_COND_GE; 584 dst[0] = ir3_n2b(b, dst[0]); 585 break; 586 case nir_op_ieq32: 587 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); 588 dst[0]->cat2.condition = IR3_COND_EQ; 589 dst[0] = ir3_n2b(b, dst[0]); 590 break; 591 case nir_op_ine32: 592 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); 593 dst[0]->cat2.condition = IR3_COND_NE; 594 dst[0] = ir3_n2b(b, dst[0]); 595 break; 596 case nir_op_ult32: 597 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); 598 dst[0]->cat2.condition = IR3_COND_LT; 599 dst[0] = ir3_n2b(b, dst[0]); 600 break; 601 case nir_op_uge32: 602 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); 603 dst[0]->cat2.condition = IR3_COND_GE; 604 dst[0] = ir3_n2b(b, dst[0]); 605 break; 606 607 case nir_op_b32csel: { 608 struct ir3_instruction *cond = ir3_b2n(b, src[0]); 609 compile_assert(ctx, bs[1] == bs[2]); 610 /* the boolean condition is 32b even if src[1] and src[2] are 611 * half-precision, but sel.b16 wants all three src's to be the 612 * same type. 613 */ 614 if (bs[1] < 32) 615 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16); 616 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0); 617 break; 618 } 619 case nir_op_bit_count: { 620 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to 621 // double check on earlier gen's. Once half-precision support is 622 // in place, this should probably move to a NIR lowering pass: 623 struct ir3_instruction *hi, *lo; 624 625 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0), 626 TYPE_U32, TYPE_U16); 627 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16); 628 629 hi = ir3_CBITS_B(b, hi, 0); 630 lo = ir3_CBITS_B(b, lo, 0); 631 632 // TODO maybe the builders should default to making dst half-precision 633 // if the src's were half precision, to make this less awkward.. otoh 634 // we should probably just do this lowering in NIR. 635 hi->regs[0]->flags |= IR3_REG_HALF; 636 lo->regs[0]->flags |= IR3_REG_HALF; 637 638 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0); 639 dst[0]->regs[0]->flags |= IR3_REG_HALF; 640 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32); 641 break; 642 } 643 case nir_op_ifind_msb: { 644 struct ir3_instruction *cmp; 645 dst[0] = ir3_CLZ_S(b, src[0], 0); 646 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0); 647 cmp->cat2.condition = IR3_COND_GE; 648 dst[0] = ir3_SEL_B32(b, 649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0, 650 cmp, 0, dst[0], 0); 651 break; 652 } 653 case nir_op_ufind_msb: 654 dst[0] = ir3_CLZ_B(b, src[0], 0); 655 dst[0] = ir3_SEL_B32(b, 656 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0, 657 src[0], 0, dst[0], 0); 658 break; 659 case nir_op_find_lsb: 660 dst[0] = ir3_BFREV_B(b, src[0], 0); 661 dst[0] = ir3_CLZ_B(b, dst[0], 0); 662 break; 663 case nir_op_bitfield_reverse: 664 dst[0] = ir3_BFREV_B(b, src[0], 0); 665 break; 666 667 default: 668 ir3_context_error(ctx, "Unhandled ALU op: %s\n", 669 nir_op_infos[alu->op].name); 670 break; 671 } 672 673 ir3_put_dst(ctx, &alu->dest.dest); 674} 675 676/* handles direct/indirect UBO reads: */ 677static void 678emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, 679 struct ir3_instruction **dst) 680{ 681 struct ir3_block *b = ctx->block; 682 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1; 683 /* UBO addresses are the first driver params, but subtract 2 here to 684 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0 685 * is the uniforms: */ 686 unsigned ubo = regid(ctx->so->constbase.ubo, 0) - 2; 687 const unsigned ptrsz = ir3_pointer_size(ctx); 688 689 int off = 0; 690 691 /* First src is ubo index, which could either be an immed or not: */ 692 src0 = ir3_get_src(ctx, &intr->src[0])[0]; 693 if (is_same_type_mov(src0) && 694 (src0->regs[1]->flags & IR3_REG_IMMED)) { 695 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz)); 696 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1); 697 } else { 698 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz)); 699 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz)); 700 } 701 702 /* note: on 32bit gpu's base_hi is ignored and DCE'd */ 703 addr = base_lo; 704 705 if (nir_src_is_const(intr->src[1])) { 706 off += nir_src_as_uint(intr->src[1]); 707 } else { 708 /* For load_ubo_indirect, second src is indirect offset: */ 709 src1 = ir3_get_src(ctx, &intr->src[1])[0]; 710 711 /* and add offset to addr: */ 712 addr = ir3_ADD_S(b, addr, 0, src1, 0); 713 } 714 715 /* if offset is to large to encode in the ldg, split it out: */ 716 if ((off + (intr->num_components * 4)) > 1024) { 717 /* split out the minimal amount to improve the odds that 718 * cp can fit the immediate in the add.s instruction: 719 */ 720 unsigned off2 = off + (intr->num_components * 4) - 1024; 721 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0); 722 off -= off2; 723 } 724 725 if (ptrsz == 2) { 726 struct ir3_instruction *carry; 727 728 /* handle 32b rollover, ie: 729 * if (addr < base_lo) 730 * base_hi++ 731 */ 732 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0); 733 carry->cat2.condition = IR3_COND_LT; 734 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0); 735 736 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2); 737 } 738 739 for (int i = 0; i < intr->num_components; i++) { 740 struct ir3_instruction *load = 741 ir3_LDG(b, addr, 0, create_immed(b, 1), 0); 742 load->cat6.type = TYPE_U32; 743 load->cat6.src_offset = off + i * 4; /* byte offset */ 744 dst[i] = load; 745 } 746} 747 748/* src[] = { block_index } */ 749static void 750emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, 751 struct ir3_instruction **dst) 752{ 753 /* SSBO size stored as a const starting at ssbo_sizes: */ 754 unsigned blk_idx = nir_src_as_uint(intr->src[0]); 755 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) + 756 ctx->so->const_layout.ssbo_size.off[blk_idx]; 757 758 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx)); 759 760 dst[0] = create_uniform(ctx->block, idx); 761} 762 763/* src[] = { offset }. const_index[] = { base } */ 764static void 765emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr, 766 struct ir3_instruction **dst) 767{ 768 struct ir3_block *b = ctx->block; 769 struct ir3_instruction *ldl, *offset; 770 unsigned base; 771 772 offset = ir3_get_src(ctx, &intr->src[0])[0]; 773 base = nir_intrinsic_base(intr); 774 775 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0); 776 ldl->cat6.src_offset = base; 777 ldl->cat6.type = utype_dst(intr->dest); 778 ldl->regs[0]->wrmask = MASK(intr->num_components); 779 780 ldl->barrier_class = IR3_BARRIER_SHARED_R; 781 ldl->barrier_conflict = IR3_BARRIER_SHARED_W; 782 783 ir3_split_dest(b, dst, ldl, 0, intr->num_components); 784} 785 786/* src[] = { value, offset }. const_index[] = { base, write_mask } */ 787static void 788emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr) 789{ 790 struct ir3_block *b = ctx->block; 791 struct ir3_instruction *stl, *offset; 792 struct ir3_instruction * const *value; 793 unsigned base, wrmask; 794 795 value = ir3_get_src(ctx, &intr->src[0]); 796 offset = ir3_get_src(ctx, &intr->src[1])[0]; 797 798 base = nir_intrinsic_base(intr); 799 wrmask = nir_intrinsic_write_mask(intr); 800 801 /* Combine groups of consecutive enabled channels in one write 802 * message. We use ffs to find the first enabled channel and then ffs on 803 * the bit-inverse, down-shifted writemask to determine the length of 804 * the block of enabled bits. 805 * 806 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic()) 807 */ 808 while (wrmask) { 809 unsigned first_component = ffs(wrmask) - 1; 810 unsigned length = ffs(~(wrmask >> first_component)) - 1; 811 812 stl = ir3_STL(b, offset, 0, 813 ir3_create_collect(ctx, &value[first_component], length), 0, 814 create_immed(b, length), 0); 815 stl->cat6.dst_offset = first_component + base; 816 stl->cat6.type = utype_src(intr->src[0]); 817 stl->barrier_class = IR3_BARRIER_SHARED_W; 818 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; 819 820 array_insert(b, b->keeps, stl); 821 822 /* Clear the bits in the writemask that we just wrote, then try 823 * again to see if more channels are left. 824 */ 825 wrmask &= (15 << (first_component + length)); 826 } 827} 828 829/* 830 * CS shared variable atomic intrinsics 831 * 832 * All of the shared variable atomic memory operations read a value from 833 * memory, compute a new value using one of the operations below, write the 834 * new value to memory, and return the original value read. 835 * 836 * All operations take 2 sources except CompSwap that takes 3. These 837 * sources represent: 838 * 839 * 0: The offset into the shared variable storage region that the atomic 840 * operation will operate on. 841 * 1: The data parameter to the atomic function (i.e. the value to add 842 * in shared_atomic_add, etc). 843 * 2: For CompSwap only: the second data parameter. 844 */ 845static struct ir3_instruction * 846emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr) 847{ 848 struct ir3_block *b = ctx->block; 849 struct ir3_instruction *atomic, *src0, *src1; 850 type_t type = TYPE_U32; 851 852 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */ 853 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */ 854 855 switch (intr->intrinsic) { 856 case nir_intrinsic_shared_atomic_add: 857 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0); 858 break; 859 case nir_intrinsic_shared_atomic_imin: 860 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0); 861 type = TYPE_S32; 862 break; 863 case nir_intrinsic_shared_atomic_umin: 864 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0); 865 break; 866 case nir_intrinsic_shared_atomic_imax: 867 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0); 868 type = TYPE_S32; 869 break; 870 case nir_intrinsic_shared_atomic_umax: 871 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0); 872 break; 873 case nir_intrinsic_shared_atomic_and: 874 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0); 875 break; 876 case nir_intrinsic_shared_atomic_or: 877 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0); 878 break; 879 case nir_intrinsic_shared_atomic_xor: 880 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0); 881 break; 882 case nir_intrinsic_shared_atomic_exchange: 883 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0); 884 break; 885 case nir_intrinsic_shared_atomic_comp_swap: 886 /* for cmpxchg, src1 is [ui]vec2(data, compare): */ 887 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 888 ir3_get_src(ctx, &intr->src[2])[0], 889 src1, 890 }, 2); 891 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0); 892 break; 893 default: 894 unreachable("boo"); 895 } 896 897 atomic->cat6.iim_val = 1; 898 atomic->cat6.d = 1; 899 atomic->cat6.type = type; 900 atomic->barrier_class = IR3_BARRIER_SHARED_W; 901 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; 902 903 /* even if nothing consume the result, we can't DCE the instruction: */ 904 array_insert(b, b->keeps, atomic); 905 906 return atomic; 907} 908 909/* TODO handle actual indirect/dynamic case.. which is going to be weird 910 * to handle with the image_mapping table.. 911 */ 912static struct ir3_instruction * 913get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr) 914{ 915 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0])); 916 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot); 917 struct ir3_instruction *texture, *sampler; 918 919 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16); 920 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16); 921 922 return ir3_create_collect(ctx, (struct ir3_instruction*[]){ 923 sampler, 924 texture, 925 }, 2); 926} 927 928/* src[] = { deref, coord, sample_index }. const_index[] = {} */ 929static void 930emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, 931 struct ir3_instruction **dst) 932{ 933 struct ir3_block *b = ctx->block; 934 const nir_variable *var = nir_intrinsic_get_var(intr, 0); 935 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr); 936 struct ir3_instruction *sam; 937 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]); 938 struct ir3_instruction *coords[4]; 939 unsigned flags, ncoords = ir3_get_image_coords(var, &flags); 940 type_t type = ir3_get_image_type(var); 941 942 /* hmm, this seems a bit odd, but it is what blob does and (at least 943 * a5xx) just faults on bogus addresses otherwise: 944 */ 945 if (flags & IR3_INSTR_3D) { 946 flags &= ~IR3_INSTR_3D; 947 flags |= IR3_INSTR_A; 948 } 949 950 for (unsigned i = 0; i < ncoords; i++) 951 coords[i] = src0[i]; 952 953 if (ncoords == 1) 954 coords[ncoords++] = create_immed(b, 0); 955 956 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags, 957 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL); 958 959 sam->barrier_class = IR3_BARRIER_IMAGE_R; 960 sam->barrier_conflict = IR3_BARRIER_IMAGE_W; 961 962 ir3_split_dest(b, dst, sam, 0, 4); 963} 964 965static void 966emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, 967 struct ir3_instruction **dst) 968{ 969 struct ir3_block *b = ctx->block; 970 const nir_variable *var = nir_intrinsic_get_var(intr, 0); 971 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr); 972 struct ir3_instruction *sam, *lod; 973 unsigned flags, ncoords = ir3_get_image_coords(var, &flags); 974 975 lod = create_immed(b, 0); 976 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags, 977 samp_tex, lod, NULL); 978 979 /* Array size actually ends up in .w rather than .z. This doesn't 980 * matter for miplevel 0, but for higher mips the value in z is 981 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is 982 * returned, which means that we have to add 1 to it for arrays for 983 * a3xx. 984 * 985 * Note use a temporary dst and then copy, since the size of the dst 986 * array that is passed in is based on nir's understanding of the 987 * result size, not the hardware's 988 */ 989 struct ir3_instruction *tmp[4]; 990 991 ir3_split_dest(b, tmp, sam, 0, 4); 992 993 /* get_size instruction returns size in bytes instead of texels 994 * for imageBuffer, so we need to divide it by the pixel size 995 * of the image format. 996 * 997 * TODO: This is at least true on a5xx. Check other gens. 998 */ 999 enum glsl_sampler_dim dim = 1000 glsl_get_sampler_dim(glsl_without_array(var->type)); 1001 if (dim == GLSL_SAMPLER_DIM_BUF) { 1002 /* Since all the possible values the divisor can take are 1003 * power-of-two (4, 8, or 16), the division is implemented 1004 * as a shift-right. 1005 * During shader setup, the log2 of the image format's 1006 * bytes-per-pixel should have been emitted in 2nd slot of 1007 * image_dims. See ir3_shader::emit_image_dims(). 1008 */ 1009 unsigned cb = regid(ctx->so->constbase.image_dims, 0) + 1010 ctx->so->const_layout.image_dims.off[var->data.driver_location]; 1011 struct ir3_instruction *aux = create_uniform(b, cb + 1); 1012 1013 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0); 1014 } 1015 1016 for (unsigned i = 0; i < ncoords; i++) 1017 dst[i] = tmp[i]; 1018 1019 if (flags & IR3_INSTR_A) { 1020 if (ctx->compiler->levels_add_one) { 1021 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0); 1022 } else { 1023 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32); 1024 } 1025 } 1026} 1027 1028static void 1029emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr) 1030{ 1031 struct ir3_block *b = ctx->block; 1032 struct ir3_instruction *barrier; 1033 1034 switch (intr->intrinsic) { 1035 case nir_intrinsic_barrier: 1036 barrier = ir3_BAR(b); 1037 barrier->cat7.g = true; 1038 barrier->cat7.l = true; 1039 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY; 1040 barrier->barrier_class = IR3_BARRIER_EVERYTHING; 1041 break; 1042 case nir_intrinsic_memory_barrier: 1043 barrier = ir3_FENCE(b); 1044 barrier->cat7.g = true; 1045 barrier->cat7.r = true; 1046 barrier->cat7.w = true; 1047 barrier->cat7.l = true; 1048 barrier->barrier_class = IR3_BARRIER_IMAGE_W | 1049 IR3_BARRIER_BUFFER_W; 1050 barrier->barrier_conflict = 1051 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W | 1052 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; 1053 break; 1054 case nir_intrinsic_memory_barrier_atomic_counter: 1055 case nir_intrinsic_memory_barrier_buffer: 1056 barrier = ir3_FENCE(b); 1057 barrier->cat7.g = true; 1058 barrier->cat7.r = true; 1059 barrier->cat7.w = true; 1060 barrier->barrier_class = IR3_BARRIER_BUFFER_W; 1061 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R | 1062 IR3_BARRIER_BUFFER_W; 1063 break; 1064 case nir_intrinsic_memory_barrier_image: 1065 // TODO double check if this should have .g set 1066 barrier = ir3_FENCE(b); 1067 barrier->cat7.g = true; 1068 barrier->cat7.r = true; 1069 barrier->cat7.w = true; 1070 barrier->barrier_class = IR3_BARRIER_IMAGE_W; 1071 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R | 1072 IR3_BARRIER_IMAGE_W; 1073 break; 1074 case nir_intrinsic_memory_barrier_shared: 1075 barrier = ir3_FENCE(b); 1076 barrier->cat7.g = true; 1077 barrier->cat7.l = true; 1078 barrier->cat7.r = true; 1079 barrier->cat7.w = true; 1080 barrier->barrier_class = IR3_BARRIER_SHARED_W; 1081 barrier->barrier_conflict = IR3_BARRIER_SHARED_R | 1082 IR3_BARRIER_SHARED_W; 1083 break; 1084 case nir_intrinsic_group_memory_barrier: 1085 barrier = ir3_FENCE(b); 1086 barrier->cat7.g = true; 1087 barrier->cat7.l = true; 1088 barrier->cat7.r = true; 1089 barrier->cat7.w = true; 1090 barrier->barrier_class = IR3_BARRIER_SHARED_W | 1091 IR3_BARRIER_IMAGE_W | 1092 IR3_BARRIER_BUFFER_W; 1093 barrier->barrier_conflict = 1094 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W | 1095 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W | 1096 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; 1097 break; 1098 default: 1099 unreachable("boo"); 1100 } 1101 1102 /* make sure barrier doesn't get DCE'd */ 1103 array_insert(b, b->keeps, barrier); 1104} 1105 1106static void add_sysval_input_compmask(struct ir3_context *ctx, 1107 gl_system_value slot, unsigned compmask, 1108 struct ir3_instruction *instr) 1109{ 1110 struct ir3_shader_variant *so = ctx->so; 1111 unsigned r = regid(so->inputs_count, 0); 1112 unsigned n = so->inputs_count++; 1113 1114 so->inputs[n].sysval = true; 1115 so->inputs[n].slot = slot; 1116 so->inputs[n].compmask = compmask; 1117 so->inputs[n].regid = r; 1118 so->inputs[n].interpolate = INTERP_MODE_FLAT; 1119 so->total_in++; 1120 1121 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1); 1122 ctx->ir->inputs[r] = instr; 1123} 1124 1125static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot, 1126 struct ir3_instruction *instr) 1127{ 1128 add_sysval_input_compmask(ctx, slot, 0x1, instr); 1129} 1130 1131static struct ir3_instruction * 1132get_barycentric_centroid(struct ir3_context *ctx) 1133{ 1134 if (!ctx->ij_centroid) { 1135 struct ir3_instruction *xy[2]; 1136 struct ir3_instruction *ij; 1137 1138 ij = create_input_compmask(ctx, 0, 0x3); 1139 ir3_split_dest(ctx->block, xy, ij, 0, 2); 1140 1141 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2); 1142 1143 add_sysval_input_compmask(ctx, 1144 SYSTEM_VALUE_BARYCENTRIC_CENTROID, 1145 0x3, ij); 1146 } 1147 1148 return ctx->ij_centroid; 1149} 1150 1151static struct ir3_instruction * 1152get_barycentric_sample(struct ir3_context *ctx) 1153{ 1154 if (!ctx->ij_sample) { 1155 struct ir3_instruction *xy[2]; 1156 struct ir3_instruction *ij; 1157 1158 ij = create_input_compmask(ctx, 0, 0x3); 1159 ir3_split_dest(ctx->block, xy, ij, 0, 2); 1160 1161 ctx->ij_sample = ir3_create_collect(ctx, xy, 2); 1162 1163 add_sysval_input_compmask(ctx, 1164 SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 1165 0x3, ij); 1166 } 1167 1168 return ctx->ij_sample; 1169} 1170 1171static struct ir3_instruction * 1172get_barycentric_pixel(struct ir3_context *ctx) 1173{ 1174 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch 1175 * this to create ij_pixel only on demand: 1176 */ 1177 return ctx->ij_pixel; 1178} 1179 1180static struct ir3_instruction * 1181get_frag_coord(struct ir3_context *ctx) 1182{ 1183 if (!ctx->frag_coord) { 1184 struct ir3_block *b = ctx->block; 1185 struct ir3_instruction *xyzw[4]; 1186 struct ir3_instruction *hw_frag_coord; 1187 1188 hw_frag_coord = create_input_compmask(ctx, 0, 0xf); 1189 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4); 1190 1191 /* for frag_coord.xy, we get unsigned values.. we need 1192 * to subtract (integer) 8 and divide by 16 (right- 1193 * shift by 4) then convert to float: 1194 * 1195 * sub.s tmp, src, 8 1196 * shr.b tmp, tmp, 4 1197 * mov.u32f32 dst, tmp 1198 * 1199 */ 1200 for (int i = 0; i < 2; i++) { 1201 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0, 1202 create_immed(b, 8), 0); 1203 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0, 1204 create_immed(b, 4), 0); 1205 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32); 1206 } 1207 1208 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4); 1209 1210 add_sysval_input_compmask(ctx, 1211 SYSTEM_VALUE_FRAG_COORD, 1212 0xf, hw_frag_coord); 1213 1214 ctx->so->frag_coord = true; 1215 } 1216 1217 return ctx->frag_coord; 1218} 1219 1220static void 1221emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) 1222{ 1223 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic]; 1224 struct ir3_instruction **dst; 1225 struct ir3_instruction * const *src; 1226 struct ir3_block *b = ctx->block; 1227 int idx, comp; 1228 1229 if (info->has_dest) { 1230 unsigned n = nir_intrinsic_dest_components(intr); 1231 dst = ir3_get_dst(ctx, &intr->dest, n); 1232 } else { 1233 dst = NULL; 1234 } 1235 1236 switch (intr->intrinsic) { 1237 case nir_intrinsic_load_uniform: 1238 idx = nir_intrinsic_base(intr); 1239 if (nir_src_is_const(intr->src[0])) { 1240 idx += nir_src_as_uint(intr->src[0]); 1241 for (int i = 0; i < intr->num_components; i++) { 1242 dst[i] = create_uniform(b, idx + i); 1243 } 1244 } else { 1245 src = ir3_get_src(ctx, &intr->src[0]); 1246 for (int i = 0; i < intr->num_components; i++) { 1247 dst[i] = create_uniform_indirect(b, idx + i, 1248 ir3_get_addr(ctx, src[0], 1)); 1249 } 1250 /* NOTE: if relative addressing is used, we set 1251 * constlen in the compiler (to worst-case value) 1252 * since we don't know in the assembler what the max 1253 * addr reg value can be: 1254 */ 1255 ctx->so->constlen = ctx->s->num_uniforms; 1256 } 1257 break; 1258 case nir_intrinsic_load_ubo: 1259 emit_intrinsic_load_ubo(ctx, intr, dst); 1260 break; 1261 case nir_intrinsic_load_frag_coord: 1262 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4); 1263 break; 1264 case nir_intrinsic_load_sample_pos_from_id: { 1265 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32, 1266 * but that doesn't seem necessary. 1267 */ 1268 struct ir3_instruction *offset = 1269 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0); 1270 offset->regs[0]->wrmask = 0x3; 1271 offset->cat5.type = TYPE_F32; 1272 1273 ir3_split_dest(b, dst, offset, 0, 2); 1274 1275 break; 1276 } 1277 case nir_intrinsic_load_size_ir3: 1278 if (!ctx->ij_size) { 1279 ctx->ij_size = create_input(ctx, 0); 1280 1281 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 1282 ctx->ij_size); 1283 } 1284 dst[0] = ctx->ij_size; 1285 break; 1286 case nir_intrinsic_load_barycentric_centroid: 1287 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2); 1288 break; 1289 case nir_intrinsic_load_barycentric_sample: 1290 if (ctx->so->key.msaa) { 1291 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2); 1292 } else { 1293 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2); 1294 } 1295 break; 1296 case nir_intrinsic_load_barycentric_pixel: 1297 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2); 1298 break; 1299 case nir_intrinsic_load_interpolated_input: 1300 idx = nir_intrinsic_base(intr); 1301 comp = nir_intrinsic_component(intr); 1302 src = ir3_get_src(ctx, &intr->src[0]); 1303 if (nir_src_is_const(intr->src[1])) { 1304 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2); 1305 idx += nir_src_as_uint(intr->src[1]); 1306 for (int i = 0; i < intr->num_components; i++) { 1307 unsigned inloc = idx * 4 + i + comp; 1308 if (ctx->so->inputs[idx].bary && 1309 !ctx->so->inputs[idx].use_ldlv) { 1310 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0); 1311 } else { 1312 /* for non-varyings use the pre-setup input, since 1313 * that is easier than mapping things back to a 1314 * nir_variable to figure out what it is. 1315 */ 1316 dst[i] = ctx->ir->inputs[inloc]; 1317 } 1318 } 1319 } else { 1320 ir3_context_error(ctx, "unhandled"); 1321 } 1322 break; 1323 case nir_intrinsic_load_input: 1324 idx = nir_intrinsic_base(intr); 1325 comp = nir_intrinsic_component(intr); 1326 if (nir_src_is_const(intr->src[0])) { 1327 idx += nir_src_as_uint(intr->src[0]); 1328 for (int i = 0; i < intr->num_components; i++) { 1329 unsigned n = idx * 4 + i + comp; 1330 dst[i] = ctx->ir->inputs[n]; 1331 compile_assert(ctx, ctx->ir->inputs[n]); 1332 } 1333 } else { 1334 src = ir3_get_src(ctx, &intr->src[0]); 1335 struct ir3_instruction *collect = 1336 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs); 1337 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4); 1338 for (int i = 0; i < intr->num_components; i++) { 1339 unsigned n = idx * 4 + i + comp; 1340 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs, 1341 n, addr, collect); 1342 } 1343 } 1344 break; 1345 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets' 1346 * pass and replaced by an ir3-specifc version that adds the 1347 * dword-offset in the last source. 1348 */ 1349 case nir_intrinsic_load_ssbo_ir3: 1350 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst); 1351 break; 1352 case nir_intrinsic_store_ssbo_ir3: 1353 if ((ctx->so->type == MESA_SHADER_FRAGMENT) && 1354 !ctx->s->info.fs.early_fragment_tests) 1355 ctx->so->no_earlyz = true; 1356 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr); 1357 break; 1358 case nir_intrinsic_get_buffer_size: 1359 emit_intrinsic_ssbo_size(ctx, intr, dst); 1360 break; 1361 case nir_intrinsic_ssbo_atomic_add_ir3: 1362 case nir_intrinsic_ssbo_atomic_imin_ir3: 1363 case nir_intrinsic_ssbo_atomic_umin_ir3: 1364 case nir_intrinsic_ssbo_atomic_imax_ir3: 1365 case nir_intrinsic_ssbo_atomic_umax_ir3: 1366 case nir_intrinsic_ssbo_atomic_and_ir3: 1367 case nir_intrinsic_ssbo_atomic_or_ir3: 1368 case nir_intrinsic_ssbo_atomic_xor_ir3: 1369 case nir_intrinsic_ssbo_atomic_exchange_ir3: 1370 case nir_intrinsic_ssbo_atomic_comp_swap_ir3: 1371 if ((ctx->so->type == MESA_SHADER_FRAGMENT) && 1372 !ctx->s->info.fs.early_fragment_tests) 1373 ctx->so->no_earlyz = true; 1374 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr); 1375 break; 1376 case nir_intrinsic_load_shared: 1377 emit_intrinsic_load_shared(ctx, intr, dst); 1378 break; 1379 case nir_intrinsic_store_shared: 1380 emit_intrinsic_store_shared(ctx, intr); 1381 break; 1382 case nir_intrinsic_shared_atomic_add: 1383 case nir_intrinsic_shared_atomic_imin: 1384 case nir_intrinsic_shared_atomic_umin: 1385 case nir_intrinsic_shared_atomic_imax: 1386 case nir_intrinsic_shared_atomic_umax: 1387 case nir_intrinsic_shared_atomic_and: 1388 case nir_intrinsic_shared_atomic_or: 1389 case nir_intrinsic_shared_atomic_xor: 1390 case nir_intrinsic_shared_atomic_exchange: 1391 case nir_intrinsic_shared_atomic_comp_swap: 1392 dst[0] = emit_intrinsic_atomic_shared(ctx, intr); 1393 break; 1394 case nir_intrinsic_image_deref_load: 1395 emit_intrinsic_load_image(ctx, intr, dst); 1396 break; 1397 case nir_intrinsic_image_deref_store: 1398 if ((ctx->so->type == MESA_SHADER_FRAGMENT) && 1399 !ctx->s->info.fs.early_fragment_tests) 1400 ctx->so->no_earlyz = true; 1401 ctx->funcs->emit_intrinsic_store_image(ctx, intr); 1402 break; 1403 case nir_intrinsic_image_deref_size: 1404 emit_intrinsic_image_size(ctx, intr, dst); 1405 break; 1406 case nir_intrinsic_image_deref_atomic_add: 1407 case nir_intrinsic_image_deref_atomic_min: 1408 case nir_intrinsic_image_deref_atomic_max: 1409 case nir_intrinsic_image_deref_atomic_and: 1410 case nir_intrinsic_image_deref_atomic_or: 1411 case nir_intrinsic_image_deref_atomic_xor: 1412 case nir_intrinsic_image_deref_atomic_exchange: 1413 case nir_intrinsic_image_deref_atomic_comp_swap: 1414 if ((ctx->so->type == MESA_SHADER_FRAGMENT) && 1415 !ctx->s->info.fs.early_fragment_tests) 1416 ctx->so->no_earlyz = true; 1417 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr); 1418 break; 1419 case nir_intrinsic_barrier: 1420 case nir_intrinsic_memory_barrier: 1421 case nir_intrinsic_group_memory_barrier: 1422 case nir_intrinsic_memory_barrier_atomic_counter: 1423 case nir_intrinsic_memory_barrier_buffer: 1424 case nir_intrinsic_memory_barrier_image: 1425 case nir_intrinsic_memory_barrier_shared: 1426 emit_intrinsic_barrier(ctx, intr); 1427 /* note that blk ptr no longer valid, make that obvious: */ 1428 b = NULL; 1429 break; 1430 case nir_intrinsic_store_output: 1431 idx = nir_intrinsic_base(intr); 1432 comp = nir_intrinsic_component(intr); 1433 compile_assert(ctx, nir_src_is_const(intr->src[1])); 1434 idx += nir_src_as_uint(intr->src[1]); 1435 1436 src = ir3_get_src(ctx, &intr->src[0]); 1437 for (int i = 0; i < intr->num_components; i++) { 1438 unsigned n = idx * 4 + i + comp; 1439 ctx->ir->outputs[n] = src[i]; 1440 } 1441 break; 1442 case nir_intrinsic_load_base_vertex: 1443 case nir_intrinsic_load_first_vertex: 1444 if (!ctx->basevertex) { 1445 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE); 1446 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex); 1447 } 1448 dst[0] = ctx->basevertex; 1449 break; 1450 case nir_intrinsic_load_vertex_id_zero_base: 1451 case nir_intrinsic_load_vertex_id: 1452 if (!ctx->vertex_id) { 1453 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ? 1454 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE; 1455 ctx->vertex_id = create_input(ctx, 0); 1456 add_sysval_input(ctx, sv, ctx->vertex_id); 1457 } 1458 dst[0] = ctx->vertex_id; 1459 break; 1460 case nir_intrinsic_load_instance_id: 1461 if (!ctx->instance_id) { 1462 ctx->instance_id = create_input(ctx, 0); 1463 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 1464 ctx->instance_id); 1465 } 1466 dst[0] = ctx->instance_id; 1467 break; 1468 case nir_intrinsic_load_sample_id: 1469 ctx->so->per_samp = true; 1470 /* fall-thru */ 1471 case nir_intrinsic_load_sample_id_no_per_sample: 1472 if (!ctx->samp_id) { 1473 ctx->samp_id = create_input(ctx, 0); 1474 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF; 1475 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 1476 ctx->samp_id); 1477 } 1478 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32); 1479 break; 1480 case nir_intrinsic_load_sample_mask_in: 1481 if (!ctx->samp_mask_in) { 1482 ctx->samp_mask_in = create_input(ctx, 0); 1483 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 1484 ctx->samp_mask_in); 1485 } 1486 dst[0] = ctx->samp_mask_in; 1487 break; 1488 case nir_intrinsic_load_user_clip_plane: 1489 idx = nir_intrinsic_ucp_id(intr); 1490 for (int i = 0; i < intr->num_components; i++) { 1491 unsigned n = idx * 4 + i; 1492 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n); 1493 } 1494 break; 1495 case nir_intrinsic_load_front_face: 1496 if (!ctx->frag_face) { 1497 ctx->so->frag_face = true; 1498 ctx->frag_face = create_input(ctx, 0); 1499 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face); 1500 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF; 1501 } 1502 /* for fragface, we get -1 for back and 0 for front. However this is 1503 * the inverse of what nir expects (where ~0 is true). 1504 */ 1505 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32); 1506 dst[0] = ir3_NOT_B(b, dst[0], 0); 1507 break; 1508 case nir_intrinsic_load_local_invocation_id: 1509 if (!ctx->local_invocation_id) { 1510 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7); 1511 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 1512 0x7, ctx->local_invocation_id); 1513 } 1514 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3); 1515 break; 1516 case nir_intrinsic_load_work_group_id: 1517 if (!ctx->work_group_id) { 1518 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7); 1519 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 1520 0x7, ctx->work_group_id); 1521 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH; 1522 } 1523 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3); 1524 break; 1525 case nir_intrinsic_load_num_work_groups: 1526 for (int i = 0; i < intr->num_components; i++) { 1527 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i); 1528 } 1529 break; 1530 case nir_intrinsic_load_local_group_size: 1531 for (int i = 0; i < intr->num_components; i++) { 1532 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i); 1533 } 1534 break; 1535 case nir_intrinsic_discard_if: 1536 case nir_intrinsic_discard: { 1537 struct ir3_instruction *cond, *kill; 1538 1539 if (intr->intrinsic == nir_intrinsic_discard_if) { 1540 /* conditional discard: */ 1541 src = ir3_get_src(ctx, &intr->src[0]); 1542 cond = ir3_b2n(b, src[0]); 1543 } else { 1544 /* unconditional discard: */ 1545 cond = create_immed(b, 1); 1546 } 1547 1548 /* NOTE: only cmps.*.* can write p0.x: */ 1549 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0); 1550 cond->cat2.condition = IR3_COND_NE; 1551 1552 /* condition always goes in predicate register: */ 1553 cond->regs[0]->num = regid(REG_P0, 0); 1554 1555 kill = ir3_KILL(b, cond, 0); 1556 array_insert(ctx->ir, ctx->ir->predicates, kill); 1557 1558 array_insert(b, b->keeps, kill); 1559 ctx->so->no_earlyz = true; 1560 1561 break; 1562 } 1563 default: 1564 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n", 1565 nir_intrinsic_infos[intr->intrinsic].name); 1566 break; 1567 } 1568 1569 if (info->has_dest) 1570 ir3_put_dst(ctx, &intr->dest); 1571} 1572 1573static void 1574emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr) 1575{ 1576 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def, 1577 instr->def.num_components); 1578 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32; 1579 1580 for (int i = 0; i < instr->def.num_components; i++) 1581 dst[i] = create_immed_typed(ctx->block, instr->value[i].u32, type); 1582} 1583 1584static void 1585emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef) 1586{ 1587 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def, 1588 undef->def.num_components); 1589 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32; 1590 1591 /* backend doesn't want undefined instructions, so just plug 1592 * in 0.0.. 1593 */ 1594 for (int i = 0; i < undef->def.num_components; i++) 1595 dst[i] = create_immed_typed(ctx->block, fui(0.0), type); 1596} 1597 1598/* 1599 * texture fetch/sample instructions: 1600 */ 1601 1602static void 1603tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp) 1604{ 1605 unsigned coords, flags = 0; 1606 1607 /* note: would use tex->coord_components.. except txs.. also, 1608 * since array index goes after shadow ref, we don't want to 1609 * count it: 1610 */ 1611 switch (tex->sampler_dim) { 1612 case GLSL_SAMPLER_DIM_1D: 1613 case GLSL_SAMPLER_DIM_BUF: 1614 coords = 1; 1615 break; 1616 case GLSL_SAMPLER_DIM_2D: 1617 case GLSL_SAMPLER_DIM_RECT: 1618 case GLSL_SAMPLER_DIM_EXTERNAL: 1619 case GLSL_SAMPLER_DIM_MS: 1620 coords = 2; 1621 break; 1622 case GLSL_SAMPLER_DIM_3D: 1623 case GLSL_SAMPLER_DIM_CUBE: 1624 coords = 3; 1625 flags |= IR3_INSTR_3D; 1626 break; 1627 default: 1628 unreachable("bad sampler_dim"); 1629 } 1630 1631 if (tex->is_shadow && tex->op != nir_texop_lod) 1632 flags |= IR3_INSTR_S; 1633 1634 if (tex->is_array && tex->op != nir_texop_lod) 1635 flags |= IR3_INSTR_A; 1636 1637 *flagsp = flags; 1638 *coordsp = coords; 1639} 1640 1641/* Gets the sampler/texture idx as a hvec2. Which could either be dynamic 1642 * or immediate (in which case it will get lowered later to a non .s2en 1643 * version of the tex instruction which encode tex/samp as immediates: 1644 */ 1645static struct ir3_instruction * 1646get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex) 1647{ 1648 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset); 1649 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset); 1650 struct ir3_instruction *texture, *sampler; 1651 1652 if (texture_idx >= 0) { 1653 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0]; 1654 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16); 1655 } else { 1656 /* TODO what to do for dynamic case? I guess we only need the 1657 * max index for astc srgb workaround so maybe not a problem 1658 * to worry about if we don't enable indirect samplers for 1659 * a4xx? 1660 */ 1661 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index); 1662 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16); 1663 } 1664 1665 if (sampler_idx >= 0) { 1666 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0]; 1667 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16); 1668 } else { 1669 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16); 1670 } 1671 1672 return ir3_create_collect(ctx, (struct ir3_instruction*[]){ 1673 sampler, 1674 texture, 1675 }, 2); 1676} 1677 1678static void 1679emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) 1680{ 1681 struct ir3_block *b = ctx->block; 1682 struct ir3_instruction **dst, *sam, *src0[12], *src1[4]; 1683 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy; 1684 struct ir3_instruction *lod, *compare, *proj, *sample_index; 1685 bool has_bias = false, has_lod = false, has_proj = false, has_off = false; 1686 unsigned i, coords, flags, ncomp; 1687 unsigned nsrc0 = 0, nsrc1 = 0; 1688 type_t type; 1689 opc_t opc = 0; 1690 1691 ncomp = nir_dest_num_components(tex->dest); 1692 1693 coord = off = ddx = ddy = NULL; 1694 lod = proj = compare = sample_index = NULL; 1695 1696 dst = ir3_get_dst(ctx, &tex->dest, ncomp); 1697 1698 for (unsigned i = 0; i < tex->num_srcs; i++) { 1699 switch (tex->src[i].src_type) { 1700 case nir_tex_src_coord: 1701 coord = ir3_get_src(ctx, &tex->src[i].src); 1702 break; 1703 case nir_tex_src_bias: 1704 lod = ir3_get_src(ctx, &tex->src[i].src)[0]; 1705 has_bias = true; 1706 break; 1707 case nir_tex_src_lod: 1708 lod = ir3_get_src(ctx, &tex->src[i].src)[0]; 1709 has_lod = true; 1710 break; 1711 case nir_tex_src_comparator: /* shadow comparator */ 1712 compare = ir3_get_src(ctx, &tex->src[i].src)[0]; 1713 break; 1714 case nir_tex_src_projector: 1715 proj = ir3_get_src(ctx, &tex->src[i].src)[0]; 1716 has_proj = true; 1717 break; 1718 case nir_tex_src_offset: 1719 off = ir3_get_src(ctx, &tex->src[i].src); 1720 has_off = true; 1721 break; 1722 case nir_tex_src_ddx: 1723 ddx = ir3_get_src(ctx, &tex->src[i].src); 1724 break; 1725 case nir_tex_src_ddy: 1726 ddy = ir3_get_src(ctx, &tex->src[i].src); 1727 break; 1728 case nir_tex_src_ms_index: 1729 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0]; 1730 break; 1731 case nir_tex_src_texture_offset: 1732 case nir_tex_src_sampler_offset: 1733 /* handled in get_tex_samp_src() */ 1734 break; 1735 default: 1736 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n", 1737 tex->src[i].src_type); 1738 return; 1739 } 1740 } 1741 1742 switch (tex->op) { 1743 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break; 1744 case nir_texop_txb: opc = OPC_SAMB; break; 1745 case nir_texop_txl: opc = OPC_SAML; break; 1746 case nir_texop_txd: opc = OPC_SAMGQ; break; 1747 case nir_texop_txf: opc = OPC_ISAML; break; 1748 case nir_texop_lod: opc = OPC_GETLOD; break; 1749 case nir_texop_tg4: 1750 /* NOTE: a4xx might need to emulate gather w/ txf (this is 1751 * what blob does, seems gather is broken?), and a3xx did 1752 * not support it (but probably could also emulate). 1753 */ 1754 switch (tex->component) { 1755 case 0: opc = OPC_GATHER4R; break; 1756 case 1: opc = OPC_GATHER4G; break; 1757 case 2: opc = OPC_GATHER4B; break; 1758 case 3: opc = OPC_GATHER4A; break; 1759 } 1760 break; 1761 case nir_texop_txf_ms_fb: 1762 case nir_texop_txf_ms: opc = OPC_ISAMM; break; 1763 default: 1764 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op); 1765 return; 1766 } 1767 1768 tex_info(tex, &flags, &coords); 1769 1770 /* 1771 * lay out the first argument in the proper order: 1772 * - actual coordinates first 1773 * - shadow reference 1774 * - array index 1775 * - projection w 1776 * - starting at offset 4, dpdx.xy, dpdy.xy 1777 * 1778 * bias/lod go into the second arg 1779 */ 1780 1781 /* insert tex coords: */ 1782 for (i = 0; i < coords; i++) 1783 src0[i] = coord[i]; 1784 1785 nsrc0 = i; 1786 1787 /* scale up integer coords for TXF based on the LOD */ 1788 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) { 1789 assert(has_lod); 1790 for (i = 0; i < coords; i++) 1791 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0); 1792 } 1793 1794 if (coords == 1) { 1795 /* hw doesn't do 1d, so we treat it as 2d with 1796 * height of 1, and patch up the y coord. 1797 */ 1798 if (is_isam(opc)) { 1799 src0[nsrc0++] = create_immed(b, 0); 1800 } else { 1801 src0[nsrc0++] = create_immed(b, fui(0.5)); 1802 } 1803 } 1804 1805 if (tex->is_shadow && tex->op != nir_texop_lod) 1806 src0[nsrc0++] = compare; 1807 1808 if (tex->is_array && tex->op != nir_texop_lod) { 1809 struct ir3_instruction *idx = coord[coords]; 1810 1811 /* the array coord for cube arrays needs 0.5 added to it */ 1812 if (ctx->compiler->array_index_add_half && !is_isam(opc)) 1813 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0); 1814 1815 src0[nsrc0++] = idx; 1816 } 1817 1818 if (has_proj) { 1819 src0[nsrc0++] = proj; 1820 flags |= IR3_INSTR_P; 1821 } 1822 1823 /* pad to 4, then ddx/ddy: */ 1824 if (tex->op == nir_texop_txd) { 1825 while (nsrc0 < 4) 1826 src0[nsrc0++] = create_immed(b, fui(0.0)); 1827 for (i = 0; i < coords; i++) 1828 src0[nsrc0++] = ddx[i]; 1829 if (coords < 2) 1830 src0[nsrc0++] = create_immed(b, fui(0.0)); 1831 for (i = 0; i < coords; i++) 1832 src0[nsrc0++] = ddy[i]; 1833 if (coords < 2) 1834 src0[nsrc0++] = create_immed(b, fui(0.0)); 1835 } 1836 1837 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml 1838 * with scaled x coord according to requested sample: 1839 */ 1840 if (opc == OPC_ISAMM) { 1841 if (ctx->compiler->txf_ms_with_isaml) { 1842 /* the samples are laid out in x dimension as 1843 * 0 1 2 3 1844 * x_ms = (x << ms) + sample_index; 1845 */ 1846 struct ir3_instruction *ms; 1847 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3); 1848 1849 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0); 1850 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0); 1851 1852 opc = OPC_ISAML; 1853 } else { 1854 src0[nsrc0++] = sample_index; 1855 } 1856 } 1857 1858 /* 1859 * second argument (if applicable): 1860 * - offsets 1861 * - lod 1862 * - bias 1863 */ 1864 if (has_off | has_lod | has_bias) { 1865 if (has_off) { 1866 unsigned off_coords = coords; 1867 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE) 1868 off_coords--; 1869 for (i = 0; i < off_coords; i++) 1870 src1[nsrc1++] = off[i]; 1871 if (off_coords < 2) 1872 src1[nsrc1++] = create_immed(b, fui(0.0)); 1873 flags |= IR3_INSTR_O; 1874 } 1875 1876 if (has_lod | has_bias) 1877 src1[nsrc1++] = lod; 1878 } 1879 1880 switch (tex->dest_type) { 1881 case nir_type_invalid: 1882 case nir_type_float: 1883 type = TYPE_F32; 1884 break; 1885 case nir_type_int: 1886 type = TYPE_S32; 1887 break; 1888 case nir_type_uint: 1889 case nir_type_bool: 1890 type = TYPE_U32; 1891 break; 1892 default: 1893 unreachable("bad dest_type"); 1894 } 1895 1896 if (opc == OPC_GETLOD) 1897 type = TYPE_U32; 1898 1899 struct ir3_instruction *samp_tex; 1900 1901 if (tex->op == nir_texop_txf_ms_fb) { 1902 /* only expect a single txf_ms_fb per shader: */ 1903 compile_assert(ctx, !ctx->so->fb_read); 1904 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT); 1905 1906 ctx->so->fb_read = true; 1907 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){ 1908 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16), 1909 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16), 1910 }, 2); 1911 1912 ctx->so->num_samp++; 1913 } else { 1914 samp_tex = get_tex_samp_tex_src(ctx, tex); 1915 } 1916 1917 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0); 1918 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1); 1919 1920 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags, 1921 samp_tex, col0, col1); 1922 1923 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) { 1924 /* only need first 3 components: */ 1925 sam->regs[0]->wrmask = 0x7; 1926 ir3_split_dest(b, dst, sam, 0, 3); 1927 1928 /* we need to sample the alpha separately with a non-ASTC 1929 * texture state: 1930 */ 1931 sam = ir3_SAM(b, opc, type, 0b1000, flags, 1932 samp_tex, col0, col1); 1933 1934 array_insert(ctx->ir, ctx->ir->astc_srgb, sam); 1935 1936 /* fixup .w component: */ 1937 ir3_split_dest(b, &dst[3], sam, 3, 1); 1938 } else { 1939 /* normal (non-workaround) case: */ 1940 ir3_split_dest(b, dst, sam, 0, ncomp); 1941 } 1942 1943 /* GETLOD returns results in 4.8 fixed point */ 1944 if (opc == OPC_GETLOD) { 1945 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256)); 1946 1947 compile_assert(ctx, tex->dest_type == nir_type_float); 1948 for (i = 0; i < 2; i++) { 1949 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0, 1950 factor, 0); 1951 } 1952 } 1953 1954 ir3_put_dst(ctx, &tex->dest); 1955} 1956 1957static void 1958emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex) 1959{ 1960 struct ir3_block *b = ctx->block; 1961 struct ir3_instruction **dst, *sam; 1962 1963 dst = ir3_get_dst(ctx, &tex->dest, 1); 1964 1965 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0, 1966 get_tex_samp_tex_src(ctx, tex), NULL, NULL); 1967 1968 /* even though there is only one component, since it ends 1969 * up in .z rather than .x, we need a split_dest() 1970 */ 1971 ir3_split_dest(b, dst, sam, 0, 3); 1972 1973 /* The # of levels comes from getinfo.z. We need to add 1 to it, since 1974 * the value in TEX_CONST_0 is zero-based. 1975 */ 1976 if (ctx->compiler->levels_add_one) 1977 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0); 1978 1979 ir3_put_dst(ctx, &tex->dest); 1980} 1981 1982static void 1983emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex) 1984{ 1985 struct ir3_block *b = ctx->block; 1986 struct ir3_instruction **dst, *sam; 1987 struct ir3_instruction *lod; 1988 unsigned flags, coords; 1989 1990 tex_info(tex, &flags, &coords); 1991 1992 /* Actually we want the number of dimensions, not coordinates. This 1993 * distinction only matters for cubes. 1994 */ 1995 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE) 1996 coords = 2; 1997 1998 dst = ir3_get_dst(ctx, &tex->dest, 4); 1999 2000 compile_assert(ctx, tex->num_srcs == 1); 2001 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod); 2002 2003 lod = ir3_get_src(ctx, &tex->src[0].src)[0]; 2004 2005 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags, 2006 get_tex_samp_tex_src(ctx, tex), lod, NULL); 2007 2008 ir3_split_dest(b, dst, sam, 0, 4); 2009 2010 /* Array size actually ends up in .w rather than .z. This doesn't 2011 * matter for miplevel 0, but for higher mips the value in z is 2012 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is 2013 * returned, which means that we have to add 1 to it for arrays. 2014 */ 2015 if (tex->is_array) { 2016 if (ctx->compiler->levels_add_one) { 2017 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0); 2018 } else { 2019 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32); 2020 } 2021 } 2022 2023 ir3_put_dst(ctx, &tex->dest); 2024} 2025 2026static void 2027emit_jump(struct ir3_context *ctx, nir_jump_instr *jump) 2028{ 2029 switch (jump->type) { 2030 case nir_jump_break: 2031 case nir_jump_continue: 2032 case nir_jump_return: 2033 /* I *think* we can simply just ignore this, and use the 2034 * successor block link to figure out where we need to 2035 * jump to for break/continue 2036 */ 2037 break; 2038 default: 2039 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type); 2040 break; 2041 } 2042} 2043 2044static void 2045emit_instr(struct ir3_context *ctx, nir_instr *instr) 2046{ 2047 switch (instr->type) { 2048 case nir_instr_type_alu: 2049 emit_alu(ctx, nir_instr_as_alu(instr)); 2050 break; 2051 case nir_instr_type_deref: 2052 /* ignored, handled as part of the intrinsic they are src to */ 2053 break; 2054 case nir_instr_type_intrinsic: 2055 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr)); 2056 break; 2057 case nir_instr_type_load_const: 2058 emit_load_const(ctx, nir_instr_as_load_const(instr)); 2059 break; 2060 case nir_instr_type_ssa_undef: 2061 emit_undef(ctx, nir_instr_as_ssa_undef(instr)); 2062 break; 2063 case nir_instr_type_tex: { 2064 nir_tex_instr *tex = nir_instr_as_tex(instr); 2065 /* couple tex instructions get special-cased: 2066 */ 2067 switch (tex->op) { 2068 case nir_texop_txs: 2069 emit_tex_txs(ctx, tex); 2070 break; 2071 case nir_texop_query_levels: 2072 emit_tex_query_levels(ctx, tex); 2073 break; 2074 default: 2075 emit_tex(ctx, tex); 2076 break; 2077 } 2078 break; 2079 } 2080 case nir_instr_type_jump: 2081 emit_jump(ctx, nir_instr_as_jump(instr)); 2082 break; 2083 case nir_instr_type_phi: 2084 /* we have converted phi webs to regs in NIR by now */ 2085 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type); 2086 break; 2087 case nir_instr_type_call: 2088 case nir_instr_type_parallel_copy: 2089 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type); 2090 break; 2091 } 2092} 2093 2094static struct ir3_block * 2095get_block(struct ir3_context *ctx, const nir_block *nblock) 2096{ 2097 struct ir3_block *block; 2098 struct hash_entry *hentry; 2099 unsigned i; 2100 2101 hentry = _mesa_hash_table_search(ctx->block_ht, nblock); 2102 if (hentry) 2103 return hentry->data; 2104 2105 block = ir3_block_create(ctx->ir); 2106 block->nblock = nblock; 2107 _mesa_hash_table_insert(ctx->block_ht, nblock, block); 2108 2109 block->predecessors_count = nblock->predecessors->entries; 2110 block->predecessors = ralloc_array_size(block, 2111 sizeof(block->predecessors[0]), block->predecessors_count); 2112 i = 0; 2113 set_foreach(nblock->predecessors, sentry) { 2114 block->predecessors[i++] = get_block(ctx, sentry->key); 2115 } 2116 2117 return block; 2118} 2119 2120static void 2121emit_block(struct ir3_context *ctx, nir_block *nblock) 2122{ 2123 struct ir3_block *block = get_block(ctx, nblock); 2124 2125 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) { 2126 if (nblock->successors[i]) { 2127 block->successors[i] = 2128 get_block(ctx, nblock->successors[i]); 2129 } 2130 } 2131 2132 ctx->block = block; 2133 list_addtail(&block->node, &ctx->ir->block_list); 2134 2135 /* re-emit addr register in each block if needed: */ 2136 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) { 2137 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL); 2138 ctx->addr_ht[i] = NULL; 2139 } 2140 2141 nir_foreach_instr(instr, nblock) { 2142 ctx->cur_instr = instr; 2143 emit_instr(ctx, instr); 2144 ctx->cur_instr = NULL; 2145 if (ctx->error) 2146 return; 2147 } 2148} 2149 2150static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list); 2151 2152static void 2153emit_if(struct ir3_context *ctx, nir_if *nif) 2154{ 2155 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0]; 2156 2157 ctx->block->condition = 2158 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition)); 2159 2160 emit_cf_list(ctx, &nif->then_list); 2161 emit_cf_list(ctx, &nif->else_list); 2162} 2163 2164static void 2165emit_loop(struct ir3_context *ctx, nir_loop *nloop) 2166{ 2167 emit_cf_list(ctx, &nloop->body); 2168} 2169 2170static void 2171stack_push(struct ir3_context *ctx) 2172{ 2173 ctx->stack++; 2174 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack); 2175} 2176 2177static void 2178stack_pop(struct ir3_context *ctx) 2179{ 2180 compile_assert(ctx, ctx->stack > 0); 2181 ctx->stack--; 2182} 2183 2184static void 2185emit_cf_list(struct ir3_context *ctx, struct exec_list *list) 2186{ 2187 foreach_list_typed(nir_cf_node, node, node, list) { 2188 switch (node->type) { 2189 case nir_cf_node_block: 2190 emit_block(ctx, nir_cf_node_as_block(node)); 2191 break; 2192 case nir_cf_node_if: 2193 stack_push(ctx); 2194 emit_if(ctx, nir_cf_node_as_if(node)); 2195 stack_pop(ctx); 2196 break; 2197 case nir_cf_node_loop: 2198 stack_push(ctx); 2199 emit_loop(ctx, nir_cf_node_as_loop(node)); 2200 stack_pop(ctx); 2201 break; 2202 case nir_cf_node_function: 2203 ir3_context_error(ctx, "TODO\n"); 2204 break; 2205 } 2206 } 2207} 2208 2209/* emit stream-out code. At this point, the current block is the original 2210 * (nir) end block, and nir ensures that all flow control paths terminate 2211 * into the end block. We re-purpose the original end block to generate 2212 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional 2213 * block holding stream-out write instructions, followed by the new end 2214 * block: 2215 * 2216 * blockOrigEnd { 2217 * p0.x = (vtxcnt < maxvtxcnt) 2218 * // succs: blockStreamOut, blockNewEnd 2219 * } 2220 * blockStreamOut { 2221 * ... stream-out instructions ... 2222 * // succs: blockNewEnd 2223 * } 2224 * blockNewEnd { 2225 * } 2226 */ 2227static void 2228emit_stream_out(struct ir3_context *ctx) 2229{ 2230 struct ir3_shader_variant *v = ctx->so; 2231 struct ir3 *ir = ctx->ir; 2232 struct ir3_stream_output_info *strmout = 2233 &ctx->so->shader->stream_output; 2234 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block; 2235 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond; 2236 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS]; 2237 2238 /* create vtxcnt input in input block at top of shader, 2239 * so that it is seen as live over the entire duration 2240 * of the shader: 2241 */ 2242 vtxcnt = create_input(ctx, 0); 2243 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt); 2244 2245 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX); 2246 2247 /* at this point, we are at the original 'end' block, 2248 * re-purpose this block to stream-out condition, then 2249 * append stream-out block and new-end block 2250 */ 2251 orig_end_block = ctx->block; 2252 2253// TODO these blocks need to update predecessors.. 2254// maybe w/ store_global intrinsic, we could do this 2255// stuff in nir->nir pass 2256 2257 stream_out_block = ir3_block_create(ir); 2258 list_addtail(&stream_out_block->node, &ir->block_list); 2259 2260 new_end_block = ir3_block_create(ir); 2261 list_addtail(&new_end_block->node, &ir->block_list); 2262 2263 orig_end_block->successors[0] = stream_out_block; 2264 orig_end_block->successors[1] = new_end_block; 2265 stream_out_block->successors[0] = new_end_block; 2266 2267 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */ 2268 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0); 2269 cond->regs[0]->num = regid(REG_P0, 0); 2270 cond->cat2.condition = IR3_COND_LT; 2271 2272 /* condition goes on previous block to the conditional, 2273 * since it is used to pick which of the two successor 2274 * paths to take: 2275 */ 2276 orig_end_block->condition = cond; 2277 2278 /* switch to stream_out_block to generate the stream-out 2279 * instructions: 2280 */ 2281 ctx->block = stream_out_block; 2282 2283 /* Calculate base addresses based on vtxcnt. Instructions 2284 * generated for bases not used in following loop will be 2285 * stripped out in the backend. 2286 */ 2287 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) { 2288 unsigned stride = strmout->stride[i]; 2289 struct ir3_instruction *base, *off; 2290 2291 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i)); 2292 2293 /* 24-bit should be enough: */ 2294 off = ir3_MUL_U(ctx->block, vtxcnt, 0, 2295 create_immed(ctx->block, stride * 4), 0); 2296 2297 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0); 2298 } 2299 2300 /* Generate the per-output store instructions: */ 2301 for (unsigned i = 0; i < strmout->num_outputs; i++) { 2302 for (unsigned j = 0; j < strmout->output[i].num_components; j++) { 2303 unsigned c = j + strmout->output[i].start_component; 2304 struct ir3_instruction *base, *out, *stg; 2305 2306 base = bases[strmout->output[i].output_buffer]; 2307 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)]; 2308 2309 stg = ir3_STG(ctx->block, base, 0, out, 0, 2310 create_immed(ctx->block, 1), 0); 2311 stg->cat6.type = TYPE_U32; 2312 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4; 2313 2314 array_insert(ctx->block, ctx->block->keeps, stg); 2315 } 2316 } 2317 2318 /* and finally switch to the new_end_block: */ 2319 ctx->block = new_end_block; 2320} 2321 2322static void 2323emit_function(struct ir3_context *ctx, nir_function_impl *impl) 2324{ 2325 nir_metadata_require(impl, nir_metadata_block_index); 2326 2327 compile_assert(ctx, ctx->stack == 0); 2328 2329 emit_cf_list(ctx, &impl->body); 2330 emit_block(ctx, impl->end_block); 2331 2332 compile_assert(ctx, ctx->stack == 0); 2333 2334 /* at this point, we should have a single empty block, 2335 * into which we emit the 'end' instruction. 2336 */ 2337 compile_assert(ctx, list_empty(&ctx->block->instr_list)); 2338 2339 /* If stream-out (aka transform-feedback) enabled, emit the 2340 * stream-out instructions, followed by a new empty block (into 2341 * which the 'end' instruction lands). 2342 * 2343 * NOTE: it is done in this order, rather than inserting before 2344 * we emit end_block, because NIR guarantees that all blocks 2345 * flow into end_block, and that end_block has no successors. 2346 * So by re-purposing end_block as the first block of stream- 2347 * out, we guarantee that all exit paths flow into the stream- 2348 * out instructions. 2349 */ 2350 if ((ctx->compiler->gpu_id < 500) && 2351 (ctx->so->shader->stream_output.num_outputs > 0) && 2352 !ctx->so->binning_pass) { 2353 debug_assert(ctx->so->type == MESA_SHADER_VERTEX); 2354 emit_stream_out(ctx); 2355 } 2356 2357 ir3_END(ctx->block); 2358} 2359 2360static void 2361setup_input(struct ir3_context *ctx, nir_variable *in) 2362{ 2363 struct ir3_shader_variant *so = ctx->so; 2364 unsigned ncomp = glsl_get_components(in->type); 2365 unsigned n = in->data.driver_location; 2366 unsigned frac = in->data.location_frac; 2367 unsigned slot = in->data.location; 2368 2369 /* skip unread inputs, we could end up with (for example), unsplit 2370 * matrix/etc inputs in the case they are not read, so just silently 2371 * skip these. 2372 */ 2373 if (ncomp > 4) 2374 return; 2375 2376 so->inputs[n].slot = slot; 2377 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1; 2378 so->inputs_count = MAX2(so->inputs_count, n + 1); 2379 so->inputs[n].interpolate = in->data.interpolation; 2380 so->inputs[n].ncomp = ncomp; 2381 2382 if (ctx->so->type == MESA_SHADER_FRAGMENT) { 2383 2384 /* if any varyings have 'sample' qualifer, that triggers us 2385 * to run in per-sample mode: 2386 */ 2387 so->per_samp |= in->data.sample; 2388 2389 for (int i = 0; i < ncomp; i++) { 2390 struct ir3_instruction *instr = NULL; 2391 unsigned idx = (n * 4) + i + frac; 2392 2393 if (slot == VARYING_SLOT_POS) { 2394 ir3_context_error(ctx, "fragcoord should be a sysval!\n"); 2395 } else if (slot == VARYING_SLOT_PNTC) { 2396 /* see for example st_nir_fixup_varying_slots().. this is 2397 * maybe a bit mesa/st specific. But we need things to line 2398 * up for this in fdN_program: 2399 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0); 2400 * if (emit->sprite_coord_enable & texmask) { 2401 * ... 2402 * } 2403 */ 2404 so->inputs[n].slot = VARYING_SLOT_VAR8; 2405 so->inputs[n].bary = true; 2406 instr = create_frag_input(ctx, false, idx); 2407 } else { 2408 /* detect the special case for front/back colors where 2409 * we need to do flat vs smooth shading depending on 2410 * rast state: 2411 */ 2412 if (in->data.interpolation == INTERP_MODE_NONE) { 2413 switch (slot) { 2414 case VARYING_SLOT_COL0: 2415 case VARYING_SLOT_COL1: 2416 case VARYING_SLOT_BFC0: 2417 case VARYING_SLOT_BFC1: 2418 so->inputs[n].rasterflat = true; 2419 break; 2420 default: 2421 break; 2422 } 2423 } 2424 2425 if (ctx->compiler->flat_bypass) { 2426 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) || 2427 (so->inputs[n].rasterflat && ctx->so->key.rasterflat)) 2428 so->inputs[n].use_ldlv = true; 2429 } 2430 2431 so->inputs[n].bary = true; 2432 2433 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx); 2434 } 2435 2436 compile_assert(ctx, idx < ctx->ir->ninputs); 2437 2438 ctx->ir->inputs[idx] = instr; 2439 } 2440 } else if (ctx->so->type == MESA_SHADER_VERTEX) { 2441 for (int i = 0; i < ncomp; i++) { 2442 unsigned idx = (n * 4) + i + frac; 2443 compile_assert(ctx, idx < ctx->ir->ninputs); 2444 ctx->ir->inputs[idx] = create_input(ctx, idx); 2445 } 2446 } else { 2447 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type); 2448 } 2449 2450 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) { 2451 so->total_in += ncomp; 2452 } 2453} 2454 2455/* Initially we assign non-packed inloc's for varyings, as we don't really 2456 * know up-front which components will be unused. After all the compilation 2457 * stages we scan the shader to see which components are actually used, and 2458 * re-pack the inlocs to eliminate unneeded varyings. 2459 */ 2460static void 2461pack_inlocs(struct ir3_context *ctx) 2462{ 2463 struct ir3_shader_variant *so = ctx->so; 2464 uint8_t used_components[so->inputs_count]; 2465 2466 memset(used_components, 0, sizeof(used_components)); 2467 2468 /* 2469 * First Step: scan shader to find which bary.f/ldlv remain: 2470 */ 2471 2472 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) { 2473 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { 2474 if (is_input(instr)) { 2475 unsigned inloc = instr->regs[1]->iim_val; 2476 unsigned i = inloc / 4; 2477 unsigned j = inloc % 4; 2478 2479 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED); 2480 compile_assert(ctx, i < so->inputs_count); 2481 2482 used_components[i] |= 1 << j; 2483 } 2484 } 2485 } 2486 2487 /* 2488 * Second Step: reassign varying inloc/slots: 2489 */ 2490 2491 unsigned actual_in = 0; 2492 unsigned inloc = 0; 2493 2494 for (unsigned i = 0; i < so->inputs_count; i++) { 2495 unsigned compmask = 0, maxcomp = 0; 2496 2497 so->inputs[i].ncomp = 0; 2498 so->inputs[i].inloc = inloc; 2499 so->inputs[i].bary = false; 2500 2501 for (unsigned j = 0; j < 4; j++) { 2502 if (!(used_components[i] & (1 << j))) 2503 continue; 2504 2505 compmask |= (1 << j); 2506 actual_in++; 2507 so->inputs[i].ncomp++; 2508 maxcomp = j + 1; 2509 2510 /* at this point, since used_components[i] mask is only 2511 * considering varyings (ie. not sysvals) we know this 2512 * is a varying: 2513 */ 2514 so->inputs[i].bary = true; 2515 } 2516 2517 if (so->inputs[i].bary) { 2518 so->varying_in++; 2519 so->inputs[i].compmask = (1 << maxcomp) - 1; 2520 inloc += maxcomp; 2521 } 2522 } 2523 2524 /* 2525 * Third Step: reassign packed inloc's: 2526 */ 2527 2528 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) { 2529 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { 2530 if (is_input(instr)) { 2531 unsigned inloc = instr->regs[1]->iim_val; 2532 unsigned i = inloc / 4; 2533 unsigned j = inloc % 4; 2534 2535 instr->regs[1]->iim_val = so->inputs[i].inloc + j; 2536 } 2537 } 2538 } 2539} 2540 2541static void 2542setup_output(struct ir3_context *ctx, nir_variable *out) 2543{ 2544 struct ir3_shader_variant *so = ctx->so; 2545 unsigned ncomp = glsl_get_components(out->type); 2546 unsigned n = out->data.driver_location; 2547 unsigned frac = out->data.location_frac; 2548 unsigned slot = out->data.location; 2549 unsigned comp = 0; 2550 2551 if (ctx->so->type == MESA_SHADER_FRAGMENT) { 2552 switch (slot) { 2553 case FRAG_RESULT_DEPTH: 2554 comp = 2; /* tgsi will write to .z component */ 2555 so->writes_pos = true; 2556 break; 2557 case FRAG_RESULT_COLOR: 2558 so->color0_mrt = 1; 2559 break; 2560 case FRAG_RESULT_SAMPLE_MASK: 2561 so->writes_smask = true; 2562 break; 2563 default: 2564 if (slot >= FRAG_RESULT_DATA0) 2565 break; 2566 ir3_context_error(ctx, "unknown FS output name: %s\n", 2567 gl_frag_result_name(slot)); 2568 } 2569 } else if (ctx->so->type == MESA_SHADER_VERTEX) { 2570 switch (slot) { 2571 case VARYING_SLOT_POS: 2572 so->writes_pos = true; 2573 break; 2574 case VARYING_SLOT_PSIZ: 2575 so->writes_psize = true; 2576 break; 2577 case VARYING_SLOT_COL0: 2578 case VARYING_SLOT_COL1: 2579 case VARYING_SLOT_BFC0: 2580 case VARYING_SLOT_BFC1: 2581 case VARYING_SLOT_FOGC: 2582 case VARYING_SLOT_CLIP_DIST0: 2583 case VARYING_SLOT_CLIP_DIST1: 2584 case VARYING_SLOT_CLIP_VERTEX: 2585 break; 2586 default: 2587 if (slot >= VARYING_SLOT_VAR0) 2588 break; 2589 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7)) 2590 break; 2591 ir3_context_error(ctx, "unknown VS output name: %s\n", 2592 gl_varying_slot_name(slot)); 2593 } 2594 } else { 2595 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type); 2596 } 2597 2598 compile_assert(ctx, n < ARRAY_SIZE(so->outputs)); 2599 2600 so->outputs[n].slot = slot; 2601 so->outputs[n].regid = regid(n, comp); 2602 so->outputs_count = MAX2(so->outputs_count, n + 1); 2603 2604 for (int i = 0; i < ncomp; i++) { 2605 unsigned idx = (n * 4) + i + frac; 2606 compile_assert(ctx, idx < ctx->ir->noutputs); 2607 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0)); 2608 } 2609 2610 /* if varying packing doesn't happen, we could end up in a situation 2611 * with "holes" in the output, and since the per-generation code that 2612 * sets up varying linkage registers doesn't expect to have more than 2613 * one varying per vec4 slot, pad the holes. 2614 * 2615 * Note that this should probably generate a performance warning of 2616 * some sort. 2617 */ 2618 for (int i = 0; i < frac; i++) { 2619 unsigned idx = (n * 4) + i; 2620 if (!ctx->ir->outputs[idx]) { 2621 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0)); 2622 } 2623 } 2624} 2625 2626static int 2627max_drvloc(struct exec_list *vars) 2628{ 2629 int drvloc = -1; 2630 nir_foreach_variable(var, vars) { 2631 drvloc = MAX2(drvloc, (int)var->data.driver_location); 2632 } 2633 return drvloc; 2634} 2635 2636static const unsigned max_sysvals[] = { 2637 [MESA_SHADER_FRAGMENT] = 24, // TODO 2638 [MESA_SHADER_VERTEX] = 16, 2639 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need? 2640 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need? 2641}; 2642 2643static void 2644emit_instructions(struct ir3_context *ctx) 2645{ 2646 unsigned ninputs, noutputs; 2647 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s); 2648 2649 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4; 2650 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4; 2651 2652 /* we need to leave room for sysvals: 2653 */ 2654 ninputs += max_sysvals[ctx->so->type]; 2655 2656 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs); 2657 2658 /* Create inputs in first block: */ 2659 ctx->block = get_block(ctx, nir_start_block(fxn)); 2660 ctx->in_block = ctx->block; 2661 list_addtail(&ctx->block->node, &ctx->ir->block_list); 2662 2663 ninputs -= max_sysvals[ctx->so->type]; 2664 2665 /* for fragment shader, the vcoord input register is used as the 2666 * base for bary.f varying fetch instrs: 2667 * 2668 * TODO defer creating ctx->ij_pixel and corresponding sysvals 2669 * until emit_intrinsic when we know they are actually needed. 2670 * For now, we defer creating ctx->ij_centroid, etc, since we 2671 * only need ij_pixel for "old style" varying inputs (ie. 2672 * tgsi_to_nir) 2673 */ 2674 struct ir3_instruction *vcoord = NULL; 2675 if (ctx->so->type == MESA_SHADER_FRAGMENT) { 2676 struct ir3_instruction *xy[2]; 2677 2678 vcoord = create_input_compmask(ctx, 0, 0x3); 2679 ir3_split_dest(ctx->block, xy, vcoord, 0, 2); 2680 2681 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2); 2682 } 2683 2684 /* Setup inputs: */ 2685 nir_foreach_variable(var, &ctx->s->inputs) { 2686 setup_input(ctx, var); 2687 } 2688 2689 /* Defer add_sysval_input() stuff until after setup_inputs(), 2690 * because sysvals need to be appended after varyings: 2691 */ 2692 if (vcoord) { 2693 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL, 2694 0x3, vcoord); 2695 } 2696 2697 /* Setup outputs: */ 2698 nir_foreach_variable(var, &ctx->s->outputs) { 2699 setup_output(ctx, var); 2700 } 2701 2702 /* Find # of samplers: */ 2703 nir_foreach_variable(var, &ctx->s->uniforms) { 2704 ctx->so->num_samp += glsl_type_get_sampler_count(var->type); 2705 /* just assume that we'll be reading from images.. if it 2706 * is write-only we don't have to count it, but not sure 2707 * if there is a good way to know? 2708 */ 2709 ctx->so->num_samp += glsl_type_get_image_count(var->type); 2710 } 2711 2712 /* NOTE: need to do something more clever when we support >1 fxn */ 2713 nir_foreach_register(reg, &fxn->registers) { 2714 ir3_declare_array(ctx, reg); 2715 } 2716 /* And emit the body: */ 2717 ctx->impl = fxn; 2718 emit_function(ctx, fxn); 2719} 2720 2721/* from NIR perspective, we actually have varying inputs. But the varying 2722 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The 2723 * only actual inputs are the sysvals. 2724 */ 2725static void 2726fixup_frag_inputs(struct ir3_context *ctx) 2727{ 2728 struct ir3_shader_variant *so = ctx->so; 2729 struct ir3 *ir = ctx->ir; 2730 unsigned i = 0; 2731 2732 /* sysvals should appear at the end of the inputs, drop everything else: */ 2733 while ((i < so->inputs_count) && !so->inputs[i].sysval) 2734 i++; 2735 2736 /* at IR level, inputs are always blocks of 4 scalars: */ 2737 i *= 4; 2738 2739 ir->inputs = &ir->inputs[i]; 2740 ir->ninputs -= i; 2741} 2742 2743/* Fixup tex sampler state for astc/srgb workaround instructions. We 2744 * need to assign the tex state indexes for these after we know the 2745 * max tex index. 2746 */ 2747static void 2748fixup_astc_srgb(struct ir3_context *ctx) 2749{ 2750 struct ir3_shader_variant *so = ctx->so; 2751 /* indexed by original tex idx, value is newly assigned alpha sampler 2752 * state tex idx. Zero is invalid since there is at least one sampler 2753 * if we get here. 2754 */ 2755 unsigned alt_tex_state[16] = {0}; 2756 unsigned tex_idx = ctx->max_texture_index + 1; 2757 unsigned idx = 0; 2758 2759 so->astc_srgb.base = tex_idx; 2760 2761 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) { 2762 struct ir3_instruction *sam = ctx->ir->astc_srgb[i]; 2763 2764 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state)); 2765 2766 if (alt_tex_state[sam->cat5.tex] == 0) { 2767 /* assign new alternate/alpha tex state slot: */ 2768 alt_tex_state[sam->cat5.tex] = tex_idx++; 2769 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex; 2770 so->astc_srgb.count++; 2771 } 2772 2773 sam->cat5.tex = alt_tex_state[sam->cat5.tex]; 2774 } 2775} 2776 2777static void 2778fixup_binning_pass(struct ir3_context *ctx) 2779{ 2780 struct ir3_shader_variant *so = ctx->so; 2781 struct ir3 *ir = ctx->ir; 2782 unsigned i, j; 2783 2784 for (i = 0, j = 0; i < so->outputs_count; i++) { 2785 unsigned slot = so->outputs[i].slot; 2786 2787 /* throw away everything but first position/psize */ 2788 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) { 2789 if (i != j) { 2790 so->outputs[j] = so->outputs[i]; 2791 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0]; 2792 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1]; 2793 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2]; 2794 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3]; 2795 } 2796 j++; 2797 } 2798 } 2799 so->outputs_count = j; 2800 ir->noutputs = j * 4; 2801} 2802 2803int 2804ir3_compile_shader_nir(struct ir3_compiler *compiler, 2805 struct ir3_shader_variant *so) 2806{ 2807 struct ir3_context *ctx; 2808 struct ir3 *ir; 2809 struct ir3_instruction **inputs; 2810 unsigned i; 2811 int ret = 0, max_bary; 2812 2813 assert(!so->ir); 2814 2815 ctx = ir3_context_init(compiler, so); 2816 if (!ctx) { 2817 DBG("INIT failed!"); 2818 ret = -1; 2819 goto out; 2820 } 2821 2822 emit_instructions(ctx); 2823 2824 if (ctx->error) { 2825 DBG("EMIT failed!"); 2826 ret = -1; 2827 goto out; 2828 } 2829 2830 ir = so->ir = ctx->ir; 2831 2832 /* keep track of the inputs from TGSI perspective.. */ 2833 inputs = ir->inputs; 2834 2835 /* but fixup actual inputs for frag shader: */ 2836 if (so->type == MESA_SHADER_FRAGMENT) 2837 fixup_frag_inputs(ctx); 2838 2839 /* at this point, for binning pass, throw away unneeded outputs: */ 2840 if (so->binning_pass && (ctx->compiler->gpu_id < 600)) 2841 fixup_binning_pass(ctx); 2842 2843 /* if we want half-precision outputs, mark the output registers 2844 * as half: 2845 */ 2846 if (so->key.half_precision) { 2847 for (i = 0; i < ir->noutputs; i++) { 2848 struct ir3_instruction *out = ir->outputs[i]; 2849 2850 if (!out) 2851 continue; 2852 2853 /* if frag shader writes z, that needs to be full precision: */ 2854 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH) 2855 continue; 2856 2857 out->regs[0]->flags |= IR3_REG_HALF; 2858 /* output could be a fanout (ie. texture fetch output) 2859 * in which case we need to propagate the half-reg flag 2860 * up to the definer so that RA sees it: 2861 */ 2862 if (out->opc == OPC_META_FO) { 2863 out = out->regs[1]->instr; 2864 out->regs[0]->flags |= IR3_REG_HALF; 2865 } 2866 2867 if (out->opc == OPC_MOV) { 2868 out->cat1.dst_type = half_type(out->cat1.dst_type); 2869 } 2870 } 2871 } 2872 2873 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2874 printf("BEFORE CP:\n"); 2875 ir3_print(ir); 2876 } 2877 2878 ir3_cp(ir, so); 2879 2880 /* at this point, for binning pass, throw away unneeded outputs: 2881 * Note that for a6xx and later, we do this after ir3_cp to ensure 2882 * that the uniform/constant layout for BS and VS matches, so that 2883 * we can re-use same VS_CONST state group. 2884 */ 2885 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) 2886 fixup_binning_pass(ctx); 2887 2888 /* Insert mov if there's same instruction for each output. 2889 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow 2890 */ 2891 for (int i = ir->noutputs - 1; i >= 0; i--) { 2892 if (!ir->outputs[i]) 2893 continue; 2894 for (unsigned j = 0; j < i; j++) { 2895 if (ir->outputs[i] == ir->outputs[j]) { 2896 ir->outputs[i] = 2897 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32); 2898 } 2899 } 2900 } 2901 2902 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2903 printf("BEFORE GROUPING:\n"); 2904 ir3_print(ir); 2905 } 2906 2907 ir3_sched_add_deps(ir); 2908 2909 /* Group left/right neighbors, inserting mov's where needed to 2910 * solve conflicts: 2911 */ 2912 ir3_group(ir); 2913 2914 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2915 printf("AFTER GROUPING:\n"); 2916 ir3_print(ir); 2917 } 2918 2919 ir3_depth(ir); 2920 2921 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2922 printf("AFTER DEPTH:\n"); 2923 ir3_print(ir); 2924 } 2925 2926 /* do Sethi–Ullman numbering before scheduling: */ 2927 ir3_sun(ir); 2928 2929 ret = ir3_sched(ir); 2930 if (ret) { 2931 DBG("SCHED failed!"); 2932 goto out; 2933 } 2934 2935 if (compiler->gpu_id >= 600) { 2936 ir3_a6xx_fixup_atomic_dests(ir, so); 2937 } 2938 2939 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2940 printf("AFTER SCHED:\n"); 2941 ir3_print(ir); 2942 } 2943 2944 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face); 2945 if (ret) { 2946 DBG("RA failed!"); 2947 goto out; 2948 } 2949 2950 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 2951 printf("AFTER RA:\n"); 2952 ir3_print(ir); 2953 } 2954 2955 if (so->type == MESA_SHADER_FRAGMENT) 2956 pack_inlocs(ctx); 2957 2958 /* fixup input/outputs: */ 2959 for (i = 0; i < so->outputs_count; i++) { 2960 /* sometimes we get outputs that don't write the .x coord, like: 2961 * 2962 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0) 2963 * 2964 * Presumably the result of varying packing and then eliminating 2965 * some unneeded varyings? Just skip head to the first valid 2966 * component of the output. 2967 */ 2968 for (unsigned j = 0; j < 4; j++) { 2969 struct ir3_instruction *instr = ir->outputs[(i*4) + j]; 2970 if (instr) { 2971 so->outputs[i].regid = instr->regs[0]->num; 2972 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF); 2973 break; 2974 } 2975 } 2976 } 2977 2978 /* Note that some or all channels of an input may be unused: */ 2979 for (i = 0; i < so->inputs_count; i++) { 2980 unsigned j, reg = regid(63,0); 2981 bool half = false; 2982 for (j = 0; j < 4; j++) { 2983 struct ir3_instruction *in = inputs[(i*4) + j]; 2984 2985 if (in && !(in->flags & IR3_INSTR_UNUSED)) { 2986 reg = in->regs[0]->num - j; 2987 if (half) { 2988 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF); 2989 } else { 2990 half = !!(in->regs[0]->flags & IR3_REG_HALF); 2991 } 2992 } 2993 } 2994 so->inputs[i].regid = reg; 2995 so->inputs[i].half = half; 2996 } 2997 2998 if (ctx->astc_srgb) 2999 fixup_astc_srgb(ctx); 3000 3001 /* We need to do legalize after (for frag shader's) the "bary.f" 3002 * offsets (inloc) have been assigned. 3003 */ 3004 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary); 3005 3006 if (ir3_shader_debug & IR3_DBG_OPTMSGS) { 3007 printf("AFTER LEGALIZE:\n"); 3008 ir3_print(ir); 3009 } 3010 3011 so->branchstack = ctx->max_stack; 3012 3013 /* Note that actual_in counts inputs that are not bary.f'd for FS: */ 3014 if (so->type == MESA_SHADER_FRAGMENT) 3015 so->total_in = max_bary + 1; 3016 3017 so->max_sun = ir->max_sun; 3018 3019out: 3020 if (ret) { 3021 if (so->ir) 3022 ir3_destroy(so->ir); 3023 so->ir = NULL; 3024 } 3025 ir3_context_free(ctx); 3026 3027 return ret; 3028} 3029