1#ifndef A4XX_XML 2#define A4XX_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17) 14- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53) 15- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-03 18:24:29) 16- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2019-05-03 18:24:29) 19- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-03 18:24:37) 20- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23Copyright (C) 2013-2018 by the following authors: 24- Rob Clark <robdclark@gmail.com> (robclark) 25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27Permission is hereby granted, free of charge, to any person obtaining 28a copy of this software and associated documentation files (the 29"Software"), to deal in the Software without restriction, including 30without limitation the rights to use, copy, modify, merge, publish, 31distribute, sublicense, and/or sell copies of the Software, and to 32permit persons to whom the Software is furnished to do so, subject to 33the following conditions: 34 35The above copyright notice and this permission notice (including the 36next paragraph) shall be included in all copies or substantial 37portions of the Software. 38 39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46*/ 47 48 49enum a4xx_color_fmt { 50 RB4_A8_UNORM = 1, 51 RB4_R8_UNORM = 2, 52 RB4_R8_SNORM = 3, 53 RB4_R8_UINT = 4, 54 RB4_R8_SINT = 5, 55 RB4_R4G4B4A4_UNORM = 8, 56 RB4_R5G5B5A1_UNORM = 10, 57 RB4_R5G6B5_UNORM = 14, 58 RB4_R8G8_UNORM = 15, 59 RB4_R8G8_SNORM = 16, 60 RB4_R8G8_UINT = 17, 61 RB4_R8G8_SINT = 18, 62 RB4_R16_UNORM = 19, 63 RB4_R16_SNORM = 20, 64 RB4_R16_FLOAT = 21, 65 RB4_R16_UINT = 22, 66 RB4_R16_SINT = 23, 67 RB4_R8G8B8_UNORM = 25, 68 RB4_R8G8B8A8_UNORM = 26, 69 RB4_R8G8B8A8_SNORM = 28, 70 RB4_R8G8B8A8_UINT = 29, 71 RB4_R8G8B8A8_SINT = 30, 72 RB4_R10G10B10A2_UNORM = 31, 73 RB4_R10G10B10A2_UINT = 34, 74 RB4_R11G11B10_FLOAT = 39, 75 RB4_R16G16_UNORM = 40, 76 RB4_R16G16_SNORM = 41, 77 RB4_R16G16_FLOAT = 42, 78 RB4_R16G16_UINT = 43, 79 RB4_R16G16_SINT = 44, 80 RB4_R32_FLOAT = 45, 81 RB4_R32_UINT = 46, 82 RB4_R32_SINT = 47, 83 RB4_R16G16B16A16_UNORM = 52, 84 RB4_R16G16B16A16_SNORM = 53, 85 RB4_R16G16B16A16_FLOAT = 54, 86 RB4_R16G16B16A16_UINT = 55, 87 RB4_R16G16B16A16_SINT = 56, 88 RB4_R32G32_FLOAT = 57, 89 RB4_R32G32_UINT = 58, 90 RB4_R32G32_SINT = 59, 91 RB4_R32G32B32A32_FLOAT = 60, 92 RB4_R32G32B32A32_UINT = 61, 93 RB4_R32G32B32A32_SINT = 62, 94}; 95 96enum a4xx_tile_mode { 97 TILE4_LINEAR = 0, 98 TILE4_2 = 2, 99 TILE4_3 = 3, 100}; 101 102enum a4xx_vtx_fmt { 103 VFMT4_32_FLOAT = 1, 104 VFMT4_32_32_FLOAT = 2, 105 VFMT4_32_32_32_FLOAT = 3, 106 VFMT4_32_32_32_32_FLOAT = 4, 107 VFMT4_16_FLOAT = 5, 108 VFMT4_16_16_FLOAT = 6, 109 VFMT4_16_16_16_FLOAT = 7, 110 VFMT4_16_16_16_16_FLOAT = 8, 111 VFMT4_32_FIXED = 9, 112 VFMT4_32_32_FIXED = 10, 113 VFMT4_32_32_32_FIXED = 11, 114 VFMT4_32_32_32_32_FIXED = 12, 115 VFMT4_11_11_10_FLOAT = 13, 116 VFMT4_16_SINT = 16, 117 VFMT4_16_16_SINT = 17, 118 VFMT4_16_16_16_SINT = 18, 119 VFMT4_16_16_16_16_SINT = 19, 120 VFMT4_16_UINT = 20, 121 VFMT4_16_16_UINT = 21, 122 VFMT4_16_16_16_UINT = 22, 123 VFMT4_16_16_16_16_UINT = 23, 124 VFMT4_16_SNORM = 24, 125 VFMT4_16_16_SNORM = 25, 126 VFMT4_16_16_16_SNORM = 26, 127 VFMT4_16_16_16_16_SNORM = 27, 128 VFMT4_16_UNORM = 28, 129 VFMT4_16_16_UNORM = 29, 130 VFMT4_16_16_16_UNORM = 30, 131 VFMT4_16_16_16_16_UNORM = 31, 132 VFMT4_32_UINT = 32, 133 VFMT4_32_32_UINT = 33, 134 VFMT4_32_32_32_UINT = 34, 135 VFMT4_32_32_32_32_UINT = 35, 136 VFMT4_32_SINT = 36, 137 VFMT4_32_32_SINT = 37, 138 VFMT4_32_32_32_SINT = 38, 139 VFMT4_32_32_32_32_SINT = 39, 140 VFMT4_8_UINT = 40, 141 VFMT4_8_8_UINT = 41, 142 VFMT4_8_8_8_UINT = 42, 143 VFMT4_8_8_8_8_UINT = 43, 144 VFMT4_8_UNORM = 44, 145 VFMT4_8_8_UNORM = 45, 146 VFMT4_8_8_8_UNORM = 46, 147 VFMT4_8_8_8_8_UNORM = 47, 148 VFMT4_8_SINT = 48, 149 VFMT4_8_8_SINT = 49, 150 VFMT4_8_8_8_SINT = 50, 151 VFMT4_8_8_8_8_SINT = 51, 152 VFMT4_8_SNORM = 52, 153 VFMT4_8_8_SNORM = 53, 154 VFMT4_8_8_8_SNORM = 54, 155 VFMT4_8_8_8_8_SNORM = 55, 156 VFMT4_10_10_10_2_UINT = 56, 157 VFMT4_10_10_10_2_UNORM = 57, 158 VFMT4_10_10_10_2_SINT = 58, 159 VFMT4_10_10_10_2_SNORM = 59, 160 VFMT4_2_10_10_10_UINT = 60, 161 VFMT4_2_10_10_10_UNORM = 61, 162 VFMT4_2_10_10_10_SINT = 62, 163 VFMT4_2_10_10_10_SNORM = 63, 164}; 165 166enum a4xx_tex_fmt { 167 TFMT4_A8_UNORM = 3, 168 TFMT4_8_UNORM = 4, 169 TFMT4_8_SNORM = 5, 170 TFMT4_8_UINT = 6, 171 TFMT4_8_SINT = 7, 172 TFMT4_4_4_4_4_UNORM = 8, 173 TFMT4_5_5_5_1_UNORM = 9, 174 TFMT4_5_6_5_UNORM = 11, 175 TFMT4_L8_A8_UNORM = 13, 176 TFMT4_8_8_UNORM = 14, 177 TFMT4_8_8_SNORM = 15, 178 TFMT4_8_8_UINT = 16, 179 TFMT4_8_8_SINT = 17, 180 TFMT4_16_UNORM = 18, 181 TFMT4_16_SNORM = 19, 182 TFMT4_16_FLOAT = 20, 183 TFMT4_16_UINT = 21, 184 TFMT4_16_SINT = 22, 185 TFMT4_8_8_8_8_UNORM = 28, 186 TFMT4_8_8_8_8_SNORM = 29, 187 TFMT4_8_8_8_8_UINT = 30, 188 TFMT4_8_8_8_8_SINT = 31, 189 TFMT4_9_9_9_E5_FLOAT = 32, 190 TFMT4_10_10_10_2_UNORM = 33, 191 TFMT4_10_10_10_2_UINT = 34, 192 TFMT4_11_11_10_FLOAT = 37, 193 TFMT4_16_16_UNORM = 38, 194 TFMT4_16_16_SNORM = 39, 195 TFMT4_16_16_FLOAT = 40, 196 TFMT4_16_16_UINT = 41, 197 TFMT4_16_16_SINT = 42, 198 TFMT4_32_FLOAT = 43, 199 TFMT4_32_UINT = 44, 200 TFMT4_32_SINT = 45, 201 TFMT4_16_16_16_16_UNORM = 51, 202 TFMT4_16_16_16_16_SNORM = 52, 203 TFMT4_16_16_16_16_FLOAT = 53, 204 TFMT4_16_16_16_16_UINT = 54, 205 TFMT4_16_16_16_16_SINT = 55, 206 TFMT4_32_32_FLOAT = 56, 207 TFMT4_32_32_UINT = 57, 208 TFMT4_32_32_SINT = 58, 209 TFMT4_32_32_32_FLOAT = 59, 210 TFMT4_32_32_32_UINT = 60, 211 TFMT4_32_32_32_SINT = 61, 212 TFMT4_32_32_32_32_FLOAT = 63, 213 TFMT4_32_32_32_32_UINT = 64, 214 TFMT4_32_32_32_32_SINT = 65, 215 TFMT4_X8Z24_UNORM = 71, 216 TFMT4_DXT1 = 86, 217 TFMT4_DXT3 = 87, 218 TFMT4_DXT5 = 88, 219 TFMT4_RGTC1_UNORM = 90, 220 TFMT4_RGTC1_SNORM = 91, 221 TFMT4_RGTC2_UNORM = 94, 222 TFMT4_RGTC2_SNORM = 95, 223 TFMT4_BPTC_UFLOAT = 97, 224 TFMT4_BPTC_FLOAT = 98, 225 TFMT4_BPTC = 99, 226 TFMT4_ATC_RGB = 100, 227 TFMT4_ATC_RGBA_EXPLICIT = 101, 228 TFMT4_ATC_RGBA_INTERPOLATED = 102, 229 TFMT4_ETC2_RG11_UNORM = 103, 230 TFMT4_ETC2_RG11_SNORM = 104, 231 TFMT4_ETC2_R11_UNORM = 105, 232 TFMT4_ETC2_R11_SNORM = 106, 233 TFMT4_ETC1 = 107, 234 TFMT4_ETC2_RGB8 = 108, 235 TFMT4_ETC2_RGBA8 = 109, 236 TFMT4_ETC2_RGB8A1 = 110, 237 TFMT4_ASTC_4x4 = 111, 238 TFMT4_ASTC_5x4 = 112, 239 TFMT4_ASTC_5x5 = 113, 240 TFMT4_ASTC_6x5 = 114, 241 TFMT4_ASTC_6x6 = 115, 242 TFMT4_ASTC_8x5 = 116, 243 TFMT4_ASTC_8x6 = 117, 244 TFMT4_ASTC_8x8 = 118, 245 TFMT4_ASTC_10x5 = 119, 246 TFMT4_ASTC_10x6 = 120, 247 TFMT4_ASTC_10x8 = 121, 248 TFMT4_ASTC_10x10 = 122, 249 TFMT4_ASTC_12x10 = 123, 250 TFMT4_ASTC_12x12 = 124, 251}; 252 253enum a4xx_tex_fetchsize { 254 TFETCH4_1_BYTE = 0, 255 TFETCH4_2_BYTE = 1, 256 TFETCH4_4_BYTE = 2, 257 TFETCH4_8_BYTE = 3, 258 TFETCH4_16_BYTE = 4, 259}; 260 261enum a4xx_depth_format { 262 DEPTH4_NONE = 0, 263 DEPTH4_16 = 1, 264 DEPTH4_24_8 = 2, 265 DEPTH4_32 = 3, 266}; 267 268enum a4xx_ccu_perfcounter_select { 269 CCU_BUSY_CYCLES = 0, 270 CCU_RB_DEPTH_RETURN_STALL = 2, 271 CCU_RB_COLOR_RETURN_STALL = 3, 272 CCU_DEPTH_BLOCKS = 6, 273 CCU_COLOR_BLOCKS = 7, 274 CCU_DEPTH_BLOCK_HIT = 8, 275 CCU_COLOR_BLOCK_HIT = 9, 276 CCU_DEPTH_FLAG1_COUNT = 10, 277 CCU_DEPTH_FLAG2_COUNT = 11, 278 CCU_DEPTH_FLAG3_COUNT = 12, 279 CCU_DEPTH_FLAG4_COUNT = 13, 280 CCU_COLOR_FLAG1_COUNT = 14, 281 CCU_COLOR_FLAG2_COUNT = 15, 282 CCU_COLOR_FLAG3_COUNT = 16, 283 CCU_COLOR_FLAG4_COUNT = 17, 284 CCU_PARTIAL_BLOCK_READ = 18, 285}; 286 287enum a4xx_cp_perfcounter_select { 288 CP_ALWAYS_COUNT = 0, 289 CP_BUSY = 1, 290 CP_PFP_IDLE = 2, 291 CP_PFP_BUSY_WORKING = 3, 292 CP_PFP_STALL_CYCLES_ANY = 4, 293 CP_PFP_STARVE_CYCLES_ANY = 5, 294 CP_PFP_STARVED_PER_LOAD_ADDR = 6, 295 CP_PFP_STALLED_PER_STORE_ADDR = 7, 296 CP_PFP_PC_PROFILE = 8, 297 CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 298 CP_PFP_COND_INDIRECT_DISCARDED = 10, 299 CP_LONG_RESUMPTIONS = 11, 300 CP_RESUME_CYCLES = 12, 301 CP_RESUME_TO_BOUNDARY_CYCLES = 13, 302 CP_LONG_PREEMPTIONS = 14, 303 CP_PREEMPT_CYCLES = 15, 304 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, 305 CP_ME_FIFO_EMPTY_PFP_IDLE = 17, 306 CP_ME_FIFO_EMPTY_PFP_BUSY = 18, 307 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, 308 CP_ME_FIFO_FULL_ME_BUSY = 20, 309 CP_ME_FIFO_FULL_ME_NON_WORKING = 21, 310 CP_ME_WAITING_FOR_PACKETS = 22, 311 CP_ME_BUSY_WORKING = 23, 312 CP_ME_STARVE_CYCLES_ANY = 24, 313 CP_ME_STARVE_CYCLES_PER_PROFILE = 25, 314 CP_ME_STALL_CYCLES_PER_PROFILE = 26, 315 CP_ME_PC_PROFILE = 27, 316 CP_RCIU_FIFO_EMPTY = 28, 317 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, 318 CP_RCIU_FIFO_FULL = 30, 319 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, 320 CP_RCIU_FIFO_FULL_AHB_MASTER = 32, 321 CP_RCIU_FIFO_FULL_OTHER = 33, 322 CP_AHB_IDLE = 34, 323 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, 324 CP_AHB_STALL_ON_GRANT_SPLIT = 36, 325 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, 326 CP_AHB_BUSY_WORKING = 38, 327 CP_AHB_BUSY_STALL_ON_HRDY = 39, 328 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, 329}; 330 331enum a4xx_gras_ras_perfcounter_select { 332 RAS_SUPER_TILES = 0, 333 RAS_8X8_TILES = 1, 334 RAS_4X4_TILES = 2, 335 RAS_BUSY_CYCLES = 3, 336 RAS_STALL_CYCLES_BY_RB = 4, 337 RAS_STALL_CYCLES_BY_VSC = 5, 338 RAS_STARVE_CYCLES_BY_TSE = 6, 339 RAS_SUPERTILE_CYCLES = 7, 340 RAS_TILE_CYCLES = 8, 341 RAS_FULLY_COVERED_SUPER_TILES = 9, 342 RAS_FULLY_COVERED_8X8_TILES = 10, 343 RAS_4X4_PRIM = 11, 344 RAS_8X4_4X8_PRIM = 12, 345 RAS_8X8_PRIM = 13, 346}; 347 348enum a4xx_gras_tse_perfcounter_select { 349 TSE_INPUT_PRIM = 0, 350 TSE_INPUT_NULL_PRIM = 1, 351 TSE_TRIVAL_REJ_PRIM = 2, 352 TSE_CLIPPED_PRIM = 3, 353 TSE_NEW_PRIM = 4, 354 TSE_ZERO_AREA_PRIM = 5, 355 TSE_FACENESS_CULLED_PRIM = 6, 356 TSE_ZERO_PIXEL_PRIM = 7, 357 TSE_OUTPUT_NULL_PRIM = 8, 358 TSE_OUTPUT_VISIBLE_PRIM = 9, 359 TSE_PRE_CLIP_PRIM = 10, 360 TSE_POST_CLIP_PRIM = 11, 361 TSE_BUSY_CYCLES = 12, 362 TSE_PC_STARVE = 13, 363 TSE_RAS_STALL = 14, 364 TSE_STALL_BARYPLANE_FIFO_FULL = 15, 365 TSE_STALL_ZPLANE_FIFO_FULL = 16, 366}; 367 368enum a4xx_hlsq_perfcounter_select { 369 HLSQ_SP_VS_STAGE_CONSTANT = 0, 370 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, 371 HLSQ_SP_FS_STAGE_CONSTANT = 2, 372 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, 373 HLSQ_TP_STATE = 4, 374 HLSQ_QUADS = 5, 375 HLSQ_PIXELS = 6, 376 HLSQ_VERTICES = 7, 377 HLSQ_SP_VS_STAGE_DATA_BYTES = 13, 378 HLSQ_SP_FS_STAGE_DATA_BYTES = 14, 379 HLSQ_BUSY_CYCLES = 15, 380 HLSQ_STALL_CYCLES_SP_STATE = 16, 381 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, 382 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, 383 HLSQ_STALL_CYCLES_UCHE = 19, 384 HLSQ_RBBM_LOAD_CYCLES = 20, 385 HLSQ_DI_TO_VS_START_SP = 21, 386 HLSQ_DI_TO_FS_START_SP = 22, 387 HLSQ_VS_STAGE_START_TO_DONE_SP = 23, 388 HLSQ_FS_STAGE_START_TO_DONE_SP = 24, 389 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, 390 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, 391 HLSQ_UCHE_LATENCY_CYCLES = 27, 392 HLSQ_UCHE_LATENCY_COUNT = 28, 393 HLSQ_STARVE_CYCLES_VFD = 29, 394}; 395 396enum a4xx_pc_perfcounter_select { 397 PC_VIS_STREAMS_LOADED = 0, 398 PC_VPC_PRIMITIVES = 2, 399 PC_DEAD_PRIM = 3, 400 PC_LIVE_PRIM = 4, 401 PC_DEAD_DRAWCALLS = 5, 402 PC_LIVE_DRAWCALLS = 6, 403 PC_VERTEX_MISSES = 7, 404 PC_STALL_CYCLES_VFD = 9, 405 PC_STALL_CYCLES_TSE = 10, 406 PC_STALL_CYCLES_UCHE = 11, 407 PC_WORKING_CYCLES = 12, 408 PC_IA_VERTICES = 13, 409 PC_GS_PRIMITIVES = 14, 410 PC_HS_INVOCATIONS = 15, 411 PC_DS_INVOCATIONS = 16, 412 PC_DS_PRIMITIVES = 17, 413 PC_STARVE_CYCLES_FOR_INDEX = 20, 414 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, 415 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, 416 PC_STALL_CYCLES_TESS = 23, 417 PC_STARVE_CYCLES_FOR_POSITION = 24, 418 PC_MODE0_DRAWCALL = 25, 419 PC_MODE1_DRAWCALL = 26, 420 PC_MODE2_DRAWCALL = 27, 421 PC_MODE3_DRAWCALL = 28, 422 PC_MODE4_DRAWCALL = 29, 423 PC_PREDICATED_DEAD_DRAWCALL = 30, 424 PC_STALL_CYCLES_BY_TSE_ONLY = 31, 425 PC_STALL_CYCLES_BY_VPC_ONLY = 32, 426 PC_VPC_POS_DATA_TRANSACTION = 33, 427 PC_BUSY_CYCLES = 34, 428 PC_STARVE_CYCLES_DI = 35, 429 PC_STALL_CYCLES_VPC = 36, 430 TESS_WORKING_CYCLES = 37, 431 TESS_NUM_CYCLES_SETUP_WORKING = 38, 432 TESS_NUM_CYCLES_PTGEN_WORKING = 39, 433 TESS_NUM_CYCLES_CONNGEN_WORKING = 40, 434 TESS_BUSY_CYCLES = 41, 435 TESS_STARVE_CYCLES_PC = 42, 436 TESS_STALL_CYCLES_PC = 43, 437}; 438 439enum a4xx_pwr_perfcounter_select { 440 PWR_CORE_CLOCK_CYCLES = 0, 441 PWR_BUSY_CLOCK_CYCLES = 1, 442}; 443 444enum a4xx_rb_perfcounter_select { 445 RB_BUSY_CYCLES = 0, 446 RB_BUSY_CYCLES_BINNING = 1, 447 RB_BUSY_CYCLES_RENDERING = 2, 448 RB_BUSY_CYCLES_RESOLVE = 3, 449 RB_STARVE_CYCLES_BY_SP = 4, 450 RB_STARVE_CYCLES_BY_RAS = 5, 451 RB_STARVE_CYCLES_BY_MARB = 6, 452 RB_STALL_CYCLES_BY_MARB = 7, 453 RB_STALL_CYCLES_BY_HLSQ = 8, 454 RB_RB_RB_MARB_DATA = 9, 455 RB_SP_RB_QUAD = 10, 456 RB_RAS_RB_Z_QUADS = 11, 457 RB_GMEM_CH0_READ = 12, 458 RB_GMEM_CH1_READ = 13, 459 RB_GMEM_CH0_WRITE = 14, 460 RB_GMEM_CH1_WRITE = 15, 461 RB_CP_CONTEXT_DONE = 16, 462 RB_CP_CACHE_FLUSH = 17, 463 RB_CP_ZPASS_DONE = 18, 464 RB_STALL_FIFO0_FULL = 19, 465 RB_STALL_FIFO1_FULL = 20, 466 RB_STALL_FIFO2_FULL = 21, 467 RB_STALL_FIFO3_FULL = 22, 468 RB_RB_HLSQ_TRANSACTIONS = 23, 469 RB_Z_READ = 24, 470 RB_Z_WRITE = 25, 471 RB_C_READ = 26, 472 RB_C_WRITE = 27, 473 RB_C_READ_LATENCY = 28, 474 RB_Z_READ_LATENCY = 29, 475 RB_STALL_BY_UCHE = 30, 476 RB_MARB_UCHE_TRANSACTIONS = 31, 477 RB_CACHE_STALL_MISS = 32, 478 RB_CACHE_STALL_FIFO_FULL = 33, 479 RB_8BIT_BLENDER_UNITS_ACTIVE = 34, 480 RB_16BIT_BLENDER_UNITS_ACTIVE = 35, 481 RB_SAMPLER_UNITS_ACTIVE = 36, 482 RB_TOTAL_PASS = 38, 483 RB_Z_PASS = 39, 484 RB_Z_FAIL = 40, 485 RB_S_FAIL = 41, 486 RB_POWER0 = 42, 487 RB_POWER1 = 43, 488 RB_POWER2 = 44, 489 RB_POWER3 = 45, 490 RB_POWER4 = 46, 491 RB_POWER5 = 47, 492 RB_POWER6 = 48, 493 RB_POWER7 = 49, 494}; 495 496enum a4xx_rbbm_perfcounter_select { 497 RBBM_ALWAYS_ON = 0, 498 RBBM_VBIF_BUSY = 1, 499 RBBM_TSE_BUSY = 2, 500 RBBM_RAS_BUSY = 3, 501 RBBM_PC_DCALL_BUSY = 4, 502 RBBM_PC_VSD_BUSY = 5, 503 RBBM_VFD_BUSY = 6, 504 RBBM_VPC_BUSY = 7, 505 RBBM_UCHE_BUSY = 8, 506 RBBM_VSC_BUSY = 9, 507 RBBM_HLSQ_BUSY = 10, 508 RBBM_ANY_RB_BUSY = 11, 509 RBBM_ANY_TPL1_BUSY = 12, 510 RBBM_ANY_SP_BUSY = 13, 511 RBBM_ANY_MARB_BUSY = 14, 512 RBBM_ANY_ARB_BUSY = 15, 513 RBBM_AHB_STATUS_BUSY = 16, 514 RBBM_AHB_STATUS_STALLED = 17, 515 RBBM_AHB_STATUS_TXFR = 18, 516 RBBM_AHB_STATUS_TXFR_SPLIT = 19, 517 RBBM_AHB_STATUS_TXFR_ERROR = 20, 518 RBBM_AHB_STATUS_LONG_STALL = 21, 519 RBBM_STATUS_MASKED = 22, 520 RBBM_CP_BUSY_GFX_CORE_IDLE = 23, 521 RBBM_TESS_BUSY = 24, 522 RBBM_COM_BUSY = 25, 523 RBBM_DCOM_BUSY = 32, 524 RBBM_ANY_CCU_BUSY = 33, 525 RBBM_DPM_BUSY = 34, 526}; 527 528enum a4xx_sp_perfcounter_select { 529 SP_LM_LOAD_INSTRUCTIONS = 0, 530 SP_LM_STORE_INSTRUCTIONS = 1, 531 SP_LM_ATOMICS = 2, 532 SP_GM_LOAD_INSTRUCTIONS = 3, 533 SP_GM_STORE_INSTRUCTIONS = 4, 534 SP_GM_ATOMICS = 5, 535 SP_VS_STAGE_TEX_INSTRUCTIONS = 6, 536 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, 537 SP_VS_STAGE_EFU_INSTRUCTIONS = 8, 538 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, 539 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, 540 SP_FS_STAGE_TEX_INSTRUCTIONS = 11, 541 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, 542 SP_FS_STAGE_EFU_INSTRUCTIONS = 13, 543 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, 544 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, 545 SP_VS_INSTRUCTIONS = 17, 546 SP_FS_INSTRUCTIONS = 18, 547 SP_ADDR_LOCK_COUNT = 19, 548 SP_UCHE_READ_TRANS = 20, 549 SP_UCHE_WRITE_TRANS = 21, 550 SP_EXPORT_VPC_TRANS = 22, 551 SP_EXPORT_RB_TRANS = 23, 552 SP_PIXELS_KILLED = 24, 553 SP_ICL1_REQUESTS = 25, 554 SP_ICL1_MISSES = 26, 555 SP_ICL0_REQUESTS = 27, 556 SP_ICL0_MISSES = 28, 557 SP_ALU_WORKING_CYCLES = 29, 558 SP_EFU_WORKING_CYCLES = 30, 559 SP_STALL_CYCLES_BY_VPC = 31, 560 SP_STALL_CYCLES_BY_TP = 32, 561 SP_STALL_CYCLES_BY_UCHE = 33, 562 SP_STALL_CYCLES_BY_RB = 34, 563 SP_BUSY_CYCLES = 35, 564 SP_HS_INSTRUCTIONS = 36, 565 SP_DS_INSTRUCTIONS = 37, 566 SP_GS_INSTRUCTIONS = 38, 567 SP_CS_INSTRUCTIONS = 39, 568 SP_SCHEDULER_NON_WORKING = 40, 569 SP_WAVE_CONTEXTS = 41, 570 SP_WAVE_CONTEXT_CYCLES = 42, 571 SP_POWER0 = 43, 572 SP_POWER1 = 44, 573 SP_POWER2 = 45, 574 SP_POWER3 = 46, 575 SP_POWER4 = 47, 576 SP_POWER5 = 48, 577 SP_POWER6 = 49, 578 SP_POWER7 = 50, 579 SP_POWER8 = 51, 580 SP_POWER9 = 52, 581 SP_POWER10 = 53, 582 SP_POWER11 = 54, 583 SP_POWER12 = 55, 584 SP_POWER13 = 56, 585 SP_POWER14 = 57, 586 SP_POWER15 = 58, 587}; 588 589enum a4xx_tp_perfcounter_select { 590 TP_L1_REQUESTS = 0, 591 TP_L1_MISSES = 1, 592 TP_QUADS_OFFSET = 8, 593 TP_QUAD_SHADOW = 9, 594 TP_QUADS_ARRAY = 10, 595 TP_QUADS_GRADIENT = 11, 596 TP_QUADS_1D2D = 12, 597 TP_QUADS_3DCUBE = 13, 598 TP_BUSY_CYCLES = 16, 599 TP_STALL_CYCLES_BY_ARB = 17, 600 TP_STATE_CACHE_REQUESTS = 20, 601 TP_STATE_CACHE_MISSES = 21, 602 TP_POWER0 = 22, 603 TP_POWER1 = 23, 604 TP_POWER2 = 24, 605 TP_POWER3 = 25, 606 TP_POWER4 = 26, 607 TP_POWER5 = 27, 608 TP_POWER6 = 28, 609 TP_POWER7 = 29, 610}; 611 612enum a4xx_uche_perfcounter_select { 613 UCHE_VBIF_READ_BEATS_TP = 0, 614 UCHE_VBIF_READ_BEATS_VFD = 1, 615 UCHE_VBIF_READ_BEATS_HLSQ = 2, 616 UCHE_VBIF_READ_BEATS_MARB = 3, 617 UCHE_VBIF_READ_BEATS_SP = 4, 618 UCHE_READ_REQUESTS_TP = 5, 619 UCHE_READ_REQUESTS_VFD = 6, 620 UCHE_READ_REQUESTS_HLSQ = 7, 621 UCHE_READ_REQUESTS_MARB = 8, 622 UCHE_READ_REQUESTS_SP = 9, 623 UCHE_WRITE_REQUESTS_MARB = 10, 624 UCHE_WRITE_REQUESTS_SP = 11, 625 UCHE_TAG_CHECK_FAILS = 12, 626 UCHE_EVICTS = 13, 627 UCHE_FLUSHES = 14, 628 UCHE_VBIF_LATENCY_CYCLES = 15, 629 UCHE_VBIF_LATENCY_SAMPLES = 16, 630 UCHE_BUSY_CYCLES = 17, 631 UCHE_VBIF_READ_BEATS_PC = 18, 632 UCHE_READ_REQUESTS_PC = 19, 633 UCHE_WRITE_REQUESTS_VPC = 20, 634 UCHE_STALL_BY_VBIF = 21, 635 UCHE_WRITE_REQUESTS_VSC = 22, 636 UCHE_POWER0 = 23, 637 UCHE_POWER1 = 24, 638 UCHE_POWER2 = 25, 639 UCHE_POWER3 = 26, 640 UCHE_POWER4 = 27, 641 UCHE_POWER5 = 28, 642 UCHE_POWER6 = 29, 643 UCHE_POWER7 = 30, 644}; 645 646enum a4xx_vbif_perfcounter_select { 647 AXI_READ_REQUESTS_ID_0 = 0, 648 AXI_READ_REQUESTS_ID_1 = 1, 649 AXI_READ_REQUESTS_ID_2 = 2, 650 AXI_READ_REQUESTS_ID_3 = 3, 651 AXI_READ_REQUESTS_ID_4 = 4, 652 AXI_READ_REQUESTS_ID_5 = 5, 653 AXI_READ_REQUESTS_ID_6 = 6, 654 AXI_READ_REQUESTS_ID_7 = 7, 655 AXI_READ_REQUESTS_ID_8 = 8, 656 AXI_READ_REQUESTS_ID_9 = 9, 657 AXI_READ_REQUESTS_ID_10 = 10, 658 AXI_READ_REQUESTS_ID_11 = 11, 659 AXI_READ_REQUESTS_ID_12 = 12, 660 AXI_READ_REQUESTS_ID_13 = 13, 661 AXI_READ_REQUESTS_ID_14 = 14, 662 AXI_READ_REQUESTS_ID_15 = 15, 663 AXI0_READ_REQUESTS_TOTAL = 16, 664 AXI1_READ_REQUESTS_TOTAL = 17, 665 AXI2_READ_REQUESTS_TOTAL = 18, 666 AXI3_READ_REQUESTS_TOTAL = 19, 667 AXI_READ_REQUESTS_TOTAL = 20, 668 AXI_WRITE_REQUESTS_ID_0 = 21, 669 AXI_WRITE_REQUESTS_ID_1 = 22, 670 AXI_WRITE_REQUESTS_ID_2 = 23, 671 AXI_WRITE_REQUESTS_ID_3 = 24, 672 AXI_WRITE_REQUESTS_ID_4 = 25, 673 AXI_WRITE_REQUESTS_ID_5 = 26, 674 AXI_WRITE_REQUESTS_ID_6 = 27, 675 AXI_WRITE_REQUESTS_ID_7 = 28, 676 AXI_WRITE_REQUESTS_ID_8 = 29, 677 AXI_WRITE_REQUESTS_ID_9 = 30, 678 AXI_WRITE_REQUESTS_ID_10 = 31, 679 AXI_WRITE_REQUESTS_ID_11 = 32, 680 AXI_WRITE_REQUESTS_ID_12 = 33, 681 AXI_WRITE_REQUESTS_ID_13 = 34, 682 AXI_WRITE_REQUESTS_ID_14 = 35, 683 AXI_WRITE_REQUESTS_ID_15 = 36, 684 AXI0_WRITE_REQUESTS_TOTAL = 37, 685 AXI1_WRITE_REQUESTS_TOTAL = 38, 686 AXI2_WRITE_REQUESTS_TOTAL = 39, 687 AXI3_WRITE_REQUESTS_TOTAL = 40, 688 AXI_WRITE_REQUESTS_TOTAL = 41, 689 AXI_TOTAL_REQUESTS = 42, 690 AXI_READ_DATA_BEATS_ID_0 = 43, 691 AXI_READ_DATA_BEATS_ID_1 = 44, 692 AXI_READ_DATA_BEATS_ID_2 = 45, 693 AXI_READ_DATA_BEATS_ID_3 = 46, 694 AXI_READ_DATA_BEATS_ID_4 = 47, 695 AXI_READ_DATA_BEATS_ID_5 = 48, 696 AXI_READ_DATA_BEATS_ID_6 = 49, 697 AXI_READ_DATA_BEATS_ID_7 = 50, 698 AXI_READ_DATA_BEATS_ID_8 = 51, 699 AXI_READ_DATA_BEATS_ID_9 = 52, 700 AXI_READ_DATA_BEATS_ID_10 = 53, 701 AXI_READ_DATA_BEATS_ID_11 = 54, 702 AXI_READ_DATA_BEATS_ID_12 = 55, 703 AXI_READ_DATA_BEATS_ID_13 = 56, 704 AXI_READ_DATA_BEATS_ID_14 = 57, 705 AXI_READ_DATA_BEATS_ID_15 = 58, 706 AXI0_READ_DATA_BEATS_TOTAL = 59, 707 AXI1_READ_DATA_BEATS_TOTAL = 60, 708 AXI2_READ_DATA_BEATS_TOTAL = 61, 709 AXI3_READ_DATA_BEATS_TOTAL = 62, 710 AXI_READ_DATA_BEATS_TOTAL = 63, 711 AXI_WRITE_DATA_BEATS_ID_0 = 64, 712 AXI_WRITE_DATA_BEATS_ID_1 = 65, 713 AXI_WRITE_DATA_BEATS_ID_2 = 66, 714 AXI_WRITE_DATA_BEATS_ID_3 = 67, 715 AXI_WRITE_DATA_BEATS_ID_4 = 68, 716 AXI_WRITE_DATA_BEATS_ID_5 = 69, 717 AXI_WRITE_DATA_BEATS_ID_6 = 70, 718 AXI_WRITE_DATA_BEATS_ID_7 = 71, 719 AXI_WRITE_DATA_BEATS_ID_8 = 72, 720 AXI_WRITE_DATA_BEATS_ID_9 = 73, 721 AXI_WRITE_DATA_BEATS_ID_10 = 74, 722 AXI_WRITE_DATA_BEATS_ID_11 = 75, 723 AXI_WRITE_DATA_BEATS_ID_12 = 76, 724 AXI_WRITE_DATA_BEATS_ID_13 = 77, 725 AXI_WRITE_DATA_BEATS_ID_14 = 78, 726 AXI_WRITE_DATA_BEATS_ID_15 = 79, 727 AXI0_WRITE_DATA_BEATS_TOTAL = 80, 728 AXI1_WRITE_DATA_BEATS_TOTAL = 81, 729 AXI2_WRITE_DATA_BEATS_TOTAL = 82, 730 AXI3_WRITE_DATA_BEATS_TOTAL = 83, 731 AXI_WRITE_DATA_BEATS_TOTAL = 84, 732 AXI_DATA_BEATS_TOTAL = 85, 733 CYCLES_HELD_OFF_ID_0 = 86, 734 CYCLES_HELD_OFF_ID_1 = 87, 735 CYCLES_HELD_OFF_ID_2 = 88, 736 CYCLES_HELD_OFF_ID_3 = 89, 737 CYCLES_HELD_OFF_ID_4 = 90, 738 CYCLES_HELD_OFF_ID_5 = 91, 739 CYCLES_HELD_OFF_ID_6 = 92, 740 CYCLES_HELD_OFF_ID_7 = 93, 741 CYCLES_HELD_OFF_ID_8 = 94, 742 CYCLES_HELD_OFF_ID_9 = 95, 743 CYCLES_HELD_OFF_ID_10 = 96, 744 CYCLES_HELD_OFF_ID_11 = 97, 745 CYCLES_HELD_OFF_ID_12 = 98, 746 CYCLES_HELD_OFF_ID_13 = 99, 747 CYCLES_HELD_OFF_ID_14 = 100, 748 CYCLES_HELD_OFF_ID_15 = 101, 749 AXI_READ_REQUEST_HELD_OFF = 102, 750 AXI_WRITE_REQUEST_HELD_OFF = 103, 751 AXI_REQUEST_HELD_OFF = 104, 752 AXI_WRITE_DATA_HELD_OFF = 105, 753 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, 754 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, 755 OCMEM_AXI_REQUEST_HELD_OFF = 108, 756 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, 757 ELAPSED_CYCLES_DDR = 110, 758 ELAPSED_CYCLES_OCMEM = 111, 759}; 760 761enum a4xx_vfd_perfcounter_select { 762 VFD_UCHE_BYTE_FETCHED = 0, 763 VFD_UCHE_TRANS = 1, 764 VFD_FETCH_INSTRUCTIONS = 3, 765 VFD_BUSY_CYCLES = 5, 766 VFD_STALL_CYCLES_UCHE = 6, 767 VFD_STALL_CYCLES_HLSQ = 7, 768 VFD_STALL_CYCLES_VPC_BYPASS = 8, 769 VFD_STALL_CYCLES_VPC_ALLOC = 9, 770 VFD_MODE_0_FIBERS = 13, 771 VFD_MODE_1_FIBERS = 14, 772 VFD_MODE_2_FIBERS = 15, 773 VFD_MODE_3_FIBERS = 16, 774 VFD_MODE_4_FIBERS = 17, 775 VFD_BFIFO_STALL = 18, 776 VFD_NUM_VERTICES_TOTAL = 19, 777 VFD_PACKER_FULL = 20, 778 VFD_UCHE_REQUEST_FIFO_FULL = 21, 779 VFD_STARVE_CYCLES_PC = 22, 780 VFD_STARVE_CYCLES_UCHE = 23, 781}; 782 783enum a4xx_vpc_perfcounter_select { 784 VPC_SP_LM_COMPONENTS = 2, 785 VPC_SP0_LM_BYTES = 3, 786 VPC_SP1_LM_BYTES = 4, 787 VPC_SP2_LM_BYTES = 5, 788 VPC_SP3_LM_BYTES = 6, 789 VPC_WORKING_CYCLES = 7, 790 VPC_STALL_CYCLES_LM = 8, 791 VPC_STARVE_CYCLES_RAS = 9, 792 VPC_STREAMOUT_CYCLES = 10, 793 VPC_UCHE_TRANSACTIONS = 12, 794 VPC_STALL_CYCLES_UCHE = 13, 795 VPC_BUSY_CYCLES = 14, 796 VPC_STARVE_CYCLES_SP = 15, 797}; 798 799enum a4xx_vsc_perfcounter_select { 800 VSC_BUSY_CYCLES = 0, 801 VSC_WORKING_CYCLES = 1, 802 VSC_STALL_CYCLES_UCHE = 2, 803 VSC_STARVE_CYCLES_RAS = 3, 804 VSC_EOT_NUM = 4, 805}; 806 807enum a4xx_tex_filter { 808 A4XX_TEX_NEAREST = 0, 809 A4XX_TEX_LINEAR = 1, 810 A4XX_TEX_ANISO = 2, 811}; 812 813enum a4xx_tex_clamp { 814 A4XX_TEX_REPEAT = 0, 815 A4XX_TEX_CLAMP_TO_EDGE = 1, 816 A4XX_TEX_MIRROR_REPEAT = 2, 817 A4XX_TEX_CLAMP_TO_BORDER = 3, 818 A4XX_TEX_MIRROR_CLAMP = 4, 819}; 820 821enum a4xx_tex_aniso { 822 A4XX_TEX_ANISO_1 = 0, 823 A4XX_TEX_ANISO_2 = 1, 824 A4XX_TEX_ANISO_4 = 2, 825 A4XX_TEX_ANISO_8 = 3, 826 A4XX_TEX_ANISO_16 = 4, 827}; 828 829enum a4xx_tex_swiz { 830 A4XX_TEX_X = 0, 831 A4XX_TEX_Y = 1, 832 A4XX_TEX_Z = 2, 833 A4XX_TEX_W = 3, 834 A4XX_TEX_ZERO = 4, 835 A4XX_TEX_ONE = 5, 836}; 837 838enum a4xx_tex_type { 839 A4XX_TEX_1D = 0, 840 A4XX_TEX_2D = 1, 841 A4XX_TEX_CUBE = 2, 842 A4XX_TEX_3D = 3, 843}; 844 845#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 846#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 847static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 848{ 849 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 850} 851#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 852#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 853#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 854#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 855#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 856#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 857#define A4XX_INT0_VFD_ERROR 0x00000040 858#define A4XX_INT0_CP_SW_INT 0x00000080 859#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 860#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 861#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 862#define A4XX_INT0_CP_HW_FAULT 0x00000800 863#define A4XX_INT0_CP_DMA 0x00001000 864#define A4XX_INT0_CP_IB2_INT 0x00002000 865#define A4XX_INT0_CP_IB1_INT 0x00004000 866#define A4XX_INT0_CP_RB_INT 0x00008000 867#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 868#define A4XX_INT0_CP_RB_DONE_TS 0x00020000 869#define A4XX_INT0_CP_VS_DONE_TS 0x00040000 870#define A4XX_INT0_CP_PS_DONE_TS 0x00080000 871#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 872#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 873#define A4XX_INT0_MISC_HANG_DETECT 0x01000000 874#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 875#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 876 877#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 878 879#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 880 881#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 882 883#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 884 885#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 886 887#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 888 889#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 890 891#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 892 893#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf 894 895#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 896 897#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 898 899#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 900 901#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 902#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 903#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 904static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 905{ 906 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 907} 908#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 909#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 910static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 911{ 912 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 913} 914 915#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 916 917#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 918 919#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 920 921#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 922 923#define REG_A4XX_RB_MODE_CONTROL 0x000020a0 924#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 925#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 926static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 927{ 928 assert(!(val & 0x1f)); 929 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 930} 931#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 932#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 933static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 934{ 935 assert(!(val & 0x1f)); 936 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 937} 938#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 939 940#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 941#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 942#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 943 944#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 945#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 946#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 947#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 948static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 949{ 950 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 951} 952 953#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 954#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 955#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 956#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 957#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 958#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 959#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 960#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 961#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 962#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 963static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 964{ 965 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 966} 967#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 968#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 969 970static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 971 972static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 973#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 974#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 975#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 976#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 977#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 978#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 979static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 980{ 981 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; 982} 983#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 984#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 985static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 986{ 987 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 988} 989 990static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 991#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 992#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 993static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 994{ 995 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 996} 997#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 998#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 999static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 1000{ 1001 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1002} 1003#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 1004#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 1005static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1006{ 1007 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 1008} 1009#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 1010#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 1011static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1012{ 1013 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1014} 1015#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 1016#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 1017#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 1018static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1019{ 1020 assert(!(val & 0xf)); 1021 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1022} 1023 1024static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 1025 1026static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 1027#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 1028#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 1029static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 1030{ 1031 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 1032} 1033 1034static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 1035#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1036#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1037static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1038{ 1039 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1040} 1041#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1042#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1043static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1044{ 1045 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1046} 1047#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1048#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1049static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1050{ 1051 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1052} 1053#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1054#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1055static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1056{ 1057 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1058} 1059#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1060#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1061static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1062{ 1063 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1064} 1065#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1066#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1067static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1068{ 1069 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1070} 1071 1072#define REG_A4XX_RB_BLEND_RED 0x000020f0 1073#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1074#define A4XX_RB_BLEND_RED_UINT__SHIFT 0 1075static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 1076{ 1077 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 1078} 1079#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 1080#define A4XX_RB_BLEND_RED_SINT__SHIFT 8 1081static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) 1082{ 1083 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; 1084} 1085#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1086#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 1087static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 1088{ 1089 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 1090} 1091 1092#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 1093#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff 1094#define A4XX_RB_BLEND_RED_F32__SHIFT 0 1095static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 1096{ 1097 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; 1098} 1099 1100#define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1101#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1102#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 1103static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 1104{ 1105 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 1106} 1107#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 1108#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 1109static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) 1110{ 1111 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; 1112} 1113#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1114#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1115static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 1116{ 1117 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 1118} 1119 1120#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 1121#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 1122#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 1123static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 1124{ 1125 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; 1126} 1127 1128#define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1129#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1130#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 1131static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 1132{ 1133 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 1134} 1135#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 1136#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 1137static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) 1138{ 1139 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; 1140} 1141#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1142#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1143static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 1144{ 1145 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 1146} 1147 1148#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 1149#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 1150#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 1151static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 1152{ 1153 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; 1154} 1155 1156#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1157#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1158#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1159static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1160{ 1161 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 1162} 1163#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 1164#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 1165static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) 1166{ 1167 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; 1168} 1169#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1170#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1171static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 1172{ 1173 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 1174} 1175 1176#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 1177#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 1178#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 1179static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) 1180{ 1181 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; 1182} 1183 1184#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 1185#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 1186#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 1187static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 1188{ 1189 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 1190} 1191#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 1192#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 1193#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 1194static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1195{ 1196 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 1197} 1198 1199#define REG_A4XX_RB_FS_OUTPUT 0x000020f9 1200#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 1201#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 1202static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 1203{ 1204 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 1205} 1206#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 1207#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 1208#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 1209static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 1210{ 1211 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 1212} 1213 1214#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 1215#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1216#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 1217#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 1218static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 1219{ 1220 assert(!(val & 0x3)); 1221 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 1222} 1223 1224#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 1225#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 1226#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 1227static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 1228{ 1229 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 1230} 1231#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 1232#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 1233static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 1234{ 1235 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 1236} 1237#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 1238#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 1239static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 1240{ 1241 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 1242} 1243#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 1244#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 1245static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 1246{ 1247 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 1248} 1249#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 1250#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 1251static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 1252{ 1253 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 1254} 1255#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 1256#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 1257static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 1258{ 1259 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 1260} 1261#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 1262#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 1263static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 1264{ 1265 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 1266} 1267#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 1268#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 1269static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 1270{ 1271 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 1272} 1273 1274#define REG_A4XX_RB_COPY_CONTROL 0x000020fc 1275#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1276#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1277static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1278{ 1279 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1280} 1281#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1282#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 1283static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1284{ 1285 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 1286} 1287#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1288#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1289static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1290{ 1291 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1292} 1293#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1294#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1295static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1296{ 1297 assert(!(val & 0x3fff)); 1298 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1299} 1300 1301#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 1302#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 1303#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 1304static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1305{ 1306 assert(!(val & 0x1f)); 1307 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 1308} 1309 1310#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 1311#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1312#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1313static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1314{ 1315 assert(!(val & 0x1f)); 1316 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1317} 1318 1319#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 1320#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1321#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1322static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 1323{ 1324 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1325} 1326#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1327#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1328static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1329{ 1330 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 1331} 1332#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1333#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1334static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1335{ 1336 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1337} 1338#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1339#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1340static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1341{ 1342 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1343} 1344#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1345#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1346static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1347{ 1348 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1349} 1350#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 1351#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 1352static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 1353{ 1354 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 1355} 1356 1357#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 1358#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1359#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 1360static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 1361{ 1362 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 1363} 1364#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 1365 1366#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 1367#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1368#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1369#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1370#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1371#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1372static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1373{ 1374 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1375} 1376#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1377#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1378#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1379#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1380 1381#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 1382 1383#define REG_A4XX_RB_DEPTH_INFO 0x00002103 1384#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1385#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1386static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 1387{ 1388 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1389} 1390#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1391#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1392static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1393{ 1394 assert(!(val & 0xfff)); 1395 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1396} 1397 1398#define REG_A4XX_RB_DEPTH_PITCH 0x00002104 1399#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 1400#define A4XX_RB_DEPTH_PITCH__SHIFT 0 1401static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 1402{ 1403 assert(!(val & 0x1f)); 1404 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 1405} 1406 1407#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 1408#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 1409#define A4XX_RB_DEPTH_PITCH2__SHIFT 0 1410static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 1411{ 1412 assert(!(val & 0x1f)); 1413 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 1414} 1415 1416#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 1417#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1418#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1419#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1420#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1421#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1422static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1423{ 1424 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 1425} 1426#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1427#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1428static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1429{ 1430 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 1431} 1432#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1433#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1434static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1435{ 1436 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1437} 1438#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1439#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1440static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1441{ 1442 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1443} 1444#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1445#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1446static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1447{ 1448 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1449} 1450#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1451#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1452static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1453{ 1454 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1455} 1456#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1457#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1458static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1459{ 1460 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1461} 1462#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1463#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1464static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1465{ 1466 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1467} 1468 1469#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 1470#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 1471 1472#define REG_A4XX_RB_STENCIL_INFO 0x00002108 1473#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 1474#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 1475#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 1476static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1477{ 1478 assert(!(val & 0xfff)); 1479 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1480} 1481 1482#define REG_A4XX_RB_STENCIL_PITCH 0x00002109 1483#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 1484#define A4XX_RB_STENCIL_PITCH__SHIFT 0 1485static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 1486{ 1487 assert(!(val & 0x1f)); 1488 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 1489} 1490 1491#define REG_A4XX_RB_STENCILREFMASK 0x0000210b 1492#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1493#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1494static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1495{ 1496 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 1497} 1498#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1499#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1500static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1501{ 1502 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1503} 1504#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1505#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1506static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1507{ 1508 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1509} 1510 1511#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 1512#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1513#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1514static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1515{ 1516 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1517} 1518#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1519#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1520static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1521{ 1522 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1523} 1524#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1525#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1526static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1527{ 1528 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1529} 1530 1531#define REG_A4XX_RB_BIN_OFFSET 0x0000210d 1532#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 1533#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 1534#define A4XX_RB_BIN_OFFSET_X__SHIFT 0 1535static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 1536{ 1537 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 1538} 1539#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 1540#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 1541static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 1542{ 1543 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 1544} 1545 1546static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 1547 1548static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 1549 1550static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 1551 1552#define REG_A4XX_RBBM_HW_VERSION 0x00000000 1553 1554#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 1555 1556static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1557 1558static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1559 1560static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1561 1562static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1563 1564static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1565 1566static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1567 1568static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1569 1570static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1571 1572#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 1573 1574#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 1575 1576#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 1577 1578#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 1579 1580#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 1581 1582#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 1583 1584#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 1585 1586#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 1587 1588#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 1589 1590#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 1591 1592#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 1593 1594#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 1595 1596#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 1597 1598#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 1599 1600#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 1601 1602#define REG_A4XX_RBBM_AHB_CTL0 0x00000023 1603 1604#define REG_A4XX_RBBM_AHB_CTL1 0x00000024 1605 1606#define REG_A4XX_RBBM_AHB_CMD 0x00000025 1607 1608#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 1609 1610#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 1611 1612#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 1613 1614#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 1615 1616#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 1617 1618#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 1619 1620#define REG_A4XX_RBBM_INT_0_MASK 0x00000037 1621 1622#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 1623 1624#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 1625 1626#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 1627 1628#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 1629 1630#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1631 1632#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 1633 1634#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 1635 1636#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 1637 1638#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 1639 1640#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 1641 1642#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 1643 1644#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 1645#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 1646#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 1647 1648#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1649 1650#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d 1651 1652#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e 1653 1654#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f 1655 1656#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 1657 1658#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 1659 1660#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 1661 1662#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 1663 1664#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 1665 1666#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 1667 1668#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 1669 1670#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 1671 1672#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 1673 1674#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 1675 1676#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa 1677 1678#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab 1679 1680#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac 1681 1682#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad 1683 1684#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae 1685 1686#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af 1687 1688#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 1689 1690#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 1691 1692#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 1693 1694#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 1695 1696#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 1697 1698#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 1699 1700#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 1701 1702#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 1703 1704#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 1705 1706#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 1707 1708#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba 1709 1710#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb 1711 1712#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc 1713 1714#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd 1715 1716#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be 1717 1718#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf 1719 1720#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 1721 1722#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 1723 1724#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 1725 1726#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 1727 1728#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 1729 1730#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 1731 1732#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 1733 1734#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 1735 1736#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 1737 1738#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 1739 1740#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca 1741 1742#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb 1743 1744#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc 1745 1746#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd 1747 1748#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce 1749 1750#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf 1751 1752#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 1753 1754#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 1755 1756#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 1757 1758#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 1759 1760#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 1761 1762#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 1763 1764#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 1765 1766#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 1767 1768#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 1769 1770#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 1771 1772#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da 1773 1774#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db 1775 1776#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc 1777 1778#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd 1779 1780#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de 1781 1782#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df 1783 1784#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 1785 1786#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 1787 1788#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 1789 1790#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 1791 1792#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 1793 1794#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 1795 1796#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 1797 1798#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 1799 1800#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 1801 1802#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 1803 1804#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea 1805 1806#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb 1807 1808#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec 1809 1810#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed 1811 1812#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee 1813 1814#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef 1815 1816#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 1817 1818#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 1819 1820#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 1821 1822#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 1823 1824#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 1825 1826#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 1827 1828#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 1829 1830#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 1831 1832#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 1833 1834#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 1835 1836#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa 1837 1838#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb 1839 1840#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc 1841 1842#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd 1843 1844#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe 1845 1846#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff 1847 1848#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 1849 1850#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 1851 1852#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 1853 1854#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 1855 1856#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 1857 1858#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 1859 1860#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 1861 1862#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 1863 1864#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 1865 1866#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 1867 1868#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a 1869 1870#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b 1871 1872#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c 1873 1874#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d 1875 1876#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e 1877 1878#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f 1879 1880#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 1881 1882#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 1883 1884#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 1885 1886#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 1887 1888#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1889 1890#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1891 1892#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1893 1894#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1895 1896#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 1897 1898#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 1899 1900#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 1901 1902#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 1903 1904#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a 1905 1906#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b 1907 1908#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c 1909 1910#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d 1911 1912#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e 1913 1914#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f 1915 1916#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 1917 1918#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 1919 1920#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 1921 1922#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 1923 1924#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 1925 1926#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 1927 1928#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 1929 1930#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 1931 1932#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 1933 1934#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 1935 1936#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a 1937 1938#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b 1939 1940#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c 1941 1942#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d 1943 1944#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e 1945 1946#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f 1947 1948#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 1949 1950#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 1951 1952#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 1953 1954#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 1955 1956#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 1957 1958#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 1959 1960#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 1961 1962#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 1963 1964#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 1965 1966#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 1967 1968#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a 1969 1970#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b 1971 1972#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c 1973 1974#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d 1975 1976#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e 1977 1978#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f 1979 1980#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 1981 1982#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 1983 1984#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 1985 1986#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 1987 1988#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 1989 1990#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 1991 1992#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 1993 1994#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 1995 1996#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 1997 1998#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 1999 2000#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a 2001 2002#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b 2003 2004#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c 2005 2006#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d 2007 2008#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e 2009 2010#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f 2011 2012#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 2013 2014#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 2015 2016#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2017 2018#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 2019 2020#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e 2021 2022#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f 2023 2024static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2025 2026static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2027 2028static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2029 2030static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2031 2032static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2033 2034static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2035 2036static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2037 2038static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2039 2040static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2041 2042static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2043 2044static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2045 2046static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2047 2048static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2049 2050static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2051 2052static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2053 2054static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2055 2056#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 2057 2058#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 2059 2060#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 2061 2062#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 2063 2064#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 2065 2066#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 2067 2068static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2069 2070static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2071 2072#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 2073 2074#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a 2075 2076#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2077 2078#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 2079 2080#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 2081 2082#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 2083 2084#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 2085 2086#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 2087 2088#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 2089 2090#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 2091 2092#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 2093 2094#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 2095 2096#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 2097 2098#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 2099 2100#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 2101 2102#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 2103 2104#define REG_A4XX_RBBM_AHB_STATUS 0x00000189 2105 2106#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 2107 2108#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 2109 2110#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 2111 2112#define REG_A4XX_RBBM_STATUS 0x00000191 2113#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 2114#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 2115#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 2116#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 2117#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 2118#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 2119#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 2120#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 2121#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 2122#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 2123#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 2124#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 2125#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 2126#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 2127#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 2128#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 2129#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 2130#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 2131#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 2132#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 2133#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 2134 2135#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 2136 2137#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 2138#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 2139 2140#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 2141 2142#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 2143 2144#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 2145 2146#define REG_A4XX_CP_RB_BASE 0x00000200 2147 2148#define REG_A4XX_CP_RB_CNTL 0x00000201 2149 2150#define REG_A4XX_CP_RB_WPTR 0x00000205 2151 2152#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 2153 2154#define REG_A4XX_CP_RB_RPTR 0x00000204 2155 2156#define REG_A4XX_CP_IB1_BASE 0x00000206 2157 2158#define REG_A4XX_CP_IB1_BUFSZ 0x00000207 2159 2160#define REG_A4XX_CP_IB2_BASE 0x00000208 2161 2162#define REG_A4XX_CP_IB2_BUFSZ 0x00000209 2163 2164#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 2165 2166#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 2167 2168#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 2169 2170#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 2171 2172#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 2173 2174#define REG_A4XX_CP_ROQ_ADDR 0x0000021c 2175 2176#define REG_A4XX_CP_ROQ_DATA 0x0000021d 2177 2178#define REG_A4XX_CP_MEQ_ADDR 0x0000021e 2179 2180#define REG_A4XX_CP_MEQ_DATA 0x0000021f 2181 2182#define REG_A4XX_CP_MERCIU_ADDR 0x00000220 2183 2184#define REG_A4XX_CP_MERCIU_DATA 0x00000221 2185 2186#define REG_A4XX_CP_MERCIU_DATA2 0x00000222 2187 2188#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 2189 2190#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 2191 2192#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 2193 2194#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 2195 2196#define REG_A4XX_CP_ME_RAM_DATA 0x00000227 2197 2198#define REG_A4XX_CP_PREEMPT 0x0000022a 2199 2200#define REG_A4XX_CP_CNTL 0x0000022c 2201 2202#define REG_A4XX_CP_ME_CNTL 0x0000022d 2203 2204#define REG_A4XX_CP_DEBUG 0x0000022e 2205 2206#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 2207 2208#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2209 2210static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2211 2212static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2213#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 2214#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 2215static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 2216{ 2217 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; 2218} 2219#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 2220#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 2221static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 2222{ 2223 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; 2224} 2225#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 2226#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 2227 2228#define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2229 2230#define REG_A4XX_CP_ST_BASE 0x000004c0 2231 2232#define REG_A4XX_CP_STQ_AVAIL 0x000004ce 2233 2234#define REG_A4XX_CP_MERCIU_STAT 0x000004d0 2235 2236#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 2237 2238#define REG_A4XX_CP_HW_FAULT 0x000004d8 2239 2240#define REG_A4XX_CP_PROTECT_STATUS 0x000004da 2241 2242#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 2243 2244#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 2245 2246#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 2247 2248#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 2249 2250#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 2251 2252#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 2253 2254#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 2255 2256#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 2257 2258#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 2259 2260#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 2261 2262static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2263 2264static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2265 2266#define REG_A4XX_SP_VS_STATUS 0x00000ec0 2267 2268#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 2269 2270#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 2271 2272#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 2273 2274#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 2275 2276#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 2277 2278#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 2279 2280#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 2281 2282#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca 2283 2284#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb 2285 2286#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc 2287 2288#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd 2289 2290#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece 2291 2292#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 2293 2294#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 2295#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 2296 2297#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 2298#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 2299#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 2300#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 2301 2302#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 2303#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2304#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2305static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2306{ 2307 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2308} 2309#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 2310#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2311#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2312#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2313static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2314{ 2315 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2316} 2317#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2318#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2319static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2320{ 2321 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2322} 2323#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2324#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2325static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2326{ 2327 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2328} 2329#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2330#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2331static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2332{ 2333 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2334} 2335#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2336#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2337 2338#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 2339#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2340#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2341static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2342{ 2343 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2344} 2345#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2346#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2347static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2348{ 2349 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2350} 2351 2352#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 2353#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2354#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2355static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2356{ 2357 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 2358} 2359#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2360#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2361static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2362{ 2363 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2364} 2365#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2366#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2367static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2368{ 2369 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2370} 2371 2372static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2373 2374static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2375#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2376#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2377static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2378{ 2379 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 2380} 2381#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2382#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2383static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2384{ 2385 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2386} 2387#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2388#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2389static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2390{ 2391 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 2392} 2393#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2394#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2395static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2396{ 2397 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2398} 2399 2400static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2401 2402static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2403#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2404#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2405static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2406{ 2407 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2408} 2409#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2410#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2411static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2412{ 2413 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2414} 2415#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2416#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2417static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2418{ 2419 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2420} 2421#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2422#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2423static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2424{ 2425 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2426} 2427 2428#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 2429#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2430#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2431static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2432{ 2433 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2434} 2435#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2436#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2437static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2438{ 2439 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2440} 2441 2442#define REG_A4XX_SP_VS_OBJ_START 0x000022e1 2443 2444#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 2445 2446#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 2447 2448#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 2449 2450#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 2451#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2452#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2453static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2454{ 2455 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2456} 2457#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 2458#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2459#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2460#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2461static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2462{ 2463 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2464} 2465#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2466#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2467static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2468{ 2469 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2470} 2471#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2472#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2473static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2474{ 2475 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2476} 2477#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2478#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2479static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2480{ 2481 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2482} 2483#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2484#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2485 2486#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 2487#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2488#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2489static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2490{ 2491 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2492} 2493#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 2494#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 2495#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 2496 2497#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 2498#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2499#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2500static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2501{ 2502 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2503} 2504#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2505#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2506static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2507{ 2508 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2509} 2510 2511#define REG_A4XX_SP_FS_OBJ_START 0x000022eb 2512 2513#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 2514 2515#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 2516 2517#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 2518 2519#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 2520#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 2521#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2522static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2523{ 2524 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 2525} 2526#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2527#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2528#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2529static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2530{ 2531 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2532} 2533#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 2534#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 2535static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 2536{ 2537 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 2538} 2539 2540static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2541 2542static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2543#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2544#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 2545static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 2546{ 2547 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 2548} 2549#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2550#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 2551#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 2552static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 2553{ 2554 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 2555} 2556#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 2557 2558#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 2559 2560#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 2561 2562#define REG_A4XX_SP_CS_OBJ_START 0x00002302 2563 2564#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 2565 2566#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 2567 2568#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 2569 2570#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 2571 2572#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 2573#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2574#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2575static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2576{ 2577 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2578} 2579#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2580#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2581static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2582{ 2583 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2584} 2585 2586#define REG_A4XX_SP_HS_OBJ_START 0x0000230e 2587 2588#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 2589 2590#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 2591 2592#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 2593 2594#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 2595#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 2596#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 2597static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 2598{ 2599 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 2600} 2601#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 2602#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 2603static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 2604{ 2605 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 2606} 2607 2608static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 2609 2610static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 2611#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 2612#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 2613static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 2614{ 2615 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 2616} 2617#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2618#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 2619static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 2620{ 2621 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 2622} 2623#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 2624#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 2625static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 2626{ 2627 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 2628} 2629#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2630#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 2631static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 2632{ 2633 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 2634} 2635 2636static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 2637 2638static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 2639#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2640#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 2641static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 2642{ 2643 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 2644} 2645#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2646#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 2647static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 2648{ 2649 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 2650} 2651#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2652#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 2653static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 2654{ 2655 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 2656} 2657#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2658#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 2659static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 2660{ 2661 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 2662} 2663 2664#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 2665#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2666#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2667static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2668{ 2669 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2670} 2671#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2672#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2673static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2674{ 2675 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2676} 2677 2678#define REG_A4XX_SP_DS_OBJ_START 0x00002335 2679 2680#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 2681 2682#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 2683 2684#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 2685 2686#define REG_A4XX_SP_GS_PARAM_REG 0x00002341 2687#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 2688#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 2689static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 2690{ 2691 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 2692} 2693#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 2694#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 2695static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 2696{ 2697 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 2698} 2699#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 2700#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 2701static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 2702{ 2703 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 2704} 2705 2706static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 2707 2708static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 2709#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 2710#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 2711static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 2712{ 2713 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 2714} 2715#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2716#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 2717static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 2718{ 2719 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 2720} 2721#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 2722#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 2723static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 2724{ 2725 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 2726} 2727#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2728#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 2729static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 2730{ 2731 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 2732} 2733 2734static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 2735 2736static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 2737#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2738#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 2739static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 2740{ 2741 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 2742} 2743#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2744#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 2745static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 2746{ 2747 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 2748} 2749#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2750#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 2751static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 2752{ 2753 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 2754} 2755#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2756#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 2757static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 2758{ 2759 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 2760} 2761 2762#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 2763#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2764#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2765static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2766{ 2767 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2768} 2769#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2770#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2771static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2772{ 2773 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2774} 2775 2776#define REG_A4XX_SP_GS_OBJ_START 0x0000235c 2777 2778#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 2779 2780#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 2781 2782#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 2783 2784#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 2785 2786#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 2787 2788#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 2789 2790#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 2791 2792#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 2793 2794#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 2795 2796#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 2797 2798#define REG_A4XX_VPC_ATTR 0x00002140 2799#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2800#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 2801static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 2802{ 2803 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 2804} 2805#define A4XX_VPC_ATTR_PSIZE 0x00000200 2806#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 2807#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2808static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2809{ 2810 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 2811} 2812#define A4XX_VPC_ATTR_ENABLE 0x02000000 2813 2814#define REG_A4XX_VPC_PACK 0x00002141 2815#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 2816#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 2817static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 2818{ 2819 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 2820} 2821#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2822#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2823static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2824{ 2825 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2826} 2827#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2828#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2829static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2830{ 2831 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2832} 2833 2834static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2835 2836static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2837 2838static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2839 2840static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2841 2842#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 2843 2844#define REG_A4XX_VSC_BIN_SIZE 0x00000c00 2845#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2846#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2847static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2848{ 2849 assert(!(val & 0x1f)); 2850 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 2851} 2852#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2853#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2854static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2855{ 2856 assert(!(val & 0x1f)); 2857 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 2858} 2859 2860#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 2861 2862#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 2863 2864#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 2865 2866static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2867 2868static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2869#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2870#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2871static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2872{ 2873 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 2874} 2875#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2876#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2877static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2878{ 2879 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2880} 2881#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 2882#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2883static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2884{ 2885 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 2886} 2887#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 2888#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2889static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2890{ 2891 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 2892} 2893 2894static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2895 2896static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2897 2898static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2899 2900static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2901 2902#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 2903 2904#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 2905 2906#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 2907 2908#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 2909 2910#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 2911 2912#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 2913 2914#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 2915 2916#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 2917 2918#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 2919 2920#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 2921 2922#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 2923 2924#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 2925 2926#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 2927 2928#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 2929 2930#define REG_A4XX_VFD_CONTROL_0 0x00002200 2931#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 2932#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 2933static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 2934{ 2935 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 2936} 2937#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 2938#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 2939static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 2940{ 2941 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 2942} 2943#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 2944#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 2945static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 2946{ 2947 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 2948} 2949#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 2950#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 2951static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 2952{ 2953 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 2954} 2955 2956#define REG_A4XX_VFD_CONTROL_1 0x00002201 2957#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 2958#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 2959static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 2960{ 2961 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 2962} 2963#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2964#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2965static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2966{ 2967 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 2968} 2969#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 2970#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 2971static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 2972{ 2973 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 2974} 2975 2976#define REG_A4XX_VFD_CONTROL_2 0x00002202 2977 2978#define REG_A4XX_VFD_CONTROL_3 0x00002203 2979#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 2980#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 2981static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 2982{ 2983 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 2984} 2985#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 2986#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 2987static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 2988{ 2989 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 2990} 2991#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 2992#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 2993static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 2994{ 2995 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 2996} 2997 2998#define REG_A4XX_VFD_CONTROL_4 0x00002204 2999 3000#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 3001 3002static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 3003 3004static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 3005#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 3006#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 3007static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 3008{ 3009 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 3010} 3011#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 3012#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 3013static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 3014{ 3015 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 3016} 3017#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 3018#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 3019 3020static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 3021 3022static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 3023#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff 3024#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0 3025static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 3026{ 3027 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 3028} 3029 3030static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 3031#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 3032#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 3033static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 3034{ 3035 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 3036} 3037 3038static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3039 3040static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3041#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 3042#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 3043static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 3044{ 3045 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 3046} 3047#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 3048#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 3049#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 3050static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 3051{ 3052 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 3053} 3054#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 3055#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 3056static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 3057{ 3058 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 3059} 3060#define A4XX_VFD_DECODE_INSTR_INT 0x00100000 3061#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 3062#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 3063static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3064{ 3065 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 3066} 3067#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 3068#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 3069static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 3070{ 3071 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 3072} 3073#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 3074#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 3075 3076#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 3077 3078#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 3079 3080#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 3081 3082#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 3083 3084#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 3085 3086#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 3087 3088#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 3089 3090#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 3091 3092#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a 3093 3094#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 3095 3096#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 3097 3098#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 3099#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 3100#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 3101static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 3102{ 3103 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 3104} 3105#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 3106#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 3107static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 3108{ 3109 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 3110} 3111#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 3112#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 3113static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 3114{ 3115 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 3116} 3117#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 3118#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 3119static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 3120{ 3121 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 3122} 3123 3124#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 3125 3126#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 3127 3128#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 3129 3130#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 3131 3132#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 3133 3134#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 3135 3136#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 3137 3138#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 3139 3140#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 3141 3142#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 3143 3144#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 3145 3146#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 3147 3148#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 3149 3150#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a 3151 3152#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 3153 3154#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c 3155 3156#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d 3157 3158#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e 3159 3160#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f 3161 3162#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3163#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3164#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 3165#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 3166#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3167 3168#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 3169#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 3170 3171#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 3172#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 3173#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 3174static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 3175{ 3176 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 3177} 3178#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 3179#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 3180static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 3181{ 3182 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 3183} 3184 3185#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 3186#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 3187#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 3188static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 3189{ 3190 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 3191} 3192 3193#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 3194#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 3195#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 3196static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 3197{ 3198 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 3199} 3200 3201#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 3202#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 3203#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 3204static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 3205{ 3206 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 3207} 3208 3209#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 3210#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 3211#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 3212static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 3213{ 3214 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 3215} 3216 3217#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 3218#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 3219#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 3220static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 3221{ 3222 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 3223} 3224 3225#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 3226#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 3227#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 3228static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 3229{ 3230 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 3231} 3232 3233#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 3234#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 3235#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 3236static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 3237{ 3238 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 3239} 3240#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 3241#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 3242static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 3243{ 3244 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 3245} 3246 3247#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 3248#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 3249#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 3250static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 3251{ 3252 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 3253} 3254 3255#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 3256#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 3257#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 3258 3259#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 3260#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 3261#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 3262static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 3263{ 3264 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 3265} 3266 3267#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 3268#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 3269#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 3270static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 3271{ 3272 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 3273} 3274 3275#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 3276#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 3277#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 3278static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 3279{ 3280 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 3281} 3282 3283#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 3284#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 3285#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 3286static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 3287{ 3288 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 3289} 3290 3291#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 3292#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 3293#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 3294#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 3295#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 3296#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 3297static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 3298{ 3299 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 3300} 3301#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 3302#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 3303#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 3304 3305#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 3306#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 3307#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 3308static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 3309{ 3310 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 3311} 3312#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 3313#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 3314static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 3315{ 3316 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 3317} 3318#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 3319#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 3320#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 3321static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 3322{ 3323 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 3324} 3325 3326#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 3327#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3328#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 3329#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3330static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 3331{ 3332 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 3333} 3334#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 3335#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3336static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 3337{ 3338 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 3339} 3340 3341#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 3342#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3343#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 3344#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3345static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 3346{ 3347 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 3348} 3349#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 3350#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3351static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 3352{ 3353 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 3354} 3355 3356#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 3357#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3358#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3359#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3360static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3361{ 3362 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3363} 3364#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3365#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3366static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3367{ 3368 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3369} 3370 3371#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 3372#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3373#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3374#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3375static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3376{ 3377 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3378} 3379#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3380#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3381static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3382{ 3383 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3384} 3385 3386#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 3387#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 3388#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 3389#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 3390static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 3391{ 3392 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 3393} 3394#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 3395#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 3396static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 3397{ 3398 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 3399} 3400 3401#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 3402#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 3403#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 3404#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 3405static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 3406{ 3407 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 3408} 3409#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 3410#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 3411static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 3412{ 3413 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 3414} 3415 3416#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 3417 3418#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 3419 3420#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 3421 3422#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 3423 3424#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 3425 3426#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 3427 3428#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 3429 3430#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e 3431 3432#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f 3433 3434#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 3435 3436#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 3437 3438#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 3439 3440#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 3441 3442#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 3443 3444#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 3445 3446#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 3447 3448#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 3449 3450#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 3451 3452#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 3453 3454#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 3455 3456#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 3457 3458#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 3459 3460#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 3461 3462#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a 3463 3464#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b 3465 3466#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c 3467 3468#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d 3469 3470#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 3471#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 3472#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 3473static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 3474{ 3475 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 3476} 3477#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 3478#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 3479#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 3480#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 3481#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 3482#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 3483static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 3484{ 3485 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 3486} 3487#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 3488#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 3489#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 3490#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 3491 3492#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 3493#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 3494#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 3495static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 3496{ 3497 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 3498} 3499#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 3500#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 3501#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 3502#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 3503static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 3504{ 3505 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 3506} 3507#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 3508#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 3509static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 3510{ 3511 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 3512} 3513 3514#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 3515#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 3516#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 3517static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3518{ 3519 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 3520} 3521#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 3522#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 3523static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 3524{ 3525 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 3526} 3527#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 3528#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 3529static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 3530{ 3531 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 3532} 3533#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 3534#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 3535static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 3536{ 3537 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 3538} 3539 3540#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 3541#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 3542#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 3543static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 3544{ 3545 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 3546} 3547 3548#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 3549 3550#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 3551#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3552#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3553static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3554{ 3555 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 3556} 3557#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3558#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3559static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3560{ 3561 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3562} 3563#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000 3564#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 3565#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3566#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3567static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3568{ 3569 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3570} 3571#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3572#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3573static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3574{ 3575 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 3576} 3577 3578#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 3579#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3580#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3581static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3582{ 3583 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 3584} 3585#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3586#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3587static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3588{ 3589 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3590} 3591#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000 3592#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 3593#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3594#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3595static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3596{ 3597 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3598} 3599#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3600#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3601static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3602{ 3603 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 3604} 3605 3606#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 3607#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3608#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3609static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3610{ 3611 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 3612} 3613#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3614#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3615static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3616{ 3617 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3618} 3619#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000 3620#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 3621#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3622#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3623static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3624{ 3625 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3626} 3627#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3628#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3629static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3630{ 3631 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 3632} 3633 3634#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 3635#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3636#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3637static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3638{ 3639 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 3640} 3641#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3642#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3643static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3644{ 3645 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3646} 3647#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000 3648#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 3649#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3650#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3651static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3652{ 3653 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3654} 3655#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3656#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3657static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3658{ 3659 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 3660} 3661 3662#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 3663#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3664#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3665static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3666{ 3667 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 3668} 3669#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3670#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3671static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3672{ 3673 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3674} 3675#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000 3676#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 3677#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3678#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3679static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3680{ 3681 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3682} 3683#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3684#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3685static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3686{ 3687 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 3688} 3689 3690#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca 3691#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3692#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3693static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3694{ 3695 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK; 3696} 3697#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3698#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3699static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3700{ 3701 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3702} 3703#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000 3704#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000 3705#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3706#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3707static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3708{ 3709 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3710} 3711#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3712#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3713static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3714{ 3715 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK; 3716} 3717 3718#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 3719#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003 3720#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0 3721static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) 3722{ 3723 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK; 3724} 3725#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 3726#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2 3727static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) 3728{ 3729 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK; 3730} 3731#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 3732#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12 3733static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) 3734{ 3735 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK; 3736} 3737#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 3738#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22 3739static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) 3740{ 3741 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK; 3742} 3743 3744#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 3745#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff 3746#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0 3747static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) 3748{ 3749 return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK; 3750} 3751 3752#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 3753 3754#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 3755#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff 3756#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0 3757static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) 3758{ 3759 return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK; 3760} 3761 3762#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 3763 3764#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 3765#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff 3766#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0 3767static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) 3768{ 3769 return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK; 3770} 3771 3772#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 3773 3774#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 3775#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff 3776#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0 3777static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) 3778{ 3779 return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK; 3780} 3781#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000 3782#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24 3783static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) 3784{ 3785 return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK; 3786} 3787 3788#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 3789 3790#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 3791 3792#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 3793 3794#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 3795 3796#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 3797 3798#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 3799 3800#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 3801 3802#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3803#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3804 3805#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 3806 3807#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3808 3809#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3810 3811#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 3812 3813#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 3814 3815#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 3816 3817#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 3818 3819#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 3820 3821#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 3822 3823#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 3824 3825#define REG_A4XX_PC_BIN_BASE 0x000021c0 3826 3827#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 3828#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 3829#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 3830static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 3831{ 3832 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; 3833} 3834#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 3835#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 3836static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) 3837{ 3838 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; 3839} 3840 3841#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3842#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3843#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3844static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 3845{ 3846 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 3847} 3848#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 3849#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 3850#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 3851 3852#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 3853#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3854#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 3855static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3856{ 3857 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; 3858} 3859#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 3860#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 3861static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3862{ 3863 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; 3864} 3865#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 3866 3867#define REG_A4XX_PC_RESTART_INDEX 0x000021c6 3868 3869#define REG_A4XX_PC_GS_PARAM 0x000021e5 3870#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3871#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3872static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3873{ 3874 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3875} 3876#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3877#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3878static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3879{ 3880 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 3881} 3882#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3883#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3884static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3885{ 3886 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 3887} 3888#define A4XX_PC_GS_PARAM_LAYER 0x80000000 3889 3890#define REG_A4XX_PC_HS_PARAM 0x000021e7 3891#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3892#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3893static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3894{ 3895 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3896} 3897#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3898#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 3899static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3900{ 3901 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3902} 3903#define A4XX_PC_HS_PARAM_CW 0x00800000 3904#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 3905 3906#define REG_A4XX_VBIF_VERSION 0x00003000 3907 3908#define REG_A4XX_VBIF_CLKON 0x00003001 3909#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 3910 3911#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 3912 3913#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 3914 3915#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 3916 3917#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 3918 3919#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 3920 3921#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 3922 3923#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 3924 3925#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 3926 3927#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0 3928 3929#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1 3930 3931#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2 3932 3933#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3 3934 3935#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0 3936 3937#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1 3938 3939#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2 3940 3941#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3 3942 3943#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8 3944 3945#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9 3946 3947#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da 3948 3949#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db 3950 3951#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0 3952 3953#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1 3954 3955#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2 3956 3957#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3 3958 3959#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 3960 3961#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 3962 3963#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 3964 3965#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 3966 3967#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 3968 3969#define REG_A4XX_UNKNOWN_0D01 0x00000d01 3970 3971#define REG_A4XX_UNKNOWN_0E42 0x00000e42 3972 3973#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 3974 3975#define REG_A4XX_UNKNOWN_2001 0x00002001 3976 3977#define REG_A4XX_UNKNOWN_209B 0x0000209b 3978 3979#define REG_A4XX_UNKNOWN_20EF 0x000020ef 3980 3981#define REG_A4XX_UNKNOWN_2152 0x00002152 3982 3983#define REG_A4XX_UNKNOWN_2153 0x00002153 3984 3985#define REG_A4XX_UNKNOWN_2154 0x00002154 3986 3987#define REG_A4XX_UNKNOWN_2155 0x00002155 3988 3989#define REG_A4XX_UNKNOWN_2156 0x00002156 3990 3991#define REG_A4XX_UNKNOWN_2157 0x00002157 3992 3993#define REG_A4XX_UNKNOWN_21C3 0x000021c3 3994 3995#define REG_A4XX_UNKNOWN_21E6 0x000021e6 3996 3997#define REG_A4XX_UNKNOWN_2209 0x00002209 3998 3999#define REG_A4XX_UNKNOWN_22D7 0x000022d7 4000 4001#define REG_A4XX_UNKNOWN_2352 0x00002352 4002 4003#define REG_A4XX_TEX_SAMP_0 0x00000000 4004#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 4005#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 4006#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 4007static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 4008{ 4009 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 4010} 4011#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 4012#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 4013static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 4014{ 4015 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 4016} 4017#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 4018#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 4019static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 4020{ 4021 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 4022} 4023#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 4024#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 4025static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 4026{ 4027 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 4028} 4029#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 4030#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 4031static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 4032{ 4033 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 4034} 4035#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 4036#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 4037static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 4038{ 4039 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 4040} 4041#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 4042#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 4043static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) 4044{ 4045 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; 4046} 4047 4048#define REG_A4XX_TEX_SAMP_1 0x00000001 4049#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 4050#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 4051static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 4052{ 4053 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 4054} 4055#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 4056#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 4057#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 4058#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 4059#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 4060static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 4061{ 4062 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 4063} 4064#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 4065#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 4066static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 4067{ 4068 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 4069} 4070 4071#define REG_A4XX_TEX_CONST_0 0x00000000 4072#define A4XX_TEX_CONST_0_TILED 0x00000001 4073#define A4XX_TEX_CONST_0_SRGB 0x00000004 4074#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 4075#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 4076static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 4077{ 4078 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 4079} 4080#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 4081#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 4082static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 4083{ 4084 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 4085} 4086#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 4087#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 4088static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 4089{ 4090 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 4091} 4092#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 4093#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 4094static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 4095{ 4096 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 4097} 4098#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 4099#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 4100static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 4101{ 4102 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 4103} 4104#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 4105#define A4XX_TEX_CONST_0_FMT__SHIFT 22 4106static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 4107{ 4108 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 4109} 4110#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 4111#define A4XX_TEX_CONST_0_TYPE__SHIFT 29 4112static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 4113{ 4114 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 4115} 4116 4117#define REG_A4XX_TEX_CONST_1 0x00000001 4118#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 4119#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 4120static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 4121{ 4122 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 4123} 4124#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 4125#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 4126static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 4127{ 4128 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 4129} 4130 4131#define REG_A4XX_TEX_CONST_2 0x00000002 4132#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 4133#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 4134static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 4135{ 4136 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 4137} 4138#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 4139#define A4XX_TEX_CONST_2_PITCH__SHIFT 9 4140static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 4141{ 4142 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 4143} 4144#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 4145#define A4XX_TEX_CONST_2_SWAP__SHIFT 30 4146static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 4147{ 4148 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 4149} 4150 4151#define REG_A4XX_TEX_CONST_3 0x00000003 4152#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 4153#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 4154static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 4155{ 4156 assert(!(val & 0xfff)); 4157 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 4158} 4159#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 4160#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 4161static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 4162{ 4163 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 4164} 4165 4166#define REG_A4XX_TEX_CONST_4 0x00000004 4167#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 4168#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 4169static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 4170{ 4171 assert(!(val & 0xfff)); 4172 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 4173} 4174#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 4175#define A4XX_TEX_CONST_4_BASE__SHIFT 5 4176static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 4177{ 4178 assert(!(val & 0x1f)); 4179 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 4180} 4181 4182#define REG_A4XX_TEX_CONST_5 0x00000005 4183 4184#define REG_A4XX_TEX_CONST_6 0x00000006 4185 4186#define REG_A4XX_TEX_CONST_7 0x00000007 4187 4188#define REG_A4XX_SSBO_0_0 0x00000000 4189#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0 4190#define A4XX_SSBO_0_0_BASE__SHIFT 5 4191static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) 4192{ 4193 assert(!(val & 0x1f)); 4194 return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; 4195} 4196 4197#define REG_A4XX_SSBO_0_1 0x00000001 4198#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff 4199#define A4XX_SSBO_0_1_PITCH__SHIFT 0 4200static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) 4201{ 4202 return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK; 4203} 4204 4205#define REG_A4XX_SSBO_0_2 0x00000002 4206#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 4207#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 4208static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) 4209{ 4210 assert(!(val & 0xfff)); 4211 return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; 4212} 4213 4214#define REG_A4XX_SSBO_0_3 0x00000003 4215#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f 4216#define A4XX_SSBO_0_3_CPP__SHIFT 0 4217static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) 4218{ 4219 return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK; 4220} 4221 4222#define REG_A4XX_SSBO_1_0 0x00000000 4223#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f 4224#define A4XX_SSBO_1_0_CPP__SHIFT 0 4225static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) 4226{ 4227 return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK; 4228} 4229#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00 4230#define A4XX_SSBO_1_0_FMT__SHIFT 8 4231static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) 4232{ 4233 return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK; 4234} 4235#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000 4236#define A4XX_SSBO_1_0_WIDTH__SHIFT 16 4237static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) 4238{ 4239 return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK; 4240} 4241 4242#define REG_A4XX_SSBO_1_1 0x00000001 4243#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff 4244#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0 4245static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) 4246{ 4247 return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK; 4248} 4249#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000 4250#define A4XX_SSBO_1_1_DEPTH__SHIFT 16 4251static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) 4252{ 4253 return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; 4254} 4255 4256 4257#endif /* A4XX_XML */ 4258