1/**************************************************************************
2 *
3 * Copyright 2010-2012 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 **************************************************************************/
27
28
29#ifndef LP_BLD_LIMITS_H_
30#define LP_BLD_LIMITS_H_
31
32
33#include <limits.h>
34
35#include "pipe/p_state.h"
36#include "pipe/p_defines.h"
37
38
39/*
40 * TGSI translation limits.
41 *
42 * Some are slightly above SM 3.0 requirements to give some wiggle room to
43 * the state trackers.
44 */
45
46#define LP_MAX_TGSI_TEMPS 4096
47
48#define LP_MAX_TGSI_ADDRS 16
49
50#define LP_MAX_TGSI_IMMEDIATES 4096
51
52#define LP_MAX_TGSI_CONSTS 4096
53
54#define LP_MAX_TGSI_CONST_BUFFERS 16
55
56#define LP_MAX_TGSI_CONST_BUFFER_SIZE (LP_MAX_TGSI_CONSTS * sizeof(float[4]))
57
58/*
59 * For quick access we cache registers in statically
60 * allocated arrays. Here we define the maximum size
61 * for those arrays.
62 */
63#define LP_MAX_INLINED_TEMPS 256
64
65#define LP_MAX_INLINED_IMMEDIATES 256
66
67/**
68 * Maximum control flow nesting
69 *
70 * SM4.0 requires 64 (per subroutine actually, subroutine nesting itself is 32)
71 * SM3.0 requires 24 (most likely per subroutine too)
72 * add 2 more (some translation could add one more)
73 */
74#define LP_MAX_TGSI_NESTING 66
75
76/**
77 * Maximum iterations before loop termination
78 * Shared between every loop in a TGSI shader
79 */
80#define LP_MAX_TGSI_LOOP_ITERATIONS 65535
81
82
83/**
84 * Some of these limits are actually infinite (i.e., only limited by available
85 * memory), however advertising INT_MAX would cause some test problems to
86 * actually try to allocate the maximum and run out of memory and crash.  So
87 * stick with something reasonable here.
88 */
89static inline int
90gallivm_get_shader_param(enum pipe_shader_cap param)
91{
92   switch(param) {
93   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
94   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
95   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
96   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
97      return 1 * 1024 * 1024;
98   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
99      return LP_MAX_TGSI_NESTING;
100   case PIPE_SHADER_CAP_MAX_INPUTS:
101      return 32;
102   case PIPE_SHADER_CAP_MAX_OUTPUTS:
103      return 32;
104   case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
105      return LP_MAX_TGSI_CONST_BUFFER_SIZE;
106   case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
107      return PIPE_MAX_CONSTANT_BUFFERS;
108   case PIPE_SHADER_CAP_MAX_TEMPS:
109      return LP_MAX_TGSI_TEMPS;
110   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
111      return 1;
112   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
113   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
114   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
115   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
116      return 1;
117   case PIPE_SHADER_CAP_SUBROUTINES:
118      return 1;
119   case PIPE_SHADER_CAP_INTEGERS:
120      return 1;
121   case PIPE_SHADER_CAP_INT64_ATOMICS:
122   case PIPE_SHADER_CAP_FP16:
123      return 0;
124   case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
125      return PIPE_MAX_SAMPLERS;
126   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
127      return PIPE_MAX_SHADER_SAMPLER_VIEWS;
128   case PIPE_SHADER_CAP_PREFERRED_IR:
129      return PIPE_SHADER_IR_TGSI;
130   case PIPE_SHADER_CAP_SUPPORTED_IRS:
131      return 1 << PIPE_SHADER_IR_TGSI;
132   case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
133   case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
134      return 1;
135   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
136   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
137   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
138   case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
139   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
140   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
141   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
142   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
143   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
144   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
145      return 0;
146   case PIPE_SHADER_CAP_SCALAR_ISA:
147      return 1;
148   case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
149      return 32;
150   }
151   /* if we get here, we missed a shader cap above (and should have seen
152    * a compiler warning.)
153    */
154   return 0;
155}
156
157
158#endif /* LP_BLD_LIMITS_H_ */
159