1/* 2 * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28#include "util/u_string.h" 29#include "util/u_memory.h" 30#include "util/u_helpers.h" 31 32#include "freedreno_resource.h" 33 34#include "fd2_emit.h" 35#include "fd2_blend.h" 36#include "fd2_context.h" 37#include "fd2_program.h" 38#include "fd2_rasterizer.h" 39#include "fd2_texture.h" 40#include "fd2_util.h" 41#include "fd2_zsa.h" 42 43/* NOTE: just define the position for const regs statically.. the blob 44 * driver doesn't seem to change these dynamically, and I can't really 45 * think of a good reason to so.. 46 */ 47#define VS_CONST_BASE 0x20 48#define PS_CONST_BASE 0x120 49 50static void 51emit_constants(struct fd_ringbuffer *ring, uint32_t base, 52 struct fd_constbuf_stateobj *constbuf, 53 struct fd2_shader_stateobj *shader) 54{ 55 uint32_t enabled_mask = constbuf->enabled_mask; 56 uint32_t start_base = base; 57 unsigned i; 58 59 /* emit user constants: */ 60 while (enabled_mask) { 61 unsigned index = ffs(enabled_mask) - 1; 62 struct pipe_constant_buffer *cb = &constbuf->cb[index]; 63 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */ 64 65 // I expect that size should be a multiple of vec4's: 66 assert(size == align(size, 4)); 67 68 /* hmm, sometimes we still seem to end up with consts bound, 69 * even if shader isn't using them, which ends up overwriting 70 * const reg's used for immediates.. this is a hack to work 71 * around that: 72 */ 73 if (shader && ((base - start_base) >= (shader->first_immediate * 4))) 74 break; 75 76 const uint32_t *dwords; 77 78 if (cb->user_buffer) { 79 dwords = cb->user_buffer; 80 } else { 81 struct fd_resource *rsc = fd_resource(cb->buffer); 82 dwords = fd_bo_map(rsc->bo); 83 } 84 85 dwords = (uint32_t *)(((uint8_t *)dwords) + cb->buffer_offset); 86 87 OUT_PKT3(ring, CP_SET_CONSTANT, size + 1); 88 OUT_RING(ring, base); 89 for (i = 0; i < size; i++) 90 OUT_RING(ring, *(dwords++)); 91 92 base += size; 93 enabled_mask &= ~(1 << index); 94 } 95 96 /* emit shader immediates: */ 97 if (shader) { 98 for (i = 0; i < shader->num_immediates; i++) { 99 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 100 OUT_RING(ring, start_base + (4 * (shader->first_immediate + i))); 101 OUT_RING(ring, shader->immediates[i].val[0]); 102 OUT_RING(ring, shader->immediates[i].val[1]); 103 OUT_RING(ring, shader->immediates[i].val[2]); 104 OUT_RING(ring, shader->immediates[i].val[3]); 105 base += 4; 106 } 107 } 108} 109 110typedef uint32_t texmask; 111 112static texmask 113emit_texture(struct fd_ringbuffer *ring, struct fd_context *ctx, 114 struct fd_texture_stateobj *tex, unsigned samp_id, texmask emitted) 115{ 116 unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id); 117 static const struct fd2_sampler_stateobj dummy_sampler = {}; 118 static const struct fd2_pipe_sampler_view dummy_view = {}; 119 const struct fd2_sampler_stateobj *sampler; 120 const struct fd2_pipe_sampler_view *view; 121 struct fd_resource *rsc; 122 123 if (emitted & (1 << const_idx)) 124 return 0; 125 126 sampler = tex->samplers[samp_id] ? 127 fd2_sampler_stateobj(tex->samplers[samp_id]) : 128 &dummy_sampler; 129 view = tex->textures[samp_id] ? 130 fd2_pipe_sampler_view(tex->textures[samp_id]) : 131 &dummy_view; 132 133 rsc = view->base.texture ? fd_resource(view->base.texture) : NULL; 134 135 OUT_PKT3(ring, CP_SET_CONSTANT, 7); 136 OUT_RING(ring, 0x00010000 + (0x6 * const_idx)); 137 138 OUT_RING(ring, sampler->tex0 | view->tex0); 139 if (rsc) 140 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 0, 0), view->tex1, 0); 141 else 142 OUT_RING(ring, 0); 143 144 OUT_RING(ring, view->tex2); 145 OUT_RING(ring, sampler->tex3 | view->tex3); 146 OUT_RING(ring, sampler->tex4 | view->tex4); 147 148 if (rsc && rsc->base.last_level) 149 OUT_RELOC(ring, rsc->bo, fd_resource_offset(rsc, 1, 0), view->tex5, 0); 150 else 151 OUT_RING(ring, view->tex5); 152 153 return (1 << const_idx); 154} 155 156static void 157emit_textures(struct fd_ringbuffer *ring, struct fd_context *ctx) 158{ 159 struct fd_texture_stateobj *fragtex = &ctx->tex[PIPE_SHADER_FRAGMENT]; 160 struct fd_texture_stateobj *verttex = &ctx->tex[PIPE_SHADER_VERTEX]; 161 texmask emitted = 0; 162 unsigned i; 163 164 for (i = 0; i < verttex->num_samplers; i++) 165 if (verttex->samplers[i]) 166 emitted |= emit_texture(ring, ctx, verttex, i, emitted); 167 168 for (i = 0; i < fragtex->num_samplers; i++) 169 if (fragtex->samplers[i]) 170 emitted |= emit_texture(ring, ctx, fragtex, i, emitted); 171} 172 173void 174fd2_emit_vertex_bufs(struct fd_ringbuffer *ring, uint32_t val, 175 struct fd2_vertex_buf *vbufs, uint32_t n) 176{ 177 unsigned i; 178 179 OUT_PKT3(ring, CP_SET_CONSTANT, 1 + (2 * n)); 180 OUT_RING(ring, (0x1 << 16) | (val & 0xffff)); 181 for (i = 0; i < n; i++) { 182 struct fd_resource *rsc = fd_resource(vbufs[i].prsc); 183 OUT_RELOC(ring, rsc->bo, vbufs[i].offset, 3, 0); 184 OUT_RING (ring, vbufs[i].size); 185 } 186} 187 188void 189fd2_emit_state_binning(struct fd_context *ctx, const enum fd_dirty_3d_state dirty) 190{ 191 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend); 192 struct fd_ringbuffer *ring = ctx->batch->binning; 193 194 /* subset of fd2_emit_state needed for hw binning on a20x */ 195 196 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE)) 197 fd2_program_emit(ctx, ring, &ctx->prog); 198 199 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) { 200 emit_constants(ring, VS_CONST_BASE * 4, 201 &ctx->constbuf[PIPE_SHADER_VERTEX], 202 (dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL); 203 } 204 205 if (dirty & FD_DIRTY_VIEWPORT) { 206 OUT_PKT3(ring, CP_SET_CONSTANT, 9); 207 OUT_RING(ring, 0x00000184); 208 OUT_RING(ring, fui(ctx->viewport.translate[0])); 209 OUT_RING(ring, fui(ctx->viewport.translate[1])); 210 OUT_RING(ring, fui(ctx->viewport.translate[2])); 211 OUT_RING(ring, fui(0.0f)); 212 OUT_RING(ring, fui(ctx->viewport.scale[0])); 213 OUT_RING(ring, fui(ctx->viewport.scale[1])); 214 OUT_RING(ring, fui(ctx->viewport.scale[2])); 215 OUT_RING(ring, fui(0.0f)); 216 } 217 218 /* not sure why this is needed */ 219 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) { 220 enum pipe_format format = 221 pipe_surface_format(ctx->batch->framebuffer.cbufs[0]); 222 bool has_alpha = util_format_has_alpha(format); 223 224 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 225 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); 226 OUT_RING(ring, blend->rb_blendcontrol_alpha | 227 COND(has_alpha, blend->rb_blendcontrol_rgb) | 228 COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb)); 229 230 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 231 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 232 OUT_RING(ring, blend->rb_colormask); 233 } 234 235 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 236 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL)); 237 OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE); 238} 239 240void 241fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty) 242{ 243 struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend); 244 struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa); 245 struct fd2_shader_stateobj *fp = ctx->prog.fp; 246 struct fd_ringbuffer *ring = ctx->batch->draw; 247 248 /* NOTE: we probably want to eventually refactor this so each state 249 * object handles emitting it's own state.. although the mapping of 250 * state to registers is not always orthogonal, sometimes a single 251 * register contains bitfields coming from multiple state objects, 252 * so not sure the best way to deal with that yet. 253 */ 254 255 if (dirty & FD_DIRTY_SAMPLE_MASK) { 256 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 257 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); 258 OUT_RING(ring, ctx->sample_mask); 259 } 260 261 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF | FD_DIRTY_PROG)) { 262 struct pipe_stencil_ref *sr = &ctx->stencil_ref; 263 uint32_t val = zsa->rb_depthcontrol; 264 265 if (fp->has_kill) 266 val &= ~A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE; 267 268 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 269 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); 270 OUT_RING(ring, val); 271 272 OUT_PKT3(ring, CP_SET_CONSTANT, 4); 273 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF)); 274 OUT_RING(ring, zsa->rb_stencilrefmask_bf | 275 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1])); 276 OUT_RING(ring, zsa->rb_stencilrefmask | 277 A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0])); 278 OUT_RING(ring, zsa->rb_alpha_ref); 279 } 280 281 if (ctx->rasterizer && dirty & FD_DIRTY_RASTERIZER) { 282 struct fd2_rasterizer_stateobj *rasterizer = 283 fd2_rasterizer_stateobj(ctx->rasterizer); 284 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 285 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); 286 OUT_RING(ring, rasterizer->pa_cl_clip_cntl); 287 OUT_RING(ring, rasterizer->pa_su_sc_mode_cntl | 288 A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE); 289 290 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 291 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE)); 292 OUT_RING(ring, rasterizer->pa_su_point_size); 293 OUT_RING(ring, rasterizer->pa_su_point_minmax); 294 OUT_RING(ring, rasterizer->pa_su_line_cntl); 295 OUT_RING(ring, rasterizer->pa_sc_line_stipple); 296 297 OUT_PKT3(ring, CP_SET_CONSTANT, 6); 298 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL)); 299 OUT_RING(ring, rasterizer->pa_su_vtx_cntl); 300 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */ 301 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */ 302 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */ 303 OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */ 304 } 305 306 /* NOTE: scissor enabled bit is part of rasterizer state: */ 307 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { 308 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); 309 310 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 311 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL)); 312 OUT_RING(ring, xy2d(scissor->minx, /* PA_SC_WINDOW_SCISSOR_TL */ 313 scissor->miny)); 314 OUT_RING(ring, xy2d(scissor->maxx, /* PA_SC_WINDOW_SCISSOR_BR */ 315 scissor->maxy)); 316 317 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx); 318 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny); 319 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx); 320 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy); 321 } 322 323 if (dirty & FD_DIRTY_VIEWPORT) { 324 OUT_PKT3(ring, CP_SET_CONSTANT, 7); 325 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE)); 326 OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */ 327 OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */ 328 OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */ 329 OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */ 330 OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */ 331 OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */ 332 333 /* set viewport in C65/C66, for a20x hw binning and fragcoord.z */ 334 OUT_PKT3(ring, CP_SET_CONSTANT, 9); 335 OUT_RING(ring, 0x00000184); 336 337 OUT_RING(ring, fui(ctx->viewport.translate[0])); 338 OUT_RING(ring, fui(ctx->viewport.translate[1])); 339 OUT_RING(ring, fui(ctx->viewport.translate[2])); 340 OUT_RING(ring, fui(0.0f)); 341 342 OUT_RING(ring, fui(ctx->viewport.scale[0])); 343 OUT_RING(ring, fui(ctx->viewport.scale[1])); 344 OUT_RING(ring, fui(ctx->viewport.scale[2])); 345 OUT_RING(ring, fui(0.0f)); 346 } 347 348 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTXSTATE | FD_DIRTY_TEXSTATE)) 349 fd2_program_emit(ctx, ring, &ctx->prog); 350 351 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONST)) { 352 emit_constants(ring, VS_CONST_BASE * 4, 353 &ctx->constbuf[PIPE_SHADER_VERTEX], 354 (dirty & FD_DIRTY_PROG) ? ctx->prog.vp : NULL); 355 emit_constants(ring, PS_CONST_BASE * 4, 356 &ctx->constbuf[PIPE_SHADER_FRAGMENT], 357 (dirty & FD_DIRTY_PROG) ? ctx->prog.fp : NULL); 358 } 359 360 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) { 361 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 362 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL)); 363 OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol); 364 } 365 366 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) { 367 enum pipe_format format = 368 pipe_surface_format(ctx->batch->framebuffer.cbufs[0]); 369 bool has_alpha = util_format_has_alpha(format); 370 371 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 372 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); 373 OUT_RING(ring, blend->rb_blendcontrol_alpha | 374 COND(has_alpha, blend->rb_blendcontrol_rgb) | 375 COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb)); 376 377 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 378 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 379 OUT_RING(ring, blend->rb_colormask); 380 } 381 382 if (dirty & FD_DIRTY_BLEND_COLOR) { 383 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 384 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED)); 385 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[0])); 386 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[1])); 387 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[2])); 388 OUT_RING(ring, float_to_ubyte(ctx->blend_color.color[3])); 389 } 390 391 if (dirty & (FD_DIRTY_TEX | FD_DIRTY_PROG)) 392 emit_textures(ring, ctx); 393} 394 395/* emit per-context initialization: 396 */ 397void 398fd2_emit_restore(struct fd_context *ctx, struct fd_ringbuffer *ring) 399{ 400 if (is_a20x(ctx->screen)) { 401 OUT_PKT0(ring, REG_A2XX_RB_BC_CONTROL, 1); 402 OUT_RING(ring, 403 A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(3) | 404 A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP | 405 A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE | 406 A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(8) | 407 A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(3)); 408 409 /* not sure why this is required */ 410 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 411 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_VIZ_QUERY)); 412 OUT_RING(ring, A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(16)); 413 414 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 415 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); 416 OUT_RING(ring, 0x00000002); 417 418 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 419 OUT_RING(ring, CP_REG(REG_A2XX_VGT_OUT_DEALLOC_CNTL)); 420 OUT_RING(ring, 0x00000002); 421 } else { 422 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 423 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL)); 424 OUT_RING(ring, 0x0000003b); 425 } 426 427 /* enable perfcntrs */ 428 OUT_PKT0(ring, REG_A2XX_CP_PERFMON_CNTL, 1); 429 OUT_RING(ring, COND(fd_mesa_debug & FD_DBG_PERFC, 1)); 430 431 /* note: perfcntrs don't work without the PM_OVERRIDE bit */ 432 OUT_PKT0(ring, REG_A2XX_RBBM_PM_OVERRIDE1, 2); 433 OUT_RING(ring, 0xffffffff); 434 OUT_RING(ring, 0x00000fff); 435 436 OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1); 437 OUT_RING(ring, 0x00000002); 438 439 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); 440 OUT_RING(ring, 0x00007fff); 441 442 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 443 OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST)); 444 OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) | 445 A2XX_SQ_VS_CONST_SIZE(0x100)); 446 447 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 448 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST)); 449 OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) | 450 A2XX_SQ_PS_CONST_SIZE(0xe0)); 451 452 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 453 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX)); 454 OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */ 455 OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */ 456 457 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 458 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET)); 459 OUT_RING(ring, 0x00000000); 460 461 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 462 OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC)); 463 OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY)); 464 465 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 466 OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL)); 467 OUT_RING(ring, 0xffffffff); 468 469 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 470 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG)); 471 OUT_RING(ring, 0x00000000); 472 473 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 474 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL)); 475 OUT_RING(ring, 0x00000000); 476 477 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 478 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET)); 479 OUT_RING(ring, 0x00000000); 480 481 // XXX we change this dynamically for draw/clear.. vs gmem<->mem.. 482 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 483 OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL)); 484 OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH)); 485 486 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 487 OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS)); 488 OUT_RING(ring, 0x88888888); 489 490 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 491 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK)); 492 OUT_RING(ring, 0xffffffff); 493 494 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 495 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO)); 496 OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) | 497 A2XX_RB_COPY_DEST_INFO_WRITE_RED | 498 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN | 499 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE | 500 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA); 501 502 OUT_PKT3(ring, CP_SET_CONSTANT, 3); 503 OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0)); 504 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */ 505 OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */ 506 507 OUT_PKT3(ring, CP_SET_DRAW_INIT_FLAGS, 1); 508 OUT_RING(ring, 0x00000000); 509 510 OUT_PKT3(ring, CP_WAIT_REG_EQ, 4); 511 OUT_RING(ring, 0x000005d0); 512 OUT_RING(ring, 0x00000000); 513 OUT_RING(ring, 0x5f601000); 514 OUT_RING(ring, 0x00000001); 515 516 OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1); 517 OUT_RING(ring, 0x00000180); 518 519 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); 520 OUT_RING(ring, 0x00000300); 521 522 OUT_PKT3(ring, CP_SET_SHADER_BASES, 1); 523 OUT_RING(ring, 0x80000180); 524 525 /* not sure what this form of CP_SET_CONSTANT is.. */ 526 OUT_PKT3(ring, CP_SET_CONSTANT, 13); 527 OUT_RING(ring, 0x00000000); 528 OUT_RING(ring, 0x00000000); 529 OUT_RING(ring, 0x00000000); 530 OUT_RING(ring, 0x00000000); 531 OUT_RING(ring, 0x00000000); 532 OUT_RING(ring, 0x469c4000); 533 OUT_RING(ring, 0x3f800000); 534 OUT_RING(ring, 0x3f000000); 535 OUT_RING(ring, 0x00000000); 536 OUT_RING(ring, 0x40000000); 537 OUT_RING(ring, 0x3f400000); 538 OUT_RING(ring, 0x3ec00000); 539 OUT_RING(ring, 0x3e800000); 540 541 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 542 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); 543 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED | 544 A2XX_RB_COLOR_MASK_WRITE_GREEN | 545 A2XX_RB_COLOR_MASK_WRITE_BLUE | 546 A2XX_RB_COLOR_MASK_WRITE_ALPHA); 547 548 OUT_PKT3(ring, CP_SET_CONSTANT, 5); 549 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED)); 550 OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */ 551 OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */ 552 OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */ 553 OUT_RING(ring, 0x000000ff); /* RB_BLEND_ALPHA */ 554 555 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 556 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL)); 557 OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT | 558 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA | 559 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA | 560 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA | 561 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA | 562 A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA | 563 A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA); 564} 565 566static void 567fd2_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target) 568{ 569 __OUT_IB(ring, false, target); 570} 571 572void 573fd2_emit_init(struct pipe_context *pctx) 574{ 575 struct fd_context *ctx = fd_context(pctx); 576 ctx->emit_ib = fd2_emit_ib; 577} 578