1/* 2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28#include "util/u_string.h" 29#include "util/u_memory.h" 30#include "util/u_prim.h" 31 32#include "freedreno_state.h" 33#include "freedreno_resource.h" 34 35#include "fd5_draw.h" 36#include "fd5_context.h" 37#include "fd5_emit.h" 38#include "fd5_program.h" 39#include "fd5_format.h" 40#include "fd5_zsa.h" 41 42 43static void 44draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring, 45 struct fd5_emit *emit, unsigned index_offset) 46{ 47 const struct pipe_draw_info *info = emit->info; 48 enum pc_di_primtype primtype = ctx->primtypes[info->mode]; 49 50 fd5_emit_state(ctx, ring, emit); 51 52 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE)) 53 fd5_emit_vertex_bufs(ring, emit); 54 55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2); 56 OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */ 57 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */ 58 59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1); 60 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */ 61 info->restart_index : 0xffffffff); 62 63 fd5_emit_render_cntl(ctx, false, emit->binning_pass); 64 fd5_draw_emit(ctx->batch, ring, primtype, 65 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, 66 info, index_offset); 67} 68 69/* fixup dirty shader state in case some "unrelated" (from the state- 70 * tracker's perspective) state change causes us to switch to a 71 * different variant. 72 */ 73static void 74fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key) 75{ 76 struct fd5_context *fd5_ctx = fd5_context(ctx); 77 struct ir3_shader_key *last_key = &fd5_ctx->last_key; 78 79 if (!ir3_shader_key_equal(last_key, key)) { 80 if (ir3_shader_key_changes_fs(last_key, key)) { 81 ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG; 82 ctx->dirty |= FD_DIRTY_PROG; 83 } 84 85 if (ir3_shader_key_changes_vs(last_key, key)) { 86 ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG; 87 ctx->dirty |= FD_DIRTY_PROG; 88 } 89 90 fd5_ctx->last_key = *key; 91 } 92} 93 94static bool 95fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info, 96 unsigned index_offset) 97{ 98 struct fd5_context *fd5_ctx = fd5_context(ctx); 99 struct fd5_emit emit = { 100 .debug = &ctx->debug, 101 .vtx = &ctx->vtx, 102 .prog = &ctx->prog, 103 .info = info, 104 .key = { 105 .color_two_side = ctx->rasterizer->light_twoside, 106 .vclamp_color = ctx->rasterizer->clamp_vertex_color, 107 .fclamp_color = ctx->rasterizer->clamp_fragment_color, 108 .rasterflat = ctx->rasterizer->flatshade, 109 .ucp_enables = ctx->rasterizer->clip_plane_enable, 110 .has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate || 111 fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb), 112 .vsaturate_s = fd5_ctx->vsaturate_s, 113 .vsaturate_t = fd5_ctx->vsaturate_t, 114 .vsaturate_r = fd5_ctx->vsaturate_r, 115 .fsaturate_s = fd5_ctx->fsaturate_s, 116 .fsaturate_t = fd5_ctx->fsaturate_t, 117 .fsaturate_r = fd5_ctx->fsaturate_r, 118 .vastc_srgb = fd5_ctx->vastc_srgb, 119 .fastc_srgb = fd5_ctx->fastc_srgb, 120 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples, 121 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples, 122 }, 123 .rasterflat = ctx->rasterizer->flatshade, 124 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable, 125 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode, 126 }; 127 128 fixup_shader_state(ctx, &emit.key); 129 130 unsigned dirty = ctx->dirty; 131 const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit); 132 const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit); 133 134 /* do regular pass first, since that is more likely to fail compiling: */ 135 136 if (!vp || !fp) 137 return false; 138 139 ctx->stats.vs_regs += ir3_shader_halfregs(vp); 140 ctx->stats.fs_regs += ir3_shader_halfregs(fp); 141 142 /* figure out whether we need to disable LRZ write for binning 143 * pass using draw pass's fp: 144 */ 145 emit.no_lrz_write = fp->writes_pos || fp->no_earlyz; 146 147 emit.binning_pass = false; 148 emit.dirty = dirty; 149 150 draw_impl(ctx, ctx->batch->draw, &emit, index_offset); 151 152 /* and now binning pass: */ 153 emit.binning_pass = true; 154 emit.dirty = dirty & ~(FD_DIRTY_BLEND); 155 emit.vp = NULL; /* we changed key so need to refetch vp */ 156 emit.fp = NULL; 157 draw_impl(ctx, ctx->batch->binning, &emit, index_offset); 158 159 if (emit.streamout_mask) { 160 struct fd_ringbuffer *ring = ctx->batch->draw; 161 162 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) { 163 if (emit.streamout_mask & (1 << i)) { 164 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 165 OUT_RING(ring, FLUSH_SO_0 + i); 166 } 167 } 168 } 169 170 fd_context_all_clean(ctx); 171 172 return true; 173} 174 175static bool is_z32(enum pipe_format format) 176{ 177 switch (format) { 178 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 179 case PIPE_FORMAT_Z32_UNORM: 180 case PIPE_FORMAT_Z32_FLOAT: 181 return true; 182 default: 183 return false; 184 } 185} 186 187static void 188fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) 189{ 190 struct fd_ringbuffer *ring; 191 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth); 192 193 // TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth 194 // splitting both clear and lrz clear out into their own rb's. And 195 // just throw away any draws prior to clear. (Anything not fullscreen 196 // clear, just fallback to generic path that treats it as a normal 197 // draw 198 199 if (!batch->lrz_clear) { 200 batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0); 201 } 202 203 ring = batch->lrz_clear; 204 205 OUT_WFI5(ring); 206 207 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); 208 OUT_RING(ring, 0x10000000); 209 210 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1); 211 OUT_RING(ring, 0x20fffff); 212 213 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1); 214 OUT_RING(ring, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) | 215 COND(zsbuf->base.nr_samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE)); 216 217 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1); 218 OUT_RING(ring, 0x00000000); 219 220 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); 221 OUT_RING(ring, 0x00000181); 222 223 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1); 224 OUT_RING(ring, 0x00000000); 225 226 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5); 227 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) | 228 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) | 229 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX)); 230 OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2)); 231 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz))); 232 OUT_RELOCW(ring, zsbuf->lrz, 0x1000, 0, 0); 233 234 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1); 235 OUT_RING(ring, 0x00000000); 236 237 OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1); 238 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE)); 239 240 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); 241 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0)); 242 243 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); 244 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | 245 A5XX_RB_CLEAR_CNTL_MASK(0xf)); 246 247 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1); 248 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */ 249 250 OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2); 251 OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) | 252 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height)); 253 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE 254 255 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); 256 OUT_RING(ring, A5XX_RB_CNTL_BYPASS); 257 258 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2); 259 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | 260 A5XX_RB_RESOLVE_CNTL_1_Y(0)); 261 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) | 262 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1)); 263 264 fd5_emit_blit(batch->ctx, ring); 265} 266 267static bool 268fd5_clear(struct fd_context *ctx, unsigned buffers, 269 const union pipe_color_union *color, double depth, unsigned stencil) 270{ 271 struct fd_ringbuffer *ring = ctx->batch->draw; 272 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer; 273 274 if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) && 275 is_z32(pfb->zsbuf->format)) 276 return false; 277 278 fd5_emit_render_cntl(ctx, true, false); 279 280 if (buffers & PIPE_CLEAR_COLOR) { 281 for (int i = 0; i < pfb->nr_cbufs; i++) { 282 union util_color uc = {0}; 283 284 if (!pfb->cbufs[i]) 285 continue; 286 287 if (!(buffers & (PIPE_CLEAR_COLOR0 << i))) 288 continue; 289 290 enum pipe_format pfmt = pfb->cbufs[i]->format; 291 292 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP?? 293 union pipe_color_union swapped; 294 switch (fd5_pipe2swap(pfmt)) { 295 case WZYX: 296 swapped.ui[0] = color->ui[0]; 297 swapped.ui[1] = color->ui[1]; 298 swapped.ui[2] = color->ui[2]; 299 swapped.ui[3] = color->ui[3]; 300 break; 301 case WXYZ: 302 swapped.ui[2] = color->ui[0]; 303 swapped.ui[1] = color->ui[1]; 304 swapped.ui[0] = color->ui[2]; 305 swapped.ui[3] = color->ui[3]; 306 break; 307 case ZYXW: 308 swapped.ui[3] = color->ui[0]; 309 swapped.ui[0] = color->ui[1]; 310 swapped.ui[1] = color->ui[2]; 311 swapped.ui[2] = color->ui[3]; 312 break; 313 case XYZW: 314 swapped.ui[3] = color->ui[0]; 315 swapped.ui[2] = color->ui[1]; 316 swapped.ui[1] = color->ui[2]; 317 swapped.ui[0] = color->ui[3]; 318 break; 319 } 320 321 if (util_format_is_pure_uint(pfmt)) { 322 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1); 323 } else if (util_format_is_pure_sint(pfmt)) { 324 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1); 325 } else { 326 util_pack_color(swapped.f, pfmt, &uc); 327 } 328 329 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); 330 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i)); 331 332 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); 333 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | 334 A5XX_RB_CLEAR_CNTL_MASK(0xf)); 335 336 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4); 337 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */ 338 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */ 339 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */ 340 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */ 341 342 fd5_emit_blit(ctx, ring); 343 } 344 } 345 346 if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) { 347 uint32_t clear = 348 util_pack_z_stencil(pfb->zsbuf->format, depth, stencil); 349 uint32_t mask = 0; 350 351 if (buffers & PIPE_CLEAR_DEPTH) 352 mask |= 0x1; 353 354 if (buffers & PIPE_CLEAR_STENCIL) 355 mask |= 0x2; 356 357 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1); 358 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS)); 359 360 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); 361 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | 362 A5XX_RB_CLEAR_CNTL_MASK(mask)); 363 364 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1); 365 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */ 366 367 fd5_emit_blit(ctx, ring); 368 369 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) { 370 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture); 371 if (zsbuf->lrz) { 372 zsbuf->lrz_valid = true; 373 fd5_clear_lrz(ctx->batch, zsbuf, depth); 374 } 375 } 376 } 377 378 /* disable fast clear to not interfere w/ gmem->mem, etc.. */ 379 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1); 380 OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */ 381 382 return true; 383} 384 385void 386fd5_draw_init(struct pipe_context *pctx) 387{ 388 struct fd_context *ctx = fd_context(pctx); 389 ctx->draw_vbo = fd5_draw_vbo; 390 ctx->clear = fd5_clear; 391} 392