1/* 2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include "pipe/p_state.h" 28 29#include "freedreno_resource.h" 30#include "fd5_image.h" 31#include "fd5_format.h" 32#include "fd5_texture.h" 33 34static enum a4xx_state_block texsb[] = { 35 [PIPE_SHADER_COMPUTE] = SB4_CS_TEX, 36 [PIPE_SHADER_FRAGMENT] = SB4_FS_TEX, 37}; 38 39static enum a4xx_state_block imgsb[] = { 40 [PIPE_SHADER_COMPUTE] = SB4_CS_SSBO, 41 [PIPE_SHADER_FRAGMENT] = SB4_SSBO, 42}; 43 44struct fd5_image { 45 enum pipe_format pfmt; 46 enum a5xx_tex_fmt fmt; 47 enum a5xx_tex_fetchsize fetchsize; 48 enum a5xx_tex_type type; 49 bool srgb; 50 uint32_t cpp; 51 uint32_t width; 52 uint32_t height; 53 uint32_t depth; 54 uint32_t pitch; 55 uint32_t array_pitch; 56 struct fd_bo *bo; 57 uint32_t offset; 58}; 59 60static void translate_image(struct fd5_image *img, struct pipe_image_view *pimg) 61{ 62 enum pipe_format format = pimg->format; 63 struct pipe_resource *prsc = pimg->resource; 64 struct fd_resource *rsc = fd_resource(prsc); 65 unsigned lvl; 66 67 if (!pimg->resource) { 68 memset(img, 0, sizeof(*img)); 69 return; 70 } 71 72 img->pfmt = format; 73 img->fmt = fd5_pipe2tex(format); 74 img->fetchsize = fd5_pipe2fetchsize(format); 75 img->type = fd5_tex_type(prsc->target); 76 img->srgb = util_format_is_srgb(format); 77 img->cpp = rsc->cpp; 78 img->bo = rsc->bo; 79 80 if (prsc->target == PIPE_BUFFER) { 81 lvl = 0; 82 img->offset = pimg->u.buf.offset; 83 img->pitch = pimg->u.buf.size; 84 } else { 85 lvl = pimg->u.tex.level; 86 img->offset = fd_resource_offset(rsc, lvl, pimg->u.tex.first_layer); 87 img->pitch = rsc->slices[lvl].pitch * rsc->cpp; 88 } 89 90 img->width = u_minify(prsc->width0, lvl); 91 img->height = u_minify(prsc->height0, lvl); 92 93 unsigned layers = pimg->u.tex.last_layer - pimg->u.tex.first_layer + 1; 94 95 switch (prsc->target) { 96 case PIPE_TEXTURE_RECT: 97 case PIPE_TEXTURE_1D: 98 case PIPE_TEXTURE_2D: 99 img->array_pitch = rsc->layer_size; 100 img->depth = 1; 101 break; 102 case PIPE_TEXTURE_1D_ARRAY: 103 case PIPE_TEXTURE_2D_ARRAY: 104 img->array_pitch = rsc->layer_size; 105 img->depth = layers; 106 break; 107 case PIPE_TEXTURE_CUBE: 108 case PIPE_TEXTURE_CUBE_ARRAY: 109 img->array_pitch = rsc->layer_size; 110 img->depth = layers; 111 break; 112 case PIPE_TEXTURE_3D: 113 img->array_pitch = rsc->slices[lvl].size0; 114 img->depth = u_minify(prsc->depth0, lvl); 115 break; 116 default: 117 img->array_pitch = 0; 118 img->depth = 0; 119 break; 120 } 121} 122 123static void emit_image_tex(struct fd_ringbuffer *ring, unsigned slot, 124 struct fd5_image *img, enum pipe_shader_type shader) 125{ 126 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 12); 127 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) | 128 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 129 CP_LOAD_STATE4_0_STATE_BLOCK(texsb[shader]) | 130 CP_LOAD_STATE4_0_NUM_UNIT(1)); 131 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) | 132 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 133 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 134 135 OUT_RING(ring, A5XX_TEX_CONST_0_FMT(img->fmt) | 136 fd5_tex_swiz(img->pfmt, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, 137 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W) | 138 COND(img->srgb, A5XX_TEX_CONST_0_SRGB)); 139 OUT_RING(ring, A5XX_TEX_CONST_1_WIDTH(img->width) | 140 A5XX_TEX_CONST_1_HEIGHT(img->height)); 141 OUT_RING(ring, A5XX_TEX_CONST_2_FETCHSIZE(img->fetchsize) | 142 A5XX_TEX_CONST_2_TYPE(img->type) | 143 A5XX_TEX_CONST_2_PITCH(img->pitch)); 144 OUT_RING(ring, A5XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch)); 145 if (img->bo) { 146 OUT_RELOC(ring, img->bo, img->offset, 147 (uint64_t)A5XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0); 148 } else { 149 OUT_RING(ring, 0x00000000); 150 OUT_RING(ring, A5XX_TEX_CONST_5_DEPTH(img->depth)); 151 } 152 OUT_RING(ring, 0x00000000); 153 OUT_RING(ring, 0x00000000); 154 OUT_RING(ring, 0x00000000); 155 OUT_RING(ring, 0x00000000); 156 OUT_RING(ring, 0x00000000); 157 OUT_RING(ring, 0x00000000); 158} 159 160static void emit_image_ssbo(struct fd_ringbuffer *ring, unsigned slot, 161 struct fd5_image *img, enum pipe_shader_type shader) 162{ 163 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2); 164 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) | 165 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 166 CP_LOAD_STATE4_0_STATE_BLOCK(imgsb[shader]) | 167 CP_LOAD_STATE4_0_NUM_UNIT(1)); 168 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) | 169 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 170 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 171 OUT_RING(ring, A5XX_SSBO_1_0_FMT(img->fmt) | 172 A5XX_SSBO_1_0_WIDTH(img->width)); 173 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(img->height) | 174 A5XX_SSBO_1_1_DEPTH(img->depth)); 175 176 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2); 177 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) | 178 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) | 179 CP_LOAD_STATE4_0_STATE_BLOCK(imgsb[shader]) | 180 CP_LOAD_STATE4_0_NUM_UNIT(1)); 181 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) | 182 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0)); 183 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0)); 184 if (img->bo) { 185 OUT_RELOCW(ring, img->bo, img->offset, 0, 0); 186 } else { 187 OUT_RING(ring, 0x00000000); 188 OUT_RING(ring, 0x00000000); 189 } 190} 191 192/* Emit required "SSBO" and sampler state. The sampler state is used by the 193 * hw for imageLoad(), and "SSBO" state for imageStore(). Returns max sampler 194 * used. 195 */ 196void 197fd5_emit_images(struct fd_context *ctx, struct fd_ringbuffer *ring, 198 enum pipe_shader_type shader, const struct ir3_shader_variant *v) 199{ 200 struct fd_shaderimg_stateobj *so = &ctx->shaderimg[shader]; 201 unsigned enabled_mask = so->enabled_mask; 202 const struct ir3_ibo_mapping *m = &v->image_mapping; 203 204 while (enabled_mask) { 205 unsigned index = u_bit_scan(&enabled_mask); 206 struct fd5_image img; 207 208 translate_image(&img, &so->si[index]); 209 210 emit_image_tex(ring, m->image_to_tex[index] + m->tex_base, &img, shader); 211 emit_image_ssbo(ring, m->image_to_ibo[index], &img, shader); 212 } 213} 214