1/*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 *    Rob Clark <robclark@freedesktop.org>
26 */
27
28#ifndef FD6_EMIT_H
29#define FD6_EMIT_H
30
31#include "pipe/p_context.h"
32
33#include "freedreno_context.h"
34#include "fd6_context.h"
35#include "fd6_format.h"
36#include "fd6_program.h"
37#include "ir3_gallium.h"
38
39struct fd_ringbuffer;
40
41/* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
42 * packet, the emit tracks a collection of however many state_group's that
43 * need to be emit'd.
44 */
45enum fd6_state_id {
46	FD6_GROUP_PROG,
47	FD6_GROUP_PROG_BINNING,
48	FD6_GROUP_LRZ,
49	FD6_GROUP_LRZ_BINNING,
50	FD6_GROUP_VBO,
51	FD6_GROUP_VBO_BINNING,
52	FD6_GROUP_VS_CONST,
53	FD6_GROUP_FS_CONST,
54	FD6_GROUP_VS_TEX,
55	FD6_GROUP_FS_TEX,
56	FD6_GROUP_IBO,
57	FD6_GROUP_RASTERIZER,
58	FD6_GROUP_ZSA,
59};
60
61struct fd6_state_group {
62	struct fd_ringbuffer *stateobj;
63	enum fd6_state_id group_id;
64	uint8_t enable_mask;
65};
66
67/* grouped together emit-state for prog/vertex/state emit: */
68struct fd6_emit {
69	struct fd_context *ctx;
70	const struct fd_vertex_state *vtx;
71	const struct pipe_draw_info *info;
72	struct ir3_cache_key key;
73	enum fd_dirty_3d_state dirty;
74
75	uint32_t sprite_coord_enable;  /* bitmask */
76	bool sprite_coord_mode;
77	bool rasterflat;
78	bool no_decode_srgb;
79
80	/* in binning pass, we don't have real frag shader, so we
81	 * don't know if real draw disqualifies lrz write.  So just
82	 * figure that out up-front and stash it in the emit.
83	 */
84	bool no_lrz_write;
85
86	/* cached to avoid repeated lookups: */
87	const struct fd6_program_state *prog;
88
89	struct ir3_shader_variant *bs;
90	struct ir3_shader_variant *vs;
91	struct ir3_shader_variant *fs;
92
93	unsigned streamout_mask;
94
95	struct fd6_state_group groups[32];
96	unsigned num_groups;
97};
98
99static inline const struct fd6_program_state *
100fd6_emit_get_prog(struct fd6_emit *emit)
101{
102	if (!emit->prog) {
103		struct fd6_context *fd6_ctx = fd6_context(emit->ctx);
104		struct ir3_program_state *s =
105				ir3_cache_lookup(fd6_ctx->shader_cache, &emit->key, &emit->ctx->debug);
106		emit->prog = fd6_program_state(s);
107	}
108	return emit->prog;
109}
110
111static inline void
112fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
113		enum fd6_state_id group_id, unsigned enable_mask)
114{
115	debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
116	struct fd6_state_group *g = &emit->groups[emit->num_groups++];
117	g->stateobj = fd_ringbuffer_ref(stateobj);
118	g->group_id = group_id;
119	g->enable_mask = enable_mask;
120}
121
122static inline unsigned
123fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
124		enum vgt_event_type evt, bool timestamp)
125{
126	unsigned seqno = 0;
127
128	fd_reset_wfi(batch);
129
130	OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
131	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
132	if (timestamp) {
133		struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
134		seqno = ++fd6_ctx->seqno;
135		OUT_RELOCW(ring, fd6_ctx->blit_mem, 0, 0, 0);  /* ADDR_LO/HI */
136		OUT_RING(ring, seqno);
137	}
138
139	return seqno;
140}
141
142static inline void
143fd6_cache_inv(struct fd_batch *batch, struct fd_ringbuffer *ring)
144{
145	fd6_event_write(batch, ring, 0x31, false);
146}
147
148static inline void
149fd6_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
150{
151	struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
152	unsigned seqno;
153
154	seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
155
156	OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
157	OUT_RING(ring, 0x00000013);
158	OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
159	OUT_RING(ring, seqno);
160	OUT_RING(ring, 0xffffffff);
161	OUT_RING(ring, 0x00000010);
162
163	seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
164
165	OUT_PKT7(ring, CP_UNK_A6XX_14, 4);
166	OUT_RING(ring, 0x00000000);
167	OUT_RELOC(ring, fd6_ctx->blit_mem, 0, 0, 0);
168	OUT_RING(ring, seqno);
169}
170
171static inline void
172fd6_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
173{
174	emit_marker6(ring, 7);
175	fd6_event_write(batch, ring, BLIT, false);
176	emit_marker6(ring, 7);
177}
178
179static inline void
180fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
181{
182	OUT_PKT7(ring, CP_EVENT_WRITE, 1);
183	OUT_RING(ring, LRZ_FLUSH);
184}
185
186static inline enum a6xx_state_block
187fd6_stage2shadersb(gl_shader_stage type)
188{
189	switch (type) {
190	case MESA_SHADER_VERTEX:
191		return SB6_VS_SHADER;
192	case MESA_SHADER_FRAGMENT:
193		return SB6_FS_SHADER;
194	case MESA_SHADER_COMPUTE:
195	case MESA_SHADER_KERNEL:
196		return SB6_CS_SHADER;
197	default:
198		unreachable("bad shader type");
199		return ~0;
200	}
201}
202
203bool fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
204		enum pipe_shader_type type, struct fd_texture_stateobj *tex,
205		unsigned bcolor_offset,
206		const struct ir3_shader_variant *v, struct fd_context *ctx);
207
208void fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit);
209
210void fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
211		struct ir3_shader_variant *cp);
212
213void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
214
215void fd6_emit_init(struct pipe_context *pctx);
216
217static inline void
218fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
219{
220	emit_marker6(ring, 6);
221	__OUT_IB5(ring, target);
222	emit_marker6(ring, 6);
223}
224
225#define WRITE(reg, val) do {					\
226		OUT_PKT4(ring, reg, 1);					\
227		OUT_RING(ring, val);					\
228	} while (0)
229
230
231#endif /* FD6_EMIT_H */
232