1848b8605Smrg/*
2848b8605Smrg * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3848b8605Smrg *
4848b8605Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5848b8605Smrg * copy of this software and associated documentation files (the "Software"),
6848b8605Smrg * to deal in the Software without restriction, including without limitation
7848b8605Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8848b8605Smrg * and/or sell copies of the Software, and to permit persons to whom the
9848b8605Smrg * Software is furnished to do so, subject to the following conditions:
10848b8605Smrg *
11848b8605Smrg * The above copyright notice and this permission notice (including the next
12848b8605Smrg * paragraph) shall be included in all copies or substantial portions of the
13848b8605Smrg * Software.
14848b8605Smrg *
15848b8605Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16848b8605Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17848b8605Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18848b8605Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19848b8605Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20848b8605Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21848b8605Smrg * SOFTWARE.
22848b8605Smrg *
23848b8605Smrg * Authors:
24848b8605Smrg *    Rob Clark <robclark@freedesktop.org>
25848b8605Smrg */
26848b8605Smrg
27848b8605Smrg#include "pipe/p_state.h"
28b8e80941Smrg#include "util/u_dual_blend.h"
29848b8605Smrg#include "util/u_string.h"
30848b8605Smrg#include "util/u_memory.h"
31848b8605Smrg#include "util/u_helpers.h"
32848b8605Smrg
33848b8605Smrg#include "freedreno_state.h"
34848b8605Smrg#include "freedreno_context.h"
35848b8605Smrg#include "freedreno_resource.h"
36848b8605Smrg#include "freedreno_texture.h"
37848b8605Smrg#include "freedreno_gmem.h"
38b8e80941Smrg#include "freedreno_query_hw.h"
39848b8605Smrg#include "freedreno_util.h"
40848b8605Smrg
41848b8605Smrg/* All the generic state handling.. In case of CSO's that are specific
42848b8605Smrg * to the GPU version, when the bind and the delete are common they can
43848b8605Smrg * go in here.
44848b8605Smrg */
45848b8605Smrg
46848b8605Smrgstatic void
47848b8605Smrgfd_set_blend_color(struct pipe_context *pctx,
48848b8605Smrg		const struct pipe_blend_color *blend_color)
49848b8605Smrg{
50848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
51848b8605Smrg	ctx->blend_color = *blend_color;
52848b8605Smrg	ctx->dirty |= FD_DIRTY_BLEND_COLOR;
53848b8605Smrg}
54848b8605Smrg
55848b8605Smrgstatic void
56848b8605Smrgfd_set_stencil_ref(struct pipe_context *pctx,
57848b8605Smrg		const struct pipe_stencil_ref *stencil_ref)
58848b8605Smrg{
59848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
60848b8605Smrg	ctx->stencil_ref =* stencil_ref;
61848b8605Smrg	ctx->dirty |= FD_DIRTY_STENCIL_REF;
62848b8605Smrg}
63848b8605Smrg
64848b8605Smrgstatic void
65848b8605Smrgfd_set_clip_state(struct pipe_context *pctx,
66848b8605Smrg		const struct pipe_clip_state *clip)
67848b8605Smrg{
68b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
69b8e80941Smrg	ctx->ucp = *clip;
70b8e80941Smrg	ctx->dirty |= FD_DIRTY_UCP;
71848b8605Smrg}
72848b8605Smrg
73848b8605Smrgstatic void
74848b8605Smrgfd_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
75848b8605Smrg{
76848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
77848b8605Smrg	ctx->sample_mask = (uint16_t)sample_mask;
78848b8605Smrg	ctx->dirty |= FD_DIRTY_SAMPLE_MASK;
79848b8605Smrg}
80848b8605Smrg
81b8e80941Smrgstatic void
82b8e80941Smrgfd_set_min_samples(struct pipe_context *pctx, unsigned min_samples)
83b8e80941Smrg{
84b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
85b8e80941Smrg	ctx->min_samples = min_samples;
86b8e80941Smrg	ctx->dirty |= FD_DIRTY_MIN_SAMPLES;
87b8e80941Smrg}
88b8e80941Smrg
89848b8605Smrg/* notes from calim on #dri-devel:
90848b8605Smrg * index==0 will be non-UBO (ie. glUniformXYZ()) all packed together padded
91848b8605Smrg * out to vec4's
92848b8605Smrg * I should be able to consider that I own the user_ptr until the next
93848b8605Smrg * set_constant_buffer() call, at which point I don't really care about the
94848b8605Smrg * previous values.
95848b8605Smrg * index>0 will be UBO's.. well, I'll worry about that later
96848b8605Smrg */
97848b8605Smrgstatic void
98b8e80941Smrgfd_set_constant_buffer(struct pipe_context *pctx,
99b8e80941Smrg		enum pipe_shader_type shader, uint index,
100b8e80941Smrg		const struct pipe_constant_buffer *cb)
101848b8605Smrg{
102848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
103848b8605Smrg	struct fd_constbuf_stateobj *so = &ctx->constbuf[shader];
104848b8605Smrg
105b8e80941Smrg	util_copy_constant_buffer(&so->cb[index], cb);
106b8e80941Smrg
107848b8605Smrg	/* Note that the state tracker can unbind constant buffers by
108848b8605Smrg	 * passing NULL here.
109848b8605Smrg	 */
110848b8605Smrg	if (unlikely(!cb)) {
111848b8605Smrg		so->enabled_mask &= ~(1 << index);
112848b8605Smrg		return;
113848b8605Smrg	}
114848b8605Smrg
115848b8605Smrg	so->enabled_mask |= 1 << index;
116b8e80941Smrg	ctx->dirty_shader[shader] |= FD_DIRTY_SHADER_CONST;
117b8e80941Smrg	ctx->dirty |= FD_DIRTY_CONST;
118b8e80941Smrg}
119b8e80941Smrg
120b8e80941Smrgstatic void
121b8e80941Smrgfd_set_shader_buffers(struct pipe_context *pctx,
122b8e80941Smrg		enum pipe_shader_type shader,
123b8e80941Smrg		unsigned start, unsigned count,
124b8e80941Smrg		const struct pipe_shader_buffer *buffers,
125b8e80941Smrg		unsigned writable_bitmask)
126b8e80941Smrg{
127b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
128b8e80941Smrg	struct fd_shaderbuf_stateobj *so = &ctx->shaderbuf[shader];
129b8e80941Smrg	unsigned mask = 0;
130b8e80941Smrg
131b8e80941Smrg	if (buffers) {
132b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
133b8e80941Smrg			unsigned n = i + start;
134b8e80941Smrg			struct pipe_shader_buffer *buf = &so->sb[n];
135b8e80941Smrg
136b8e80941Smrg			if ((buf->buffer == buffers[i].buffer) &&
137b8e80941Smrg					(buf->buffer_offset == buffers[i].buffer_offset) &&
138b8e80941Smrg					(buf->buffer_size == buffers[i].buffer_size))
139b8e80941Smrg				continue;
140b8e80941Smrg
141b8e80941Smrg			mask |= BIT(n);
142b8e80941Smrg
143b8e80941Smrg			buf->buffer_offset = buffers[i].buffer_offset;
144b8e80941Smrg			buf->buffer_size = buffers[i].buffer_size;
145b8e80941Smrg			pipe_resource_reference(&buf->buffer, buffers[i].buffer);
146b8e80941Smrg
147b8e80941Smrg			if (buf->buffer)
148b8e80941Smrg				so->enabled_mask |= BIT(n);
149b8e80941Smrg			else
150b8e80941Smrg				so->enabled_mask &= ~BIT(n);
151b8e80941Smrg		}
152b8e80941Smrg	} else {
153b8e80941Smrg		mask = (BIT(count) - 1) << start;
154b8e80941Smrg
155b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
156b8e80941Smrg			unsigned n = i + start;
157b8e80941Smrg			struct pipe_shader_buffer *buf = &so->sb[n];
158b8e80941Smrg
159b8e80941Smrg			pipe_resource_reference(&buf->buffer, NULL);
160b8e80941Smrg		}
161b8e80941Smrg
162b8e80941Smrg		so->enabled_mask &= ~mask;
163b8e80941Smrg	}
164b8e80941Smrg
165b8e80941Smrg	ctx->dirty_shader[shader] |= FD_DIRTY_SHADER_SSBO;
166b8e80941Smrg}
167b8e80941Smrg
168b8e80941Smrgstatic void
169b8e80941Smrgfd_set_shader_images(struct pipe_context *pctx,
170b8e80941Smrg		enum pipe_shader_type shader,
171b8e80941Smrg		unsigned start, unsigned count,
172b8e80941Smrg		const struct pipe_image_view *images)
173b8e80941Smrg{
174b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
175b8e80941Smrg	struct fd_shaderimg_stateobj *so = &ctx->shaderimg[shader];
176b8e80941Smrg
177b8e80941Smrg	unsigned mask = 0;
178b8e80941Smrg
179b8e80941Smrg	if (images) {
180b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
181b8e80941Smrg			unsigned n = i + start;
182b8e80941Smrg			struct pipe_image_view *buf = &so->si[n];
183b8e80941Smrg
184b8e80941Smrg			if ((buf->resource == images[i].resource) &&
185b8e80941Smrg					(buf->format == images[i].format) &&
186b8e80941Smrg					(buf->access == images[i].access) &&
187b8e80941Smrg					!memcmp(&buf->u, &images[i].u, sizeof(buf->u)))
188b8e80941Smrg				continue;
189b8e80941Smrg
190b8e80941Smrg			mask |= BIT(n);
191b8e80941Smrg			util_copy_image_view(buf, &images[i]);
192b8e80941Smrg
193b8e80941Smrg			if (buf->resource)
194b8e80941Smrg				so->enabled_mask |= BIT(n);
195b8e80941Smrg			else
196b8e80941Smrg				so->enabled_mask &= ~BIT(n);
197b8e80941Smrg		}
198b8e80941Smrg	} else {
199b8e80941Smrg		mask = (BIT(count) - 1) << start;
200b8e80941Smrg
201b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
202b8e80941Smrg			unsigned n = i + start;
203b8e80941Smrg			struct pipe_image_view *img = &so->si[n];
204b8e80941Smrg
205b8e80941Smrg			pipe_resource_reference(&img->resource, NULL);
206b8e80941Smrg		}
207b8e80941Smrg
208b8e80941Smrg		so->enabled_mask &= ~mask;
209b8e80941Smrg	}
210b8e80941Smrg
211b8e80941Smrg	ctx->dirty_shader[shader] |= FD_DIRTY_SHADER_IMAGE;
212848b8605Smrg}
213848b8605Smrg
214848b8605Smrgstatic void
215848b8605Smrgfd_set_framebuffer_state(struct pipe_context *pctx,
216848b8605Smrg		const struct pipe_framebuffer_state *framebuffer)
217848b8605Smrg{
218848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
219b8e80941Smrg	struct pipe_framebuffer_state *cso;
220b8e80941Smrg
221b8e80941Smrg	DBG("%ux%u, %u layers, %u samples",
222b8e80941Smrg		framebuffer->width, framebuffer->height,
223b8e80941Smrg		framebuffer->layers, framebuffer->samples);
224848b8605Smrg
225b8e80941Smrg	cso = &ctx->framebuffer;
226848b8605Smrg
227b8e80941Smrg	if (util_framebuffer_state_equal(cso, framebuffer))
228b8e80941Smrg		return;
229848b8605Smrg
230848b8605Smrg	util_copy_framebuffer_state(cso, framebuffer);
231848b8605Smrg
232b8e80941Smrg	cso->samples = util_framebuffer_get_num_samples(cso);
233b8e80941Smrg
234b8e80941Smrg	if (ctx->screen->reorder) {
235b8e80941Smrg		struct fd_batch *old_batch = NULL;
236b8e80941Smrg
237b8e80941Smrg		fd_batch_reference(&old_batch, ctx->batch);
238b8e80941Smrg
239b8e80941Smrg		if (likely(old_batch))
240b8e80941Smrg			fd_batch_set_stage(old_batch, FD_STAGE_NULL);
241b8e80941Smrg
242b8e80941Smrg		fd_batch_reference(&ctx->batch, NULL);
243b8e80941Smrg		fd_context_all_dirty(ctx);
244b8e80941Smrg
245b8e80941Smrg		if (old_batch && old_batch->blit && !old_batch->back_blit) {
246b8e80941Smrg			/* for blits, there is not really much point in hanging on
247b8e80941Smrg			 * to the uncommitted batch (ie. you probably don't blit
248b8e80941Smrg			 * multiple times to the same surface), so we might as
249b8e80941Smrg			 * well go ahead and flush this one:
250b8e80941Smrg			 */
251b8e80941Smrg			fd_batch_flush(old_batch, false, false);
252b8e80941Smrg		}
253b8e80941Smrg
254b8e80941Smrg		fd_batch_reference(&old_batch, NULL);
255b8e80941Smrg	} else {
256b8e80941Smrg		DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx->batch->needs_flush,
257b8e80941Smrg				framebuffer->cbufs[0], framebuffer->zsbuf);
258b8e80941Smrg		fd_batch_flush(ctx->batch, false, false);
259b8e80941Smrg		util_copy_framebuffer_state(&ctx->batch->framebuffer, cso);
260b8e80941Smrg	}
261848b8605Smrg
262848b8605Smrg	ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
263848b8605Smrg
264848b8605Smrg	ctx->disabled_scissor.minx = 0;
265848b8605Smrg	ctx->disabled_scissor.miny = 0;
266848b8605Smrg	ctx->disabled_scissor.maxx = cso->width;
267848b8605Smrg	ctx->disabled_scissor.maxy = cso->height;
268848b8605Smrg
269848b8605Smrg	ctx->dirty |= FD_DIRTY_SCISSOR;
270848b8605Smrg}
271848b8605Smrg
272848b8605Smrgstatic void
273848b8605Smrgfd_set_polygon_stipple(struct pipe_context *pctx,
274848b8605Smrg		const struct pipe_poly_stipple *stipple)
275848b8605Smrg{
276848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
277848b8605Smrg	ctx->stipple = *stipple;
278848b8605Smrg	ctx->dirty |= FD_DIRTY_STIPPLE;
279848b8605Smrg}
280848b8605Smrg
281848b8605Smrgstatic void
282848b8605Smrgfd_set_scissor_states(struct pipe_context *pctx,
283848b8605Smrg		unsigned start_slot,
284848b8605Smrg		unsigned num_scissors,
285848b8605Smrg		const struct pipe_scissor_state *scissor)
286848b8605Smrg{
287848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
288848b8605Smrg
289848b8605Smrg	ctx->scissor = *scissor;
290848b8605Smrg	ctx->dirty |= FD_DIRTY_SCISSOR;
291848b8605Smrg}
292848b8605Smrg
293848b8605Smrgstatic void
294848b8605Smrgfd_set_viewport_states(struct pipe_context *pctx,
295848b8605Smrg		unsigned start_slot,
296848b8605Smrg		unsigned num_viewports,
297848b8605Smrg		const struct pipe_viewport_state *viewport)
298848b8605Smrg{
299848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
300b8e80941Smrg	struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
301b8e80941Smrg	float minx, miny, maxx, maxy;
302b8e80941Smrg
303848b8605Smrg	ctx->viewport = *viewport;
304b8e80941Smrg
305b8e80941Smrg	/* see si_get_scissor_from_viewport(): */
306b8e80941Smrg
307b8e80941Smrg	/* Convert (-1, -1) and (1, 1) from clip space into window space. */
308b8e80941Smrg	minx = -viewport->scale[0] + viewport->translate[0];
309b8e80941Smrg	miny = -viewport->scale[1] + viewport->translate[1];
310b8e80941Smrg	maxx = viewport->scale[0] + viewport->translate[0];
311b8e80941Smrg	maxy = viewport->scale[1] + viewport->translate[1];
312b8e80941Smrg
313b8e80941Smrg	/* Handle inverted viewports. */
314b8e80941Smrg	if (minx > maxx) {
315b8e80941Smrg		swap(minx, maxx);
316b8e80941Smrg	}
317b8e80941Smrg	if (miny > maxy) {
318b8e80941Smrg		swap(miny, maxy);
319b8e80941Smrg	}
320b8e80941Smrg
321b8e80941Smrg	debug_assert(miny >= 0);
322b8e80941Smrg	debug_assert(maxy >= 0);
323b8e80941Smrg
324b8e80941Smrg	/* Convert to integer and round up the max bounds. */
325b8e80941Smrg	scissor->minx = minx;
326b8e80941Smrg	scissor->miny = miny;
327b8e80941Smrg	scissor->maxx = ceilf(maxx);
328b8e80941Smrg	scissor->maxy = ceilf(maxy);
329b8e80941Smrg
330848b8605Smrg	ctx->dirty |= FD_DIRTY_VIEWPORT;
331848b8605Smrg}
332848b8605Smrg
333848b8605Smrgstatic void
334848b8605Smrgfd_set_vertex_buffers(struct pipe_context *pctx,
335848b8605Smrg		unsigned start_slot, unsigned count,
336848b8605Smrg		const struct pipe_vertex_buffer *vb)
337848b8605Smrg{
338848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
339848b8605Smrg	struct fd_vertexbuf_stateobj *so = &ctx->vtx.vertexbuf;
340848b8605Smrg	int i;
341848b8605Smrg
342848b8605Smrg	/* on a2xx, pitch is encoded in the vtx fetch instruction, so
343848b8605Smrg	 * we need to mark VTXSTATE as dirty as well to trigger patching
344848b8605Smrg	 * and re-emitting the vtx shader:
345848b8605Smrg	 */
346b8e80941Smrg	if (ctx->screen->gpu_id < 300) {
347b8e80941Smrg		for (i = 0; i < count; i++) {
348b8e80941Smrg			bool new_enabled = vb && vb[i].buffer.resource;
349b8e80941Smrg			bool old_enabled = so->vb[i].buffer.resource != NULL;
350b8e80941Smrg			uint32_t new_stride = vb ? vb[i].stride : 0;
351b8e80941Smrg			uint32_t old_stride = so->vb[i].stride;
352b8e80941Smrg			if ((new_enabled != old_enabled) || (new_stride != old_stride)) {
353b8e80941Smrg				ctx->dirty |= FD_DIRTY_VTXSTATE;
354b8e80941Smrg				break;
355b8e80941Smrg			}
356848b8605Smrg		}
357848b8605Smrg	}
358848b8605Smrg
359848b8605Smrg	util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count);
360848b8605Smrg	so->count = util_last_bit(so->enabled_mask);
361848b8605Smrg
362848b8605Smrg	ctx->dirty |= FD_DIRTY_VTXBUF;
363848b8605Smrg}
364848b8605Smrg
365848b8605Smrgstatic void
366848b8605Smrgfd_blend_state_bind(struct pipe_context *pctx, void *hwcso)
367848b8605Smrg{
368848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
369b8e80941Smrg	struct pipe_blend_state *cso = hwcso;
370b8e80941Smrg	bool old_is_dual = ctx->blend ?
371b8e80941Smrg		ctx->blend->rt[0].blend_enable && util_blend_state_is_dual(ctx->blend, 0) :
372b8e80941Smrg		false;
373b8e80941Smrg	bool new_is_dual = cso ?
374b8e80941Smrg		cso->rt[0].blend_enable && util_blend_state_is_dual(cso, 0) :
375b8e80941Smrg		false;
376848b8605Smrg	ctx->blend = hwcso;
377848b8605Smrg	ctx->dirty |= FD_DIRTY_BLEND;
378b8e80941Smrg	if (old_is_dual != new_is_dual)
379b8e80941Smrg		ctx->dirty |= FD_DIRTY_BLEND_DUAL;
380848b8605Smrg}
381848b8605Smrg
382848b8605Smrgstatic void
383848b8605Smrgfd_blend_state_delete(struct pipe_context *pctx, void *hwcso)
384848b8605Smrg{
385848b8605Smrg	FREE(hwcso);
386848b8605Smrg}
387848b8605Smrg
388848b8605Smrgstatic void
389848b8605Smrgfd_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
390848b8605Smrg{
391848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
392848b8605Smrg	struct pipe_scissor_state *old_scissor = fd_context_get_scissor(ctx);
393848b8605Smrg
394848b8605Smrg	ctx->rasterizer = hwcso;
395848b8605Smrg	ctx->dirty |= FD_DIRTY_RASTERIZER;
396848b8605Smrg
397848b8605Smrg	/* if scissor enable bit changed we need to mark scissor
398848b8605Smrg	 * state as dirty as well:
399848b8605Smrg	 * NOTE: we can do a shallow compare, since we only care
400848b8605Smrg	 * if it changed to/from &ctx->disable_scissor
401848b8605Smrg	 */
402848b8605Smrg	if (old_scissor != fd_context_get_scissor(ctx))
403848b8605Smrg		ctx->dirty |= FD_DIRTY_SCISSOR;
404848b8605Smrg}
405848b8605Smrg
406848b8605Smrgstatic void
407848b8605Smrgfd_rasterizer_state_delete(struct pipe_context *pctx, void *hwcso)
408848b8605Smrg{
409848b8605Smrg	FREE(hwcso);
410848b8605Smrg}
411848b8605Smrg
412848b8605Smrgstatic void
413848b8605Smrgfd_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
414848b8605Smrg{
415848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
416848b8605Smrg	ctx->zsa = hwcso;
417848b8605Smrg	ctx->dirty |= FD_DIRTY_ZSA;
418848b8605Smrg}
419848b8605Smrg
420848b8605Smrgstatic void
421848b8605Smrgfd_zsa_state_delete(struct pipe_context *pctx, void *hwcso)
422848b8605Smrg{
423848b8605Smrg	FREE(hwcso);
424848b8605Smrg}
425848b8605Smrg
426848b8605Smrgstatic void *
427848b8605Smrgfd_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
428848b8605Smrg		const struct pipe_vertex_element *elements)
429848b8605Smrg{
430848b8605Smrg	struct fd_vertex_stateobj *so = CALLOC_STRUCT(fd_vertex_stateobj);
431848b8605Smrg
432848b8605Smrg	if (!so)
433848b8605Smrg		return NULL;
434848b8605Smrg
435848b8605Smrg	memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
436848b8605Smrg	so->num_elements = num_elements;
437848b8605Smrg
438848b8605Smrg	return so;
439848b8605Smrg}
440848b8605Smrg
441848b8605Smrgstatic void
442848b8605Smrgfd_vertex_state_delete(struct pipe_context *pctx, void *hwcso)
443848b8605Smrg{
444848b8605Smrg	FREE(hwcso);
445848b8605Smrg}
446848b8605Smrg
447848b8605Smrgstatic void
448848b8605Smrgfd_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
449848b8605Smrg{
450848b8605Smrg	struct fd_context *ctx = fd_context(pctx);
451848b8605Smrg	ctx->vtx.vtx = hwcso;
452848b8605Smrg	ctx->dirty |= FD_DIRTY_VTXSTATE;
453848b8605Smrg}
454848b8605Smrg
455b8e80941Smrgstatic struct pipe_stream_output_target *
456b8e80941Smrgfd_create_stream_output_target(struct pipe_context *pctx,
457b8e80941Smrg		struct pipe_resource *prsc, unsigned buffer_offset,
458b8e80941Smrg		unsigned buffer_size)
459b8e80941Smrg{
460b8e80941Smrg	struct pipe_stream_output_target *target;
461b8e80941Smrg	struct fd_resource *rsc = fd_resource(prsc);
462b8e80941Smrg
463b8e80941Smrg	target = CALLOC_STRUCT(pipe_stream_output_target);
464b8e80941Smrg	if (!target)
465b8e80941Smrg		return NULL;
466b8e80941Smrg
467b8e80941Smrg	pipe_reference_init(&target->reference, 1);
468b8e80941Smrg	pipe_resource_reference(&target->buffer, prsc);
469b8e80941Smrg
470b8e80941Smrg	target->context = pctx;
471b8e80941Smrg	target->buffer_offset = buffer_offset;
472b8e80941Smrg	target->buffer_size = buffer_size;
473b8e80941Smrg
474b8e80941Smrg	assert(rsc->base.target == PIPE_BUFFER);
475b8e80941Smrg	util_range_add(&rsc->valid_buffer_range,
476b8e80941Smrg		buffer_offset, buffer_offset + buffer_size);
477b8e80941Smrg
478b8e80941Smrg	return target;
479b8e80941Smrg}
480b8e80941Smrg
481b8e80941Smrgstatic void
482b8e80941Smrgfd_stream_output_target_destroy(struct pipe_context *pctx,
483b8e80941Smrg		struct pipe_stream_output_target *target)
484b8e80941Smrg{
485b8e80941Smrg	pipe_resource_reference(&target->buffer, NULL);
486b8e80941Smrg	FREE(target);
487b8e80941Smrg}
488b8e80941Smrg
489b8e80941Smrgstatic void
490b8e80941Smrgfd_set_stream_output_targets(struct pipe_context *pctx,
491b8e80941Smrg		unsigned num_targets, struct pipe_stream_output_target **targets,
492b8e80941Smrg		const unsigned *offsets)
493b8e80941Smrg{
494b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
495b8e80941Smrg	struct fd_streamout_stateobj *so = &ctx->streamout;
496b8e80941Smrg	unsigned i;
497b8e80941Smrg
498b8e80941Smrg	debug_assert(num_targets <= ARRAY_SIZE(so->targets));
499b8e80941Smrg
500b8e80941Smrg	for (i = 0; i < num_targets; i++) {
501b8e80941Smrg		boolean changed = targets[i] != so->targets[i];
502b8e80941Smrg		boolean append = (offsets[i] == (unsigned)-1);
503b8e80941Smrg
504b8e80941Smrg		if (!changed && append)
505b8e80941Smrg			continue;
506b8e80941Smrg
507b8e80941Smrg		if (!append)
508b8e80941Smrg			so->offsets[i] = offsets[i];
509b8e80941Smrg
510b8e80941Smrg		pipe_so_target_reference(&so->targets[i], targets[i]);
511b8e80941Smrg	}
512b8e80941Smrg
513b8e80941Smrg	for (; i < so->num_targets; i++) {
514b8e80941Smrg		pipe_so_target_reference(&so->targets[i], NULL);
515b8e80941Smrg	}
516b8e80941Smrg
517b8e80941Smrg	so->num_targets = num_targets;
518b8e80941Smrg
519b8e80941Smrg	ctx->dirty |= FD_DIRTY_STREAMOUT;
520b8e80941Smrg}
521b8e80941Smrg
522b8e80941Smrgstatic void
523b8e80941Smrgfd_bind_compute_state(struct pipe_context *pctx, void *state)
524b8e80941Smrg{
525b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
526b8e80941Smrg	ctx->compute = state;
527b8e80941Smrg	ctx->dirty_shader[PIPE_SHADER_COMPUTE] |= FD_DIRTY_SHADER_PROG;
528b8e80941Smrg}
529b8e80941Smrg
530b8e80941Smrgstatic void
531b8e80941Smrgfd_set_compute_resources(struct pipe_context *pctx,
532b8e80941Smrg		unsigned start, unsigned count, struct pipe_surface **prscs)
533b8e80941Smrg{
534b8e80941Smrg	// TODO
535b8e80941Smrg}
536b8e80941Smrg
537b8e80941Smrg/* used by clover to bind global objects, returning the bo address
538b8e80941Smrg * via handles[n]
539b8e80941Smrg */
540b8e80941Smrgstatic void
541b8e80941Smrgfd_set_global_binding(struct pipe_context *pctx,
542b8e80941Smrg		unsigned first, unsigned count, struct pipe_resource **prscs,
543b8e80941Smrg		uint32_t **handles)
544b8e80941Smrg{
545b8e80941Smrg	struct fd_context *ctx = fd_context(pctx);
546b8e80941Smrg	struct fd_global_bindings_stateobj *so = &ctx->global_bindings;
547b8e80941Smrg	unsigned mask = 0;
548b8e80941Smrg
549b8e80941Smrg	if (prscs) {
550b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
551b8e80941Smrg			unsigned n = i + first;
552b8e80941Smrg
553b8e80941Smrg			mask |= BIT(n);
554b8e80941Smrg
555b8e80941Smrg			pipe_resource_reference(&so->buf[n], prscs[i]);
556b8e80941Smrg
557b8e80941Smrg			if (so->buf[n]) {
558b8e80941Smrg				struct fd_resource *rsc = fd_resource(so->buf[n]);
559b8e80941Smrg				uint64_t iova = fd_bo_get_iova(rsc->bo);
560b8e80941Smrg				// TODO need to scream if iova > 32b or fix gallium API..
561b8e80941Smrg				*handles[i] += iova;
562b8e80941Smrg			}
563b8e80941Smrg
564b8e80941Smrg			if (prscs[i])
565b8e80941Smrg				so->enabled_mask |= BIT(n);
566b8e80941Smrg			else
567b8e80941Smrg				so->enabled_mask &= ~BIT(n);
568b8e80941Smrg		}
569b8e80941Smrg	} else {
570b8e80941Smrg		mask = (BIT(count) - 1) << first;
571b8e80941Smrg
572b8e80941Smrg		for (unsigned i = 0; i < count; i++) {
573b8e80941Smrg			unsigned n = i + first;
574b8e80941Smrg			if (so->buf[n]) {
575b8e80941Smrg				struct fd_resource *rsc = fd_resource(so->buf[n]);
576b8e80941Smrg				fd_bo_put_iova(rsc->bo);
577b8e80941Smrg			}
578b8e80941Smrg			pipe_resource_reference(&so->buf[n], NULL);
579b8e80941Smrg		}
580b8e80941Smrg
581b8e80941Smrg		so->enabled_mask &= ~mask;
582b8e80941Smrg	}
583b8e80941Smrg
584b8e80941Smrg}
585b8e80941Smrg
586848b8605Smrgvoid
587848b8605Smrgfd_state_init(struct pipe_context *pctx)
588848b8605Smrg{
589848b8605Smrg	pctx->set_blend_color = fd_set_blend_color;
590848b8605Smrg	pctx->set_stencil_ref = fd_set_stencil_ref;
591848b8605Smrg	pctx->set_clip_state = fd_set_clip_state;
592848b8605Smrg	pctx->set_sample_mask = fd_set_sample_mask;
593b8e80941Smrg	pctx->set_min_samples = fd_set_min_samples;
594848b8605Smrg	pctx->set_constant_buffer = fd_set_constant_buffer;
595b8e80941Smrg	pctx->set_shader_buffers = fd_set_shader_buffers;
596b8e80941Smrg	pctx->set_shader_images = fd_set_shader_images;
597848b8605Smrg	pctx->set_framebuffer_state = fd_set_framebuffer_state;
598848b8605Smrg	pctx->set_polygon_stipple = fd_set_polygon_stipple;
599848b8605Smrg	pctx->set_scissor_states = fd_set_scissor_states;
600848b8605Smrg	pctx->set_viewport_states = fd_set_viewport_states;
601848b8605Smrg
602848b8605Smrg	pctx->set_vertex_buffers = fd_set_vertex_buffers;
603848b8605Smrg
604848b8605Smrg	pctx->bind_blend_state = fd_blend_state_bind;
605848b8605Smrg	pctx->delete_blend_state = fd_blend_state_delete;
606848b8605Smrg
607848b8605Smrg	pctx->bind_rasterizer_state = fd_rasterizer_state_bind;
608848b8605Smrg	pctx->delete_rasterizer_state = fd_rasterizer_state_delete;
609848b8605Smrg
610848b8605Smrg	pctx->bind_depth_stencil_alpha_state = fd_zsa_state_bind;
611848b8605Smrg	pctx->delete_depth_stencil_alpha_state = fd_zsa_state_delete;
612848b8605Smrg
613848b8605Smrg	pctx->create_vertex_elements_state = fd_vertex_state_create;
614848b8605Smrg	pctx->delete_vertex_elements_state = fd_vertex_state_delete;
615848b8605Smrg	pctx->bind_vertex_elements_state = fd_vertex_state_bind;
616b8e80941Smrg
617b8e80941Smrg	pctx->create_stream_output_target = fd_create_stream_output_target;
618b8e80941Smrg	pctx->stream_output_target_destroy = fd_stream_output_target_destroy;
619b8e80941Smrg	pctx->set_stream_output_targets = fd_set_stream_output_targets;
620b8e80941Smrg
621b8e80941Smrg	if (has_compute(fd_screen(pctx->screen))) {
622b8e80941Smrg		pctx->bind_compute_state = fd_bind_compute_state;
623b8e80941Smrg		pctx->set_compute_resources = fd_set_compute_resources;
624b8e80941Smrg		pctx->set_global_binding = fd_set_global_binding;
625b8e80941Smrg	}
626848b8605Smrg}
627