1/**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef _RADEON_VCN_DEC_H
29#define _RADEON_VCN_DEC_H
30
31#define RDECODE_PKT_TYPE_S(x)			(((unsigned)(x)	& 0x3) << 30)
32#define RDECODE_PKT_TYPE_G(x)			(((x) >> 30) & 0x3)
33#define RDECODE_PKT_TYPE_C			0x3FFFFFFF
34#define RDECODE_PKT_COUNT_S(x)			(((unsigned)(x) & 0x3FFF) << 16)
35#define RDECODE_PKT_COUNT_G(x)			(((x) >> 16) & 0x3FFF)
36#define RDECODE_PKT_COUNT_C			0xC000FFFF
37#define RDECODE_PKT0_BASE_INDEX_S(x)		(((unsigned)(x)	& 0xFFFF) << 0)
38#define RDECODE_PKT0_BASE_INDEX_G(x)		(((x) >> 0) & 0xFFFF)
39#define RDECODE_PKT0_BASE_INDEX_C		0xFFFF0000
40#define RDECODE_PKT0(index, count)		(RDECODE_PKT_TYPE_S(0) | \
41						RDECODE_PKT0_BASE_INDEX_S(index) | \
42						RDECODE_PKT_COUNT_S(count))
43
44#define RDECODE_PKT2()				(RDECODE_PKT_TYPE_S(2))
45
46#define RDECODE_PKT_REG_J(x)			((unsigned)(x) & 0x3FFFF)
47#define RDECODE_PKT_RES_J(x)			(((unsigned)(x)	& 0x3F) << 18)
48#define RDECODE_PKT_COND_J(x)			(((unsigned)(x)	& 0xF) << 24)
49#define RDECODE_PKT_TYPE_J(x)			(((unsigned)(x)	& 0xF) << 28)
50#define RDECODE_PKTJ(reg, cond, type)		(RDECODE_PKT_REG_J(reg) | \
51						RDECODE_PKT_RES_J(0) | \
52						RDECODE_PKT_COND_J(cond) | \
53						RDECODE_PKT_TYPE_J(type))
54
55#define RDECODE_CMD_MSG_BUFFER				0x00000000
56#define RDECODE_CMD_DPB_BUFFER				0x00000001
57#define RDECODE_CMD_DECODING_TARGET_BUFFER		0x00000002
58#define RDECODE_CMD_FEEDBACK_BUFFER			0x00000003
59#define RDECODE_CMD_PROB_TBL_BUFFER			0x00000004
60#define RDECODE_CMD_SESSION_CONTEXT_BUFFER		0x00000005
61#define RDECODE_CMD_BITSTREAM_BUFFER			0x00000100
62#define RDECODE_CMD_IT_SCALING_TABLE_BUFFER		0x00000204
63#define RDECODE_CMD_CONTEXT_BUFFER			0x00000206
64
65#define RDECODE_MSG_CREATE				0x00000000
66#define RDECODE_MSG_DECODE				0x00000001
67#define RDECODE_MSG_DESTROY				0x00000002
68
69#define RDECODE_CODEC_H264				0x00000000
70#define RDECODE_CODEC_VC1				0x00000001
71#define RDECODE_CODEC_MPEG2_VLD 			0x00000003
72#define RDECODE_CODEC_MPEG4				0x00000004
73#define RDECODE_CODEC_H264_PERF 			0x00000007
74#define RDECODE_CODEC_JPEG				0x00000008
75#define RDECODE_CODEC_H265				0x00000010
76#define RDECODE_CODEC_VP9				0x00000011
77
78#define RDECODE_ARRAY_MODE_LINEAR			0x00000000
79#define RDECODE_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED	0x00000001
80#define RDECODE_ARRAY_MODE_1D_THIN			0x00000002
81#define RDECODE_ARRAY_MODE_2D_THIN			0x00000004
82#define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR	0x00000004
83#define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_TILED	0x00000005
84
85#define RDECODE_H264_PROFILE_BASELINE			0x00000000
86#define RDECODE_H264_PROFILE_MAIN			0x00000001
87#define RDECODE_H264_PROFILE_HIGH			0x00000002
88#define RDECODE_H264_PROFILE_STEREO_HIGH		0x00000003
89#define RDECODE_H264_PROFILE_MVC			0x00000004
90
91#define RDECODE_VC1_PROFILE_SIMPLE			0x00000000
92#define RDECODE_VC1_PROFILE_MAIN			0x00000001
93#define RDECODE_VC1_PROFILE_ADVANCED			0x00000002
94
95#define RDECODE_SW_MODE_LINEAR				0x00000000
96#define RDECODE_256B_S					0x00000001
97#define RDECODE_256B_D					0x00000002
98#define RDECODE_4KB_S					0x00000005
99#define RDECODE_4KB_D					0x00000006
100#define RDECODE_64KB_S					0x00000009
101#define RDECODE_64KB_D					0x0000000A
102#define RDECODE_4KB_S_X 				0x00000015
103#define RDECODE_4KB_D_X 				0x00000016
104#define RDECODE_64KB_S_X				0x00000019
105#define RDECODE_64KB_D_X				0x0000001A
106
107#define RDECODE_MESSAGE_NOT_SUPPORTED			0x00000000
108#define RDECODE_MESSAGE_CREATE				0x00000001
109#define RDECODE_MESSAGE_DECODE				0x00000002
110#define RDECODE_MESSAGE_AVC				0x00000006
111#define RDECODE_MESSAGE_VC1				0x00000007
112#define RDECODE_MESSAGE_MPEG2_VLD			0x0000000A
113#define RDECODE_MESSAGE_MPEG4_ASP_VLD			0x0000000B
114#define RDECODE_MESSAGE_HEVC				0x0000000D
115#define RDECODE_MESSAGE_VP9				0x0000000E
116
117#define RDECODE_FEEDBACK_PROFILING			0x00000001
118
119#define RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT	7
120
121#define NUM_BUFFERS			4
122
123#define RDECODE_VP9_PROBS_DATA_SIZE			2304
124
125#define mmUVD_JPEG_CNTL 				0x0200
126#define mmUVD_JPEG_CNTL_BASE_IDX			1
127#define mmUVD_JPEG_RB_BASE				0x0201
128#define mmUVD_JPEG_RB_BASE_BASE_IDX			1
129#define mmUVD_JPEG_RB_WPTR				0x0202
130#define mmUVD_JPEG_RB_WPTR_BASE_IDX			1
131#define mmUVD_JPEG_RB_RPTR				0x0203
132#define mmUVD_JPEG_RB_RPTR_BASE_IDX			1
133#define mmUVD_JPEG_RB_SIZE				0x0204
134#define mmUVD_JPEG_RB_SIZE_BASE_IDX			1
135#define mmUVD_JPEG_TIER_CNTL2				0x021a
136#define mmUVD_JPEG_TIER_CNTL2_BASE_IDX			1
137#define mmUVD_JPEG_UV_TILING_CTRL			0x021c
138#define mmUVD_JPEG_UV_TILING_CTRL_BASE_IDX		1
139#define mmUVD_JPEG_TILING_CTRL				0x021e
140#define mmUVD_JPEG_TILING_CTRL_BASE_IDX 		1
141#define mmUVD_JPEG_OUTBUF_RPTR				0x0220
142#define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX 		1
143#define mmUVD_JPEG_OUTBUF_WPTR				0x0221
144#define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX 		1
145#define mmUVD_JPEG_PITCH				0x0222
146#define mmUVD_JPEG_PITCH_BASE_IDX			1
147#define mmUVD_JPEG_INT_EN				0x0229
148#define mmUVD_JPEG_INT_EN_BASE_IDX			1
149#define mmUVD_JPEG_UV_PITCH				0x022b
150#define mmUVD_JPEG_UV_PITCH_BASE_IDX			1
151#define mmUVD_JPEG_INDEX				0x023e
152#define mmUVD_JPEG_INDEX_BASE_IDX			1
153#define mmUVD_JPEG_DATA 				0x023f
154#define mmUVD_JPEG_DATA_BASE_IDX			1
155#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH		0x0438
156#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX	1
157#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW		0x0439
158#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX	1
159#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH		0x045a
160#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX	1
161#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW		0x045b
162#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX	1
163#define mmUVD_CTX_INDEX 				0x0528
164#define mmUVD_CTX_INDEX_BASE_IDX			1
165#define mmUVD_CTX_DATA  				0x0529
166#define mmUVD_CTX_DATA_BASE_IDX 			1
167#define mmUVD_SOFT_RESET				0x05a0
168#define mmUVD_SOFT_RESET_BASE_IDX			1
169
170#define UVD_BASE_INST0_SEG0				0x00007800
171#define UVD_BASE_INST0_SEG1				0x00007E00
172#define UVD_BASE_INST0_SEG2				0
173#define UVD_BASE_INST0_SEG3				0
174#define UVD_BASE_INST0_SEG4				0
175
176#define SOC15_REG_ADDR(reg)			(UVD_BASE_INST0_SEG1 + reg)
177
178#define COND0	0
179#define COND1	1
180#define COND2	2
181#define COND3	3
182#define COND4	4
183#define COND5	5
184#define COND6	6
185#define COND7	7
186
187#define TYPE0	0
188#define TYPE1	1
189#define TYPE2	2
190#define TYPE3	3
191#define TYPE4	4
192#define TYPE5	5
193#define TYPE6	6
194#define TYPE7	7
195
196/* VP9 Frame header flags */
197#define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_SHIFT              (13)
198#define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_SHIFT                 (12)
199#define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_SHIFT                (11)
200#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_SHIFT              (10)
201#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_SHIFT           (9)
202#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_SHIFT                (8)
203#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_SHIFT                   (7)
204#define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_SHIFT           (6)
205#define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_SHIFT                  (5)
206#define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_SHIFT                (4)
207#define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_SHIFT                             (3)
208#define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_SHIFT                   (2)
209#define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_SHIFT                             (1)
210#define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_SHIFT                    (0)
211
212#define RDECODE_FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS_MASK                (0x00002000)
213#define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_UPDATE_MASK                   (0x00001000)
214#define RDECODE_FRAME_HDR_INFO_VP9_MODE_REF_DELTA_ENABLED_MASK                  (0x00000800)
215#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_DATA_MASK                (0x00000400)
216#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_TEMPORAL_UPDATE_MASK            (0x00000200)
217#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_UPDATE_MAP_MASK                 (0x00000100)
218#define RDECODE_FRAME_HDR_INFO_VP9_SEGMENTATION_ENABLED_MASK                    (0x00000080)
219#define RDECODE_FRAME_HDR_INFO_VP9_FRAME_PARALLEL_DECODING_MODE_MASK            (0x00000040)
220#define RDECODE_FRAME_HDR_INFO_VP9_REFRESH_FRAME_CONTEXT_MASK                   (0x00000020)
221#define RDECODE_FRAME_HDR_INFO_VP9_ALLOW_HIGH_PRECISION_MV_MASK                 (0x00000010)
222#define RDECODE_FRAME_HDR_INFO_VP9_INTRA_ONLY_MASK                              (0x00000008)
223#define RDECODE_FRAME_HDR_INFO_VP9_ERROR_RESILIENT_MODE_MASK                    (0x00000004)
224#define RDECODE_FRAME_HDR_INFO_VP9_FRAME_TYPE_MASK                              (0x00000002)
225#define RDECODE_FRAME_HDR_INFO_VP9_SHOW_EXISTING_FRAME_MASK                     (0x00000001)
226
227typedef struct rvcn_dec_message_index_s {
228	unsigned int	message_id;
229	unsigned int	offset;
230	unsigned int	size;
231	unsigned int	filled;
232} rvcn_dec_message_index_t;
233
234typedef struct rvcn_dec_message_header_s {
235	unsigned int	header_size;
236	unsigned int	total_size;
237	unsigned int	num_buffers;
238	unsigned int	msg_type;
239	unsigned int	stream_handle;
240	unsigned int	status_report_feedback_number;
241
242	rvcn_dec_message_index_t	index[1];
243} rvcn_dec_message_header_t;
244
245typedef struct rvcn_dec_message_create_s {
246	unsigned int	stream_type;
247	unsigned int	session_flags;
248	unsigned int	width_in_samples;
249	unsigned int	height_in_samples;
250} rvcn_dec_message_create_t;
251
252typedef struct rvcn_dec_message_decode_s {
253	unsigned int	stream_type;
254	unsigned int	decode_flags;
255	unsigned int	width_in_samples;
256	unsigned int	height_in_samples;
257
258	unsigned int	bsd_size;
259	unsigned int	dpb_size;
260	unsigned int	dt_size;
261	unsigned int	sct_size;
262	unsigned int	sc_coeff_size;
263	unsigned int	hw_ctxt_size;
264	unsigned int	sw_ctxt_size;
265	unsigned int	pic_param_size;
266	unsigned int	mb_cntl_size;
267	unsigned int	reserved0[4];
268	unsigned int	decode_buffer_flags;
269
270	unsigned int	db_pitch;
271	unsigned int	db_aligned_height;
272	unsigned int	db_tiling_mode;
273	unsigned int	db_swizzle_mode;
274	unsigned int	db_array_mode;
275	unsigned int	db_field_mode;
276	unsigned int	db_surf_tile_config;
277
278	unsigned int	dt_pitch;
279	unsigned int	dt_uv_pitch;
280	unsigned int	dt_tiling_mode;
281	unsigned int	dt_swizzle_mode;
282	unsigned int	dt_array_mode;
283	unsigned int	dt_field_mode;
284	unsigned int	dt_out_format;
285	unsigned int	dt_surf_tile_config;
286	unsigned int	dt_uv_surf_tile_config;
287	unsigned int	dt_luma_top_offset;
288	unsigned int	dt_luma_bottom_offset;
289	unsigned int	dt_chroma_top_offset;
290	unsigned int	dt_chroma_bottom_offset;
291	unsigned int	dt_chromaV_top_offset;
292	unsigned int	dt_chromaV_bottom_offset;
293
294	unsigned char	dpbRefArraySlice[16];
295	unsigned char	dpbCurArraySlice;
296	unsigned char	dpbReserved[3];
297} rvcn_dec_message_decode_t;
298
299typedef struct {
300	unsigned short	viewOrderIndex;
301	unsigned short	viewId;
302	unsigned short	numOfAnchorRefsInL0;
303	unsigned short	viewIdOfAnchorRefsInL0[15];
304	unsigned short	numOfAnchorRefsInL1;
305	unsigned short	viewIdOfAnchorRefsInL1[15];
306	unsigned short	numOfNonAnchorRefsInL0;
307	unsigned short	viewIdOfNonAnchorRefsInL0[15];
308	unsigned short	numOfNonAnchorRefsInL1;
309	unsigned short	viewIdOfNonAnchorRefsInL1[15];
310} radeon_mvcElement_t;
311
312typedef struct rvcn_dec_message_avc_s {
313	unsigned int	profile;
314	unsigned int	level;
315
316	unsigned int	sps_info_flags;
317	unsigned int	pps_info_flags;
318	unsigned char	chroma_format;
319	unsigned char	bit_depth_luma_minus8;
320	unsigned char	bit_depth_chroma_minus8;
321	unsigned char	log2_max_frame_num_minus4;
322
323	unsigned char	pic_order_cnt_type;
324	unsigned char	log2_max_pic_order_cnt_lsb_minus4;
325	unsigned char	num_ref_frames;
326	unsigned char	reserved_8bit;
327
328	signed char	pic_init_qp_minus26;
329	signed char	pic_init_qs_minus26;
330	signed char	chroma_qp_index_offset;
331	signed char	second_chroma_qp_index_offset;
332
333	unsigned char	num_slice_groups_minus1;
334	unsigned char	slice_group_map_type;
335	unsigned char	num_ref_idx_l0_active_minus1;
336	unsigned char	num_ref_idx_l1_active_minus1;
337
338	unsigned short	slice_group_change_rate_minus1;
339	unsigned short	reserved_16bit_1;
340
341	unsigned char	scaling_list_4x4[6][16];
342	unsigned char	scaling_list_8x8[2][64];
343
344	unsigned int	frame_num;
345	unsigned int	frame_num_list[16];
346	int		curr_field_order_cnt_list[2];
347	int		field_order_cnt_list[16][2];
348
349	unsigned int	decoded_pic_idx;
350	unsigned int	curr_pic_ref_frame_num;
351	unsigned char	ref_frame_list[16];
352
353	unsigned int	reserved[122];
354
355	struct {
356		unsigned int	numViews;
357		unsigned int	viewId0;
358		radeon_mvcElement_t	mvcElements[1];
359	} mvc;
360
361} rvcn_dec_message_avc_t;
362
363typedef struct rvcn_dec_message_vc1_s {
364	unsigned int	profile;
365	unsigned int	level;
366	unsigned int	sps_info_flags;
367	unsigned int	pps_info_flags;
368	unsigned int	pic_structure;
369	unsigned int	chroma_format;
370	unsigned short	decoded_pic_idx;
371	unsigned short	deblocked_pic_idx;
372	unsigned short	forward_ref_idx;
373	unsigned short	backward_ref_idx;
374	unsigned int	cached_frame_flag;
375} rvcn_dec_message_vc1_t;
376
377typedef struct rvcn_dec_message_mpeg2_vld_s {
378	unsigned int	decoded_pic_idx;
379	unsigned int	forward_ref_pic_idx;
380	unsigned int	backward_ref_pic_idx;
381
382	unsigned char	load_intra_quantiser_matrix;
383	unsigned char	load_nonintra_quantiser_matrix;
384	unsigned char	reserved_quantiser_alignement[2];
385	unsigned char	intra_quantiser_matrix[64];
386	unsigned char	nonintra_quantiser_matrix[64];
387
388	unsigned char	profile_and_level_indication;
389	unsigned char	chroma_format;
390
391	unsigned char	picture_coding_type;
392
393	unsigned char	reserved_1;
394
395	unsigned char	f_code[2][2];
396	unsigned char	intra_dc_precision;
397	unsigned char	pic_structure;
398	unsigned char	top_field_first;
399	unsigned char	frame_pred_frame_dct;
400	unsigned char	concealment_motion_vectors;
401	unsigned char	q_scale_type;
402	unsigned char	intra_vlc_format;
403	unsigned char	alternate_scan;
404} rvcn_dec_message_mpeg2_vld_t;
405
406typedef struct rvcn_dec_message_mpeg4_asp_vld_s {
407	unsigned int	decoded_pic_idx;
408	unsigned int	forward_ref_pic_idx;
409	unsigned int	backward_ref_pic_idx;
410
411	unsigned int	variant_type;
412	unsigned char	profile_and_level_indication;
413
414	unsigned char	video_object_layer_verid;
415	unsigned char	video_object_layer_shape;
416
417	unsigned char	reserved_1;
418
419	unsigned short	video_object_layer_width;
420	unsigned short	video_object_layer_height;
421
422	unsigned short	vop_time_increment_resolution;
423
424	unsigned short	reserved_2;
425
426	struct {
427		unsigned int	short_video_header :1;
428		unsigned int	obmc_disable :1;
429		unsigned int	interlaced :1;
430		unsigned int	load_intra_quant_mat :1;
431		unsigned int	load_nonintra_quant_mat :1;
432		unsigned int	quarter_sample :1;
433		unsigned int	complexity_estimation_disable :1;
434		unsigned int	resync_marker_disable :1;
435		unsigned int	data_partitioned :1;
436		unsigned int	reversible_vlc :1;
437		unsigned int	newpred_enable :1;
438		unsigned int	reduced_resolution_vop_enable :1;
439		unsigned int	scalability :1;
440		unsigned int	is_object_layer_identifier :1;
441		unsigned int	fixed_vop_rate :1;
442		unsigned int	newpred_segment_type :1;
443		unsigned int	reserved_bits :16;
444	};
445
446	unsigned char	quant_type;
447	unsigned char	reserved_3[3];
448	unsigned char	intra_quant_mat[64];
449	unsigned char	nonintra_quant_mat[64];
450
451	struct {
452		unsigned char	sprite_enable;
453
454		unsigned char	reserved_4[3];
455
456		unsigned short	sprite_width;
457		unsigned short	sprite_height;
458		short		sprite_left_coordinate;
459		short		sprite_top_coordinate;
460
461		unsigned char	no_of_sprite_warping_points;
462		unsigned char	sprite_warping_accuracy;
463		unsigned char	sprite_brightness_change;
464		unsigned char	low_latency_sprite_enable;
465	} sprite_config;
466
467	struct {
468		struct {
469			unsigned int	check_skip :1;
470			unsigned int	switch_rounding :1;
471			unsigned int	t311 :1;
472			unsigned int	reserved_bits :29;
473		};
474
475		unsigned char	vol_mode;
476
477		unsigned char	reserved_5[3];
478	} divx_311_config;
479
480	struct {
481		unsigned char	vop_data_present;
482		unsigned char	vop_coding_type;
483		unsigned char	vop_quant;
484		unsigned char	vop_coded;
485		unsigned char	vop_rounding_type;
486		unsigned char	intra_dc_vlc_thr;
487		unsigned char	top_field_first;
488		unsigned char	alternate_vertical_scan_flag;
489		unsigned char	vop_fcode_forward;
490		unsigned char	vop_fcode_backward;
491		unsigned int	TRB[2];
492		unsigned int	TRD[2];
493	} vop;
494
495} rvcn_dec_message_mpeg4_asp_vld_t;
496
497typedef struct rvcn_dec_message_hevc_s {
498	unsigned int	sps_info_flags;
499	unsigned int	pps_info_flags;
500	unsigned char	chroma_format;
501	unsigned char	bit_depth_luma_minus8;
502	unsigned char	bit_depth_chroma_minus8;
503	unsigned char	log2_max_pic_order_cnt_lsb_minus4;
504
505	unsigned char	sps_max_dec_pic_buffering_minus1;
506	unsigned char	log2_min_luma_coding_block_size_minus3;
507	unsigned char	log2_diff_max_min_luma_coding_block_size;
508	unsigned char	log2_min_transform_block_size_minus2;
509
510	unsigned char	log2_diff_max_min_transform_block_size;
511	unsigned char	max_transform_hierarchy_depth_inter;
512	unsigned char	max_transform_hierarchy_depth_intra;
513	unsigned char	pcm_sample_bit_depth_luma_minus1;
514
515	unsigned char	pcm_sample_bit_depth_chroma_minus1;
516	unsigned char	log2_min_pcm_luma_coding_block_size_minus3;
517	unsigned char	log2_diff_max_min_pcm_luma_coding_block_size;
518	unsigned char	num_extra_slice_header_bits;
519
520	unsigned char	num_short_term_ref_pic_sets;
521	unsigned char	num_long_term_ref_pic_sps;
522	unsigned char	num_ref_idx_l0_default_active_minus1;
523	unsigned char	num_ref_idx_l1_default_active_minus1;
524
525	signed char	pps_cb_qp_offset;
526	signed char	pps_cr_qp_offset;
527	signed char	pps_beta_offset_div2;
528	signed char	pps_tc_offset_div2;
529
530	unsigned char	diff_cu_qp_delta_depth;
531	unsigned char	num_tile_columns_minus1;
532	unsigned char	num_tile_rows_minus1;
533	unsigned char	log2_parallel_merge_level_minus2;
534
535	unsigned short	column_width_minus1[19];
536	unsigned short	row_height_minus1[21];
537
538	signed char	init_qp_minus26;
539	unsigned char	num_delta_pocs_ref_rps_idx;
540	unsigned char	curr_idx;
541	unsigned char	reserved[1];
542	int		curr_poc;
543	unsigned char	ref_pic_list[16];
544	int		poc_list[16];
545	unsigned char	ref_pic_set_st_curr_before[8];
546	unsigned char	ref_pic_set_st_curr_after[8];
547	unsigned char	ref_pic_set_lt_curr[8];
548
549	unsigned char	ucScalingListDCCoefSizeID2[6];
550	unsigned char	ucScalingListDCCoefSizeID3[2];
551
552	unsigned char	highestTid;
553	unsigned char	isNonRef;
554
555	unsigned char	p010_mode;
556	unsigned char	msb_mode;
557	unsigned char	luma_10to8;
558	unsigned char	chroma_10to8;
559
560	unsigned char	hevc_reserved[2];
561
562	unsigned char	direct_reflist[2][15];
563} rvcn_dec_message_hevc_t;
564
565typedef struct rvcn_dec_message_vp9_s {
566	unsigned int	frame_header_flags;
567
568	unsigned char	frame_context_idx;
569	unsigned char	reset_frame_context;
570
571	unsigned char	curr_pic_idx;
572	unsigned char	interp_filter;
573
574	unsigned char	filter_level;
575	unsigned char	sharpness_level;
576	unsigned char	lf_adj_level[8][4][2];
577	unsigned char	base_qindex;
578	signed char	y_dc_delta_q;
579	signed char	uv_ac_delta_q;
580	signed char	uv_dc_delta_q;
581
582	unsigned char	log2_tile_cols;
583	unsigned char	log2_tile_rows;
584	unsigned char	tx_mode;
585	unsigned char	reference_mode;
586	unsigned char	chroma_format;
587
588	unsigned char	ref_frame_map[8];
589
590	unsigned char	frame_refs[3];
591	unsigned char	ref_frame_sign_bias[3];
592	unsigned char	frame_to_show;
593	unsigned char	bit_depth_luma_minus8;
594	unsigned char	bit_depth_chroma_minus8;
595
596	unsigned char	p010_mode;
597	unsigned char	msb_mode;
598	unsigned char	luma_10to8;
599	unsigned char	chroma_10to8;
600
601	unsigned int	vp9_frame_size;
602	unsigned int	compressed_header_size;
603	unsigned int	uncompressed_header_size;
604} rvcn_dec_message_vp9_t;
605
606typedef struct rvcn_dec_feature_index_s {
607	unsigned int	feature_id;
608	unsigned int	offset;
609	unsigned int	size;
610	unsigned int	filled;
611} rvcn_dec_feature_index_t;
612
613typedef struct rvcn_dec_feedback_header_s {
614	unsigned int	header_size;
615	unsigned int	total_size;
616	unsigned int	num_buffers;
617	unsigned int	status_report_feedback_number;
618	unsigned int	status;
619	unsigned int	value;
620	unsigned int	errorBits;
621	rvcn_dec_feature_index_t	index[1];
622} rvcn_dec_feedback_header_t;
623
624typedef struct rvcn_dec_feedback_profiling_s {
625	unsigned int	size;
626
627	unsigned int	decodingTime;
628	unsigned int	decodePlusOverhead;
629	unsigned int	masterTimerHits;
630	unsigned int	uvdLBSIREWaitCount;
631
632	unsigned int	avgMPCMemLatency;
633	unsigned int	maxMPCMemLatency;
634	unsigned int	uvdMPCLumaHits;
635	unsigned int	uvdMPCLumaHitPend;
636	unsigned int	uvdMPCLumaSearch;
637	unsigned int	uvdMPCChromaHits;
638	unsigned int	uvdMPCChromaHitPend;
639	unsigned int	uvdMPCChromaSearch;
640
641	unsigned int	uvdLMIPerfCountLo;
642	unsigned int	uvdLMIPerfCountHi;
643	unsigned int	uvdLMIAvgLatCntrEnvHit;
644	unsigned int	uvdLMILatCntr;
645
646	unsigned int	frameCRC0;
647	unsigned int	frameCRC1;
648	unsigned int	frameCRC2;
649	unsigned int	frameCRC3;
650
651	unsigned int	uvdLMIPerfMonCtrl;
652	unsigned int	uvdLMILatCtrl;
653	unsigned int	uvdMPCCntl;
654	unsigned int	reserved0[4];
655	unsigned int	decoderID;
656	unsigned int	codec;
657
658	unsigned int	dmaHwCrc32Enable;
659	unsigned int	dmaHwCrc32Value;
660	unsigned int	dmaHwCrc32Value2;
661} rvcn_dec_feedback_profiling_t;
662
663typedef struct rvcn_dec_vp9_nmv_ctx_mask_s {
664    unsigned short	classes_mask[2];
665    unsigned short	bits_mask[2];
666    unsigned char	joints_mask;
667    unsigned char	sign_mask[2];
668    unsigned char	class0_mask[2];
669    unsigned char	class0_fp_mask[2];
670    unsigned char	fp_mask[2];
671    unsigned char	class0_hp_mask[2];
672    unsigned char	hp_mask[2];
673    unsigned char	reserve[11];
674} rvcn_dec_vp9_nmv_ctx_mask_t;
675
676typedef struct rvcn_dec_vp9_nmv_component_s{
677    unsigned char	sign;
678    unsigned char	classes[10];
679    unsigned char	class0[1];
680    unsigned char	bits[10];
681    unsigned char	class0_fp[2][3];
682    unsigned char	fp[3];
683    unsigned char	class0_hp;
684    unsigned char	hp;
685} rvcn_dec_vp9_nmv_component_t;
686
687typedef struct rvcn_dec_vp9_probs_s {
688    rvcn_dec_vp9_nmv_ctx_mask_t	nmvc_mask;
689    unsigned char	coef_probs[4][2][2][6][6][3];
690    unsigned char	y_mode_prob[4][9];
691    unsigned char	uv_mode_prob[10][9];
692    unsigned char	single_ref_prob[5][2];
693    unsigned char	switchable_interp_prob[4][2];
694    unsigned char	partition_prob[16][3];
695    unsigned char	inter_mode_probs[7][3];
696    unsigned char	mbskip_probs[3];
697    unsigned char	intra_inter_prob[4];
698    unsigned char	comp_inter_prob[5];
699    unsigned char	comp_ref_prob[5];
700    unsigned char	tx_probs_32x32[2][3];
701    unsigned char	tx_probs_16x16[2][2];
702    unsigned char	tx_probs_8x8[2][1];
703    unsigned char	mv_joints[3];
704    rvcn_dec_vp9_nmv_component_t mv_comps[2];
705} rvcn_dec_vp9_probs_t;
706
707typedef struct rvcn_dec_vp9_probs_segment_s {
708    union {
709        rvcn_dec_vp9_probs_t	probs;
710        unsigned char	probs_data[RDECODE_VP9_PROBS_DATA_SIZE];
711    };
712
713    union {
714        struct {
715            unsigned int	feature_data[8];
716            unsigned char	tree_probs[7];
717            unsigned char	pred_probs[3];
718            unsigned char	abs_delta;
719            unsigned char	feature_mask[8];
720        } seg;
721        unsigned char	segment_data[256];
722    };
723} rvcn_dec_vp9_probs_segment_t;
724
725struct jpeg_params {
726	unsigned			bsd_size;
727	unsigned			dt_pitch;
728	unsigned			dt_uv_pitch;
729	unsigned			dt_luma_top_offset;
730	unsigned			dt_chroma_top_offset;
731};
732
733struct radeon_decoder {
734	struct pipe_video_codec		base;
735
736	unsigned			stream_handle;
737	unsigned			stream_type;
738	unsigned			frame_number;
739
740	struct pipe_screen		*screen;
741	struct radeon_winsys		*ws;
742	struct radeon_cmdbuf		*cs;
743
744	void				*msg;
745	uint32_t			*fb;
746	uint8_t				*it;
747	uint8_t				*probs;
748	void				*bs_ptr;
749
750	struct rvid_buffer		msg_fb_it_probs_buffers[NUM_BUFFERS];
751	struct rvid_buffer		bs_buffers[NUM_BUFFERS];
752	struct rvid_buffer		dpb;
753	struct rvid_buffer		ctx;
754	struct rvid_buffer		sessionctx;
755
756	unsigned			bs_size;
757	unsigned			cur_buffer;
758	void				*render_pic_list[16];
759	bool				show_frame;
760	unsigned			ref_idx;
761	struct jpeg_params		jpg;
762	void (*send_cmd)(struct radeon_decoder *dec,
763			 struct pipe_video_buffer *target,
764			 struct pipe_picture_desc *picture);
765};
766
767void send_cmd_dec(struct radeon_decoder *dec,
768		  struct pipe_video_buffer *target,
769		  struct pipe_picture_desc *picture);
770
771void send_cmd_jpeg(struct radeon_decoder *dec,
772		  struct pipe_video_buffer *target,
773		  struct pipe_picture_desc *picture);
774
775struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
776		const struct pipe_video_codec *templat);
777
778#endif
779