1/********************************************************** 2 * Copyright 1998-2017 VMware, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 **********************************************************/ 25 26/* 27 * svga3d_devcaps.h -- 28 * 29 * SVGA 3d caps definitions 30 */ 31 32#ifndef _SVGA3D_DEVCAPS_H_ 33#define _SVGA3D_DEVCAPS_H_ 34 35#define INCLUDE_ALLOW_MODULE 36#define INCLUDE_ALLOW_USERLEVEL 37#define INCLUDE_ALLOW_VMCORE 38 39#include "includeCheck.h" 40 41/* 42 * 3D Hardware Version 43 * 44 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo 45 * register. Is set by the host and read by the guest. This lets 46 * us make new guest drivers which are backwards-compatible with old 47 * SVGA hardware revisions. It does not let us support old guest 48 * drivers. Good enough for now. 49 * 50 */ 51 52#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) 53#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16) 54#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF) 55 56typedef enum { 57 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1), 58 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2), 59 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3), 60 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1), 61 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4), 62 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0), 63 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1), 64 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1, 65} SVGA3dHardwareVersion; 66 67/* 68 * DevCap indexes. 69 */ 70 71typedef enum { 72 SVGA3D_DEVCAP_INVALID = ((uint32)-1), 73 SVGA3D_DEVCAP_3D = 0, 74 SVGA3D_DEVCAP_MAX_LIGHTS = 1, 75 76 /* 77 * SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of 78 * fixed-function texture units available. Each of these units 79 * work in both FFP and Shader modes, and they support texture 80 * transforms and texture coordinates. The host may have additional 81 * texture image units that are only usable with shaders. 82 */ 83 SVGA3D_DEVCAP_MAX_TEXTURES = 2, 84 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3, 85 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4, 86 SVGA3D_DEVCAP_VERTEX_SHADER = 5, 87 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6, 88 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7, 89 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8, 90 SVGA3D_DEVCAP_S23E8_TEXTURES = 9, 91 SVGA3D_DEVCAP_S10E5_TEXTURES = 10, 92 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11, 93 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, 94 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, 95 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, 96 SVGA3D_DEVCAP_QUERY_TYPES = 15, 97 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16, 98 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17, 99 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18, 100 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19, 101 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20, 102 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21, 103 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22, 104 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23, 105 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24, 106 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25, 107 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26, 108 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27, 109 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28, 110 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29, 111 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30, 112 SVGA3D_DEVCAP_TEXTURE_OPS = 31, 113 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32, 114 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33, 115 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34, 116 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35, 117 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36, 118 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37, 119 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38, 120 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39, 121 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40, 122 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41, 123 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42, 124 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43, 125 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44, 126 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45, 127 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46, 128 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47, 129 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48, 130 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49, 131 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50, 132 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51, 133 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52, 134 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53, 135 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54, 136 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55, 137 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56, 138 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57, 139 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58, 140 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59, 141 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60, 142 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61, 143 144 /* 145 * There is a hole in our devcap definitions for 146 * historical reasons. 147 * 148 * Define a constant just for completeness. 149 */ 150 SVGA3D_DEVCAP_MISSING62 = 62, 151 152 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63, 153 154 /* 155 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color 156 * render targets. This does not include the depth or stencil targets. 157 */ 158 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64, 159 160 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65, 161 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66, 162 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67, 163 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68, 164 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69, 165 166 /* 167 * Deprecated. 168 */ 169 SVGA3D_DEVCAP_DEAD4 = 70, 170 SVGA3D_DEVCAP_DEAD5 = 71, 171 SVGA3D_DEVCAP_DEAD7 = 72, 172 SVGA3D_DEVCAP_DEAD6 = 73, 173 174 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74, 175 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75, 176 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76, 177 178 /* 179 * This is the maximum number of SVGA context IDs that the guest 180 * can define using SVGA_3D_CMD_CONTEXT_DEFINE. 181 */ 182 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77, 183 184 /* 185 * This is the maximum number of SVGA surface IDs that the guest 186 * can define using SVGA_3D_CMD_SURFACE_DEFINE*. 187 */ 188 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78, 189 190 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79, 191 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80, 192 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81, 193 194 SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82, 195 SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83, 196 197 /* 198 * Deprecated. 199 */ 200 SVGA3D_DEVCAP_DEAD1 = 84, 201 SVGA3D_DEVCAP_DEAD8 = 85, 202 SVGA3D_DEVCAP_DEAD9 = 86, 203 204 SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */ 205 SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */ 206 SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */ 207 SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */ 208 209 SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91, 210 211 /* 212 * Deprecated. 213 */ 214 SVGA3D_DEVCAP_DEAD3 = 92, 215 216 /* 217 * Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported? 218 */ 219 SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */ 220 221 /* 222 * Deprecated. 223 */ 224 SVGA3D_DEVCAP_DEAD2 = 94, 225 226 /* 227 * Does the device support DXContexts? (ie DX10 era rendering) 228 */ 229 SVGA3D_DEVCAP_DXCONTEXT = 95, 230 231 /* 232 * What is the maximum size of a texture array? 233 * 234 * (Even if this cap is zero, cubemaps are still allowed.) 235 */ 236 SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE = 96, 237 238 /* 239 * What is the maximum number of vertex buffers or vertex input registers 240 * that can be expected to work correctly with a DXContext? 241 * 242 * The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but 243 * anything in excess of this cap is not guaranteed to render correctly. 244 * 245 * Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS 246 * input registers without the SVGA3D_DEVCAP_SM4_1 cap, or 247 * SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1, 248 * but only the registers up to this cap value are guaranteed to render 249 * correctly. 250 * 251 * If guest-drivers are able to expose a lower-limit, it's recommended 252 * that they clamp to this value. Otherwise, the host will make a 253 * best-effort on case-by-case basis if guests exceed this. 254 */ 255 SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS = 97, 256 257 /* 258 * What is the maximum number of constant buffers that can be expected to 259 * work correctly with a DX context? 260 * 261 * The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but 262 * anything in excess of this cap is not guaranteed to render correctly. 263 * 264 * If guest-drivers are able to expose a lower-limit, it's recommended 265 * that they clamp to this value. Otherwise, the host will make a 266 * best-effort on case-by-case basis if guests exceed this. 267 */ 268 SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS = 98, 269 270 /* 271 * Does the device support provoking vertex control? 272 * 273 * If this cap is present, the provokingVertexLast field in the 274 * rasterizer state is enabled. (Guests can then set it to FALSE, 275 * meaning that the first vertex is the provoking vertex, or TRUE, 276 * meaning that the last verteix is the provoking vertex.) 277 * 278 * If this cap is FALSE, then guests should set the provokingVertexLast 279 * to FALSE, otherwise rendering behavior is undefined. 280 */ 281 SVGA3D_DEVCAP_DX_PROVOKING_VERTEX = 99, 282 283 SVGA3D_DEVCAP_DXFMT_X8R8G8B8 = 100, 284 SVGA3D_DEVCAP_DXFMT_A8R8G8B8 = 101, 285 SVGA3D_DEVCAP_DXFMT_R5G6B5 = 102, 286 SVGA3D_DEVCAP_DXFMT_X1R5G5B5 = 103, 287 SVGA3D_DEVCAP_DXFMT_A1R5G5B5 = 104, 288 SVGA3D_DEVCAP_DXFMT_A4R4G4B4 = 105, 289 SVGA3D_DEVCAP_DXFMT_Z_D32 = 106, 290 SVGA3D_DEVCAP_DXFMT_Z_D16 = 107, 291 SVGA3D_DEVCAP_DXFMT_Z_D24S8 = 108, 292 SVGA3D_DEVCAP_DXFMT_Z_D15S1 = 109, 293 SVGA3D_DEVCAP_DXFMT_LUMINANCE8 = 110, 294 SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 = 111, 295 SVGA3D_DEVCAP_DXFMT_LUMINANCE16 = 112, 296 SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 = 113, 297 SVGA3D_DEVCAP_DXFMT_DXT1 = 114, 298 SVGA3D_DEVCAP_DXFMT_DXT2 = 115, 299 SVGA3D_DEVCAP_DXFMT_DXT3 = 116, 300 SVGA3D_DEVCAP_DXFMT_DXT4 = 117, 301 SVGA3D_DEVCAP_DXFMT_DXT5 = 118, 302 SVGA3D_DEVCAP_DXFMT_BUMPU8V8 = 119, 303 SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 = 120, 304 SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 = 121, 305 SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 = 122, 306 SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 = 123, 307 SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 = 124, 308 SVGA3D_DEVCAP_DXFMT_A2R10G10B10 = 125, 309 SVGA3D_DEVCAP_DXFMT_V8U8 = 126, 310 SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 = 127, 311 SVGA3D_DEVCAP_DXFMT_CxV8U8 = 128, 312 SVGA3D_DEVCAP_DXFMT_X8L8V8U8 = 129, 313 SVGA3D_DEVCAP_DXFMT_A2W10V10U10 = 130, 314 SVGA3D_DEVCAP_DXFMT_ALPHA8 = 131, 315 SVGA3D_DEVCAP_DXFMT_R_S10E5 = 132, 316 SVGA3D_DEVCAP_DXFMT_R_S23E8 = 133, 317 SVGA3D_DEVCAP_DXFMT_RG_S10E5 = 134, 318 SVGA3D_DEVCAP_DXFMT_RG_S23E8 = 135, 319 SVGA3D_DEVCAP_DXFMT_BUFFER = 136, 320 SVGA3D_DEVCAP_DXFMT_Z_D24X8 = 137, 321 SVGA3D_DEVCAP_DXFMT_V16U16 = 138, 322 SVGA3D_DEVCAP_DXFMT_G16R16 = 139, 323 SVGA3D_DEVCAP_DXFMT_A16B16G16R16 = 140, 324 SVGA3D_DEVCAP_DXFMT_UYVY = 141, 325 SVGA3D_DEVCAP_DXFMT_YUY2 = 142, 326 SVGA3D_DEVCAP_DXFMT_NV12 = 143, 327 SVGA3D_DEVCAP_DXFMT_AYUV = 144, 328 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS = 145, 329 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT = 146, 330 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT = 147, 331 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS = 148, 332 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT = 149, 333 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT = 150, 334 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT = 151, 335 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS = 152, 336 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT = 153, 337 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM = 154, 338 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT = 155, 339 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS = 156, 340 SVGA3D_DEVCAP_DXFMT_R32G32_UINT = 157, 341 SVGA3D_DEVCAP_DXFMT_R32G32_SINT = 158, 342 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS = 159, 343 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT = 160, 344 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 = 161, 345 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT = 162, 346 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS = 163, 347 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT = 164, 348 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT = 165, 349 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS = 166, 350 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM = 167, 351 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB = 168, 352 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT = 169, 353 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT = 170, 354 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS = 171, 355 SVGA3D_DEVCAP_DXFMT_R16G16_UINT = 172, 356 SVGA3D_DEVCAP_DXFMT_R16G16_SINT = 173, 357 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS = 174, 358 SVGA3D_DEVCAP_DXFMT_D32_FLOAT = 175, 359 SVGA3D_DEVCAP_DXFMT_R32_UINT = 176, 360 SVGA3D_DEVCAP_DXFMT_R32_SINT = 177, 361 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS = 178, 362 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT = 179, 363 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 = 180, 364 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT = 181, 365 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS = 182, 366 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM = 183, 367 SVGA3D_DEVCAP_DXFMT_R8G8_UINT = 184, 368 SVGA3D_DEVCAP_DXFMT_R8G8_SINT = 185, 369 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS = 186, 370 SVGA3D_DEVCAP_DXFMT_R16_UNORM = 187, 371 SVGA3D_DEVCAP_DXFMT_R16_UINT = 188, 372 SVGA3D_DEVCAP_DXFMT_R16_SNORM = 189, 373 SVGA3D_DEVCAP_DXFMT_R16_SINT = 190, 374 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS = 191, 375 SVGA3D_DEVCAP_DXFMT_R8_UNORM = 192, 376 SVGA3D_DEVCAP_DXFMT_R8_UINT = 193, 377 SVGA3D_DEVCAP_DXFMT_R8_SNORM = 194, 378 SVGA3D_DEVCAP_DXFMT_R8_SINT = 195, 379 SVGA3D_DEVCAP_DXFMT_P8 = 196, 380 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP = 197, 381 SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM = 198, 382 SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM = 199, 383 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS = 200, 384 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB = 201, 385 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS = 202, 386 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB = 203, 387 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS = 204, 388 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB = 205, 389 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS = 206, 390 SVGA3D_DEVCAP_DXFMT_ATI1 = 207, 391 SVGA3D_DEVCAP_DXFMT_BC4_SNORM = 208, 392 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS = 209, 393 SVGA3D_DEVCAP_DXFMT_ATI2 = 210, 394 SVGA3D_DEVCAP_DXFMT_BC5_SNORM = 211, 395 SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM = 212, 396 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS = 213, 397 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB = 214, 398 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS = 215, 399 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB = 216, 400 SVGA3D_DEVCAP_DXFMT_Z_DF16 = 217, 401 SVGA3D_DEVCAP_DXFMT_Z_DF24 = 218, 402 SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT = 219, 403 SVGA3D_DEVCAP_DXFMT_YV12 = 220, 404 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT = 221, 405 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT = 222, 406 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM = 223, 407 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT = 224, 408 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM = 225, 409 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM = 226, 410 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT = 227, 411 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM = 228, 412 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM = 229, 413 SVGA3D_DEVCAP_DXFMT_R32_FLOAT = 230, 414 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM = 231, 415 SVGA3D_DEVCAP_DXFMT_R16_FLOAT = 232, 416 SVGA3D_DEVCAP_DXFMT_D16_UNORM = 233, 417 SVGA3D_DEVCAP_DXFMT_A8_UNORM = 234, 418 SVGA3D_DEVCAP_DXFMT_BC1_UNORM = 235, 419 SVGA3D_DEVCAP_DXFMT_BC2_UNORM = 236, 420 SVGA3D_DEVCAP_DXFMT_BC3_UNORM = 237, 421 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM = 238, 422 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM = 239, 423 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM = 240, 424 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM = 241, 425 SVGA3D_DEVCAP_DXFMT_BC4_UNORM = 242, 426 SVGA3D_DEVCAP_DXFMT_BC5_UNORM = 243, 427 428 /* 429 * Advertises shaderModel 4.1 support, independent blend-states, 430 * cube-map arrays, and a higher vertex input registers limit. 431 * 432 * (ie DX10.1 era rendering) 433 * 434 * (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.) 435 */ 436 SVGA3D_DEVCAP_SM41 = 244, 437 438 SVGA3D_DEVCAP_MULTISAMPLE_2X = 245, 439 SVGA3D_DEVCAP_MULTISAMPLE_4X = 246, 440 441 SVGA3D_DEVCAP_MAX /* This must be the last index. */ 442} SVGA3dDevCapIndex; 443 444/* 445 * Bit definitions for DXFMT devcaps 446 * 447 * See also: 448 * http://msdn.microsoft.com/en-gb/library/windows/hardware/ff539390.aspx 449 * 450 * SUPPORTED: Can the format be defined? 451 * SHADER_SAMPLE: Can the format be sampled from a shader? 452 * COLOR_RENDERTARGET: Can the format be a color render target? 453 * DEPTH_RENDERTARGET: Can the format be a depth render target? 454 * BLENDABLE: Is the format blendable? 455 * MIPS: Does the format support mip levels? 456 * ARRAY: Does the format support texture arrays? 457 * VOLUME: Does the format support having volume? 458 * MULTISAMPLE: Does the format support multisample? 459 */ 460#define SVGA3D_DXFMT_SUPPORTED (1 << 0) 461#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1) 462#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2) 463#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3) 464#define SVGA3D_DXFMT_BLENDABLE (1 << 4) 465#define SVGA3D_DXFMT_MIPS (1 << 5) 466#define SVGA3D_DXFMT_ARRAY (1 << 6) 467#define SVGA3D_DXFMT_VOLUME (1 << 7) 468#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8) 469#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9) 470#define SVGA3D_DXFMT_MAX (1 << 10) 471 472typedef union { 473 SVGA3dBool b; 474 uint32 u; 475 int32 i; 476 float f; 477} SVGA3dDevCapResult; 478 479#endif /* _SVGA3D_DEVCAPS_H_ */ 480