1/**************************************************************************** 2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 ***************************************************************************/ 23 24#include "swr_context.h" 25#include "swr_public.h" 26#include "swr_screen.h" 27#include "swr_resource.h" 28#include "swr_fence.h" 29#include "gen_knobs.h" 30 31#include "pipe/p_screen.h" 32#include "pipe/p_defines.h" 33#include "util/u_memory.h" 34#include "util/u_format.h" 35#include "util/u_inlines.h" 36#include "util/u_cpu_detect.h" 37#include "util/u_format_s3tc.h" 38#include "util/u_string.h" 39#include "util/u_screen.h" 40 41#include "state_tracker/sw_winsys.h" 42 43#include "jit_api.h" 44 45#include "memory/TilingFunctions.h" 46 47#include <stdio.h> 48#include <map> 49 50/* 51 * Max texture sizes 52 * XXX Check max texture size values against core and sampler. 53 */ 54#define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */ 55#define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */ 56#define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */ 57#define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */ 58#define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */ 59 60/* Default max client_copy_limit */ 61#define SWR_CLIENT_COPY_LIMIT 8192 62 63/* Flag indicates creation of alternate surface, to prevent recursive loop 64 * in resource creation when msaa_force_enable is set. */ 65#define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) 66 67 68static const char * 69swr_get_name(struct pipe_screen *screen) 70{ 71 static char buf[100]; 72 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)", 73 HAVE_LLVM >> 8, HAVE_LLVM & 0xff, 74 lp_native_vector_width ); 75 return buf; 76} 77 78static const char * 79swr_get_vendor(struct pipe_screen *screen) 80{ 81 return "Intel Corporation"; 82} 83 84static boolean 85swr_is_format_supported(struct pipe_screen *_screen, 86 enum pipe_format format, 87 enum pipe_texture_target target, 88 unsigned sample_count, 89 unsigned storage_sample_count, 90 unsigned bind) 91{ 92 struct swr_screen *screen = swr_screen(_screen); 93 struct sw_winsys *winsys = screen->winsys; 94 const struct util_format_description *format_desc; 95 96 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D 97 || target == PIPE_TEXTURE_1D_ARRAY 98 || target == PIPE_TEXTURE_2D 99 || target == PIPE_TEXTURE_2D_ARRAY 100 || target == PIPE_TEXTURE_RECT 101 || target == PIPE_TEXTURE_3D 102 || target == PIPE_TEXTURE_CUBE 103 || target == PIPE_TEXTURE_CUBE_ARRAY); 104 105 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 106 return false; 107 108 format_desc = util_format_description(format); 109 if (!format_desc) 110 return FALSE; 111 112 if ((sample_count > screen->msaa_max_count) 113 || !util_is_power_of_two_or_zero(sample_count)) 114 return FALSE; 115 116 if (bind & PIPE_BIND_DISPLAY_TARGET) { 117 if (!winsys->is_displaytarget_format_supported(winsys, bind, format)) 118 return FALSE; 119 } 120 121 if (bind & PIPE_BIND_RENDER_TARGET) { 122 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) 123 return FALSE; 124 125 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) 126 return FALSE; 127 128 /* 129 * Although possible, it is unnatural to render into compressed or YUV 130 * surfaces. So disable these here to avoid going into weird paths 131 * inside the state trackers. 132 */ 133 if (format_desc->block.width != 1 || format_desc->block.height != 1) 134 return FALSE; 135 } 136 137 if (bind & PIPE_BIND_DEPTH_STENCIL) { 138 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 139 return FALSE; 140 141 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) 142 return FALSE; 143 } 144 145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC || 146 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) { 147 return FALSE; 148 } 149 150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC && 151 format != PIPE_FORMAT_ETC1_RGB8) { 152 return FALSE; 153 } 154 155 return TRUE; 156} 157 158static int 159swr_get_param(struct pipe_screen *screen, enum pipe_cap param) 160{ 161 switch (param) { 162 /* limits */ 163 case PIPE_CAP_MAX_RENDER_TARGETS: 164 return PIPE_MAX_COLOR_BUFS; 165 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 166 return SWR_MAX_TEXTURE_2D_LEVELS; 167 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 168 return SWR_MAX_TEXTURE_3D_LEVELS; 169 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 170 return SWR_MAX_TEXTURE_CUBE_LEVELS; 171 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 172 return MAX_SO_STREAMS; 173 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 174 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 175 return MAX_ATTRIBUTES * 4; 176 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 177 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 178 return 1024; 179 case PIPE_CAP_MAX_VERTEX_STREAMS: 180 return 1; 181 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 182 return 2048; 183 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 184 return SWR_MAX_TEXTURE_ARRAY_LAYERS; 185 case PIPE_CAP_MIN_TEXEL_OFFSET: 186 return -8; 187 case PIPE_CAP_MAX_TEXEL_OFFSET: 188 return 7; 189 case PIPE_CAP_GLSL_FEATURE_LEVEL: 190 return 330; 191 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 192 return 140; 193 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 194 return 16; 195 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 196 return 64; 197 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 198 return 65536; 199 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 200 return 0; 201 case PIPE_CAP_MAX_VIEWPORTS: 202 return 1; 203 case PIPE_CAP_ENDIANNESS: 204 return PIPE_ENDIAN_NATIVE; 205 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 206 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 207 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 208 return 0; 209 210 /* supported features */ 211 case PIPE_CAP_NPOT_TEXTURES: 212 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 213 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 214 case PIPE_CAP_SM3: 215 case PIPE_CAP_POINT_SPRITE: 216 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 217 case PIPE_CAP_OCCLUSION_QUERY: 218 case PIPE_CAP_QUERY_TIME_ELAPSED: 219 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 220 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 221 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: 222 case PIPE_CAP_TEXTURE_SWIZZLE: 223 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 224 case PIPE_CAP_INDEP_BLEND_ENABLE: 225 case PIPE_CAP_INDEP_BLEND_FUNC: 226 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 228 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 229 case PIPE_CAP_DEPTH_CLIP_DISABLE: 230 case PIPE_CAP_PRIMITIVE_RESTART: 231 case PIPE_CAP_TGSI_INSTANCEID: 232 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 233 case PIPE_CAP_START_INSTANCE: 234 case PIPE_CAP_SEAMLESS_CUBE_MAP: 235 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 236 case PIPE_CAP_CONDITIONAL_RENDER: 237 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 238 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 239 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 240 case PIPE_CAP_USER_VERTEX_BUFFERS: 241 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 242 case PIPE_CAP_QUERY_TIMESTAMP: 243 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 244 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 245 case PIPE_CAP_DRAW_INDIRECT: 246 case PIPE_CAP_UMA: 247 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 248 case PIPE_CAP_CLIP_HALFZ: 249 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 250 case PIPE_CAP_DEPTH_BOUNDS_TEST: 251 case PIPE_CAP_CLEAR_TEXTURE: 252 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 253 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 254 case PIPE_CAP_CULL_DISTANCE: 255 case PIPE_CAP_CUBE_MAP_ARRAY: 256 case PIPE_CAP_DOUBLES: 257 return 1; 258 259 /* MSAA support 260 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT) 261 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */ 262 case PIPE_CAP_TEXTURE_MULTISAMPLE: 263 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 264 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0; 265 case PIPE_CAP_FAKE_SW_MSAA: 266 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1; 267 268 /* fetch jit change for 2-4GB buffers requires alignment */ 269 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 270 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 271 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 272 return 1; 273 274 /* unsupported features */ 275 case PIPE_CAP_ANISOTROPIC_FILTER: 276 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 277 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 278 case PIPE_CAP_SHADER_STENCIL_EXPORT: 279 case PIPE_CAP_TEXTURE_BARRIER: 280 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 281 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 282 case PIPE_CAP_COMPUTE: 283 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 284 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 285 case PIPE_CAP_TGSI_TEXCOORD: 286 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 287 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 288 case PIPE_CAP_TEXTURE_GATHER_SM5: 289 case PIPE_CAP_TEXTURE_QUERY_LOD: 290 case PIPE_CAP_SAMPLE_SHADING: 291 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 292 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 293 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 294 case PIPE_CAP_SAMPLER_VIEW_TARGET: 295 case PIPE_CAP_VERTEXID_NOBASE: 296 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 297 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 298 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 299 case PIPE_CAP_TGSI_TXQS: 300 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 301 case PIPE_CAP_SHAREABLE_SHADERS: 302 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 303 case PIPE_CAP_DRAW_PARAMETERS: 304 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 305 case PIPE_CAP_MULTI_DRAW_INDIRECT: 306 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 307 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 308 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 309 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 310 case PIPE_CAP_INVALIDATE_BUFFER: 311 case PIPE_CAP_GENERATE_MIPMAP: 312 case PIPE_CAP_STRING_MARKER: 313 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 314 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 315 case PIPE_CAP_QUERY_BUFFER_OBJECT: 316 case PIPE_CAP_QUERY_MEMORY_INFO: 317 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 318 case PIPE_CAP_PCI_GROUP: 319 case PIPE_CAP_PCI_BUS: 320 case PIPE_CAP_PCI_DEVICE: 321 case PIPE_CAP_PCI_FUNCTION: 322 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 323 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 324 case PIPE_CAP_TGSI_VOTE: 325 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 326 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 327 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 328 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 329 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 330 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 331 case PIPE_CAP_NATIVE_FENCE_FD: 332 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 333 case PIPE_CAP_TGSI_FS_FBFETCH: 334 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 335 case PIPE_CAP_INT64: 336 case PIPE_CAP_INT64_DIVMOD: 337 case PIPE_CAP_TGSI_TEX_TXF_LZ: 338 case PIPE_CAP_TGSI_CLOCK: 339 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 340 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 341 case PIPE_CAP_TGSI_BALLOT: 342 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 343 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 344 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 345 case PIPE_CAP_POST_DEPTH_COVERAGE: 346 case PIPE_CAP_BINDLESS_TEXTURE: 347 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 348 case PIPE_CAP_QUERY_SO_OVERFLOW: 349 case PIPE_CAP_MEMOBJ: 350 case PIPE_CAP_LOAD_CONSTBUF: 351 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 352 case PIPE_CAP_TILE_RASTER_ORDER: 353 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 354 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: 355 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 356 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 357 case PIPE_CAP_FENCE_SIGNAL: 358 case PIPE_CAP_CONSTBUF0_FLAGS: 359 case PIPE_CAP_PACKED_UNIFORMS: 360 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: 361 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: 362 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: 363 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: 364 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: 365 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: 366 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: 367 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: 368 case PIPE_CAP_IMAGE_LOAD_FORMATTED: 369 return 0; 370 case PIPE_CAP_MAX_GS_INVOCATIONS: 371 return 32; 372 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: 373 return 1 << 27; 374 case PIPE_CAP_MAX_VARYINGS: 375 return 32; 376 377 case PIPE_CAP_VENDOR_ID: 378 return 0xFFFFFFFF; 379 case PIPE_CAP_DEVICE_ID: 380 return 0xFFFFFFFF; 381 case PIPE_CAP_ACCELERATED: 382 return 0; 383 case PIPE_CAP_VIDEO_MEMORY: { 384 /* XXX: Do we want to return the full amount of system memory ? */ 385 uint64_t system_memory; 386 387 if (!os_get_total_physical_memory(&system_memory)) 388 return 0; 389 390 return (int)(system_memory >> 20); 391 } 392 default: 393 return u_pipe_screen_get_param_defaults(screen, param); 394 } 395} 396 397static int 398swr_get_shader_param(struct pipe_screen *screen, 399 enum pipe_shader_type shader, 400 enum pipe_shader_cap param) 401{ 402 if (shader == PIPE_SHADER_VERTEX || 403 shader == PIPE_SHADER_FRAGMENT || 404 shader == PIPE_SHADER_GEOMETRY) 405 return gallivm_get_shader_param(param); 406 407 // Todo: tesselation, compute 408 return 0; 409} 410 411 412static float 413swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param) 414{ 415 switch (param) { 416 case PIPE_CAPF_MAX_LINE_WIDTH: 417 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 418 case PIPE_CAPF_MAX_POINT_WIDTH: 419 return 255.0; /* arbitrary */ 420 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 421 return 0.0; 422 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 423 return 0.0; 424 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 425 return 16.0; /* arbitrary */ 426 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 427 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 428 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 429 return 0.0f; 430 } 431 /* should only get here on unhandled cases */ 432 debug_printf("Unexpected PIPE_CAPF %d query\n", param); 433 return 0.0; 434} 435 436SWR_FORMAT 437mesa_to_swr_format(enum pipe_format format) 438{ 439 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = { 440 /* depth / stencil */ 441 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z 442 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z 443 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z 444 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z 445 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z 446 447 /* alpha */ 448 {PIPE_FORMAT_A8_UNORM, A8_UNORM}, 449 {PIPE_FORMAT_A16_UNORM, A16_UNORM}, 450 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT}, 451 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT}, 452 453 /* odd sizes, bgr */ 454 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM}, 455 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB}, 456 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM}, 457 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM}, 458 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM}, 459 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM}, 460 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB}, 461 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM}, 462 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB}, 463 464 /* rgb10a2 */ 465 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM}, 466 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM}, 467 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED}, 468 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED}, 469 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT}, 470 471 /* rgb10x2 */ 472 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED}, 473 474 /* bgr10a2 */ 475 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM}, 476 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM}, 477 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED}, 478 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED}, 479 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT}, 480 481 /* bgr10x2 */ 482 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM}, 483 484 /* r11g11b10 */ 485 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT}, 486 487 /* 32 bits per component */ 488 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT}, 489 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT}, 490 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT}, 491 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT}, 492 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT}, 493 494 {PIPE_FORMAT_R32_USCALED, R32_USCALED}, 495 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED}, 496 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED}, 497 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED}, 498 499 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED}, 500 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED}, 501 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED}, 502 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED}, 503 504 {PIPE_FORMAT_R32_UINT, R32_UINT}, 505 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT}, 506 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT}, 507 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT}, 508 509 {PIPE_FORMAT_R32_SINT, R32_SINT}, 510 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT}, 511 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT}, 512 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT}, 513 514 /* 16 bits per component */ 515 {PIPE_FORMAT_R16_UNORM, R16_UNORM}, 516 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM}, 517 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM}, 518 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM}, 519 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM}, 520 521 {PIPE_FORMAT_R16_USCALED, R16_USCALED}, 522 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED}, 523 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED}, 524 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED}, 525 526 {PIPE_FORMAT_R16_SNORM, R16_SNORM}, 527 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM}, 528 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM}, 529 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM}, 530 531 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED}, 532 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED}, 533 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED}, 534 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED}, 535 536 {PIPE_FORMAT_R16_UINT, R16_UINT}, 537 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT}, 538 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT}, 539 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT}, 540 541 {PIPE_FORMAT_R16_SINT, R16_SINT}, 542 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT}, 543 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT}, 544 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT}, 545 546 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT}, 547 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT}, 548 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT}, 549 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT}, 550 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT}, 551 552 /* 8 bits per component */ 553 {PIPE_FORMAT_R8_UNORM, R8_UNORM}, 554 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM}, 555 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM}, 556 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB}, 557 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM}, 558 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB}, 559 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM}, 560 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB}, 561 562 {PIPE_FORMAT_R8_USCALED, R8_USCALED}, 563 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED}, 564 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED}, 565 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED}, 566 567 {PIPE_FORMAT_R8_SNORM, R8_SNORM}, 568 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM}, 569 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM}, 570 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM}, 571 572 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED}, 573 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED}, 574 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED}, 575 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED}, 576 577 {PIPE_FORMAT_R8_UINT, R8_UINT}, 578 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT}, 579 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT}, 580 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT}, 581 582 {PIPE_FORMAT_R8_SINT, R8_SINT}, 583 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT}, 584 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT}, 585 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT}, 586 587 /* These formats are valid for vertex data, but should not be used 588 * for render targets. 589 */ 590 591 {PIPE_FORMAT_R32_FIXED, R32_SFIXED}, 592 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED}, 593 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED}, 594 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED}, 595 596 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT}, 597 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT}, 598 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT}, 599 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT}, 600 601 /* These formats have entries in SWR but don't have Load/StoreTile 602 * implementations. That means these aren't renderable, and thus having 603 * a mapping entry here is detrimental. 604 */ 605 /* 606 607 {PIPE_FORMAT_L8_UNORM, L8_UNORM}, 608 {PIPE_FORMAT_I8_UNORM, I8_UNORM}, 609 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM}, 610 {PIPE_FORMAT_L16_UNORM, L16_UNORM}, 611 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY}, 612 613 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB}, 614 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB}, 615 616 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM}, 617 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM}, 618 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM}, 619 620 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB}, 621 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB}, 622 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB}, 623 624 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM}, 625 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM}, 626 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM}, 627 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM}, 628 629 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM}, 630 {PIPE_FORMAT_I16_UNORM, I16_UNORM}, 631 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT}, 632 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT}, 633 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT}, 634 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT}, 635 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT}, 636 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT}, 637 638 {PIPE_FORMAT_I8_UINT, I8_UINT}, 639 {PIPE_FORMAT_L8_UINT, L8_UINT}, 640 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT}, 641 642 {PIPE_FORMAT_I8_SINT, I8_SINT}, 643 {PIPE_FORMAT_L8_SINT, L8_SINT}, 644 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT}, 645 646 */ 647 }; 648 649 auto it = mesa2swr.find(format); 650 if (it == mesa2swr.end()) 651 return (SWR_FORMAT)-1; 652 else 653 return it->second; 654} 655 656static boolean 657swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res) 658{ 659 struct sw_winsys *winsys = screen->winsys; 660 struct sw_displaytarget *dt; 661 662 const unsigned width = align(res->swr.width, res->swr.halign); 663 const unsigned height = align(res->swr.height, res->swr.valign); 664 665 UINT stride; 666 dt = winsys->displaytarget_create(winsys, 667 res->base.bind, 668 res->base.format, 669 width, height, 670 64, NULL, 671 &stride); 672 673 if (dt == NULL) 674 return FALSE; 675 676 void *map = winsys->displaytarget_map(winsys, dt, 0); 677 678 res->display_target = dt; 679 res->swr.xpBaseAddress = (gfxptr_t)map; 680 681 /* Clear the display target surface */ 682 if (map) 683 memset(map, 0, height * stride); 684 685 winsys->displaytarget_unmap(winsys, dt); 686 687 return TRUE; 688} 689 690static bool 691swr_texture_layout(struct swr_screen *screen, 692 struct swr_resource *res, 693 boolean allocate) 694{ 695 struct pipe_resource *pt = &res->base; 696 697 pipe_format fmt = pt->format; 698 const struct util_format_description *desc = util_format_description(fmt); 699 700 res->has_depth = util_format_has_depth(desc); 701 res->has_stencil = util_format_has_stencil(desc); 702 703 if (res->has_stencil && !res->has_depth) 704 fmt = PIPE_FORMAT_R8_UINT; 705 706 /* We always use the SWR layout. For 2D and 3D textures this looks like: 707 * 708 * |<------- pitch ------->| 709 * +=======================+------- 710 * |Array 0 | ^ 711 * | | | 712 * | Level 0 | | 713 * | | | 714 * | | qpitch 715 * +-----------+-----------+ | 716 * | | L2L2L2L2 | | 717 * | Level 1 | L3L3 | | 718 * | | L4 | v 719 * +===========+===========+------- 720 * |Array 1 | 721 * | | 722 * | Level 0 | 723 * | | 724 * | | 725 * +-----------+-----------+ 726 * | | L2L2L2L2 | 727 * | Level 1 | L3L3 | 728 * | | L4 | 729 * +===========+===========+ 730 * 731 * The overall width in bytes is known as the pitch, while the overall 732 * height in rows is the qpitch. Array slices are laid out logically below 733 * one another, qpitch rows apart. For 3D surfaces, the "level" values are 734 * just invalid for the higher array numbers (since depth is also 735 * minified). 1D and 1D array surfaces are stored effectively the same way, 736 * except that pitch never plays into it. All the levels are logically 737 * adjacent to each other on the X axis. The qpitch becomes the number of 738 * elements between array slices, while the pitch is unused. 739 * 740 * Each level's sizes are subject to the valign and halign settings of the 741 * surface. For compressed formats that swr is unaware of, we will use an 742 * appropriately-sized uncompressed format, and scale the widths/heights. 743 * 744 * This surface is stored inside res->swr. For depth/stencil textures, 745 * res->secondary will have an identically-laid-out but R8_UINT-formatted 746 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp 747 * texels, to simplify map/unmap logic which copies the stencil values 748 * in/out. 749 */ 750 751 res->swr.width = pt->width0; 752 res->swr.height = pt->height0; 753 res->swr.type = swr_convert_target_type(pt->target); 754 res->swr.tileMode = SWR_TILE_NONE; 755 res->swr.format = mesa_to_swr_format(fmt); 756 res->swr.numSamples = std::max(1u, pt->nr_samples); 757 758 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) { 759 res->swr.halign = KNOB_MACROTILE_X_DIM; 760 res->swr.valign = KNOB_MACROTILE_Y_DIM; 761 762 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested 763 * surface sample count. */ 764 if (screen->msaa_force_enable) { 765 res->swr.numSamples = screen->msaa_max_count; 766 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n", 767 res->swr.numSamples); 768 } 769 } else { 770 res->swr.halign = 1; 771 res->swr.valign = 1; 772 } 773 774 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt); 775 unsigned width = align(pt->width0, halign); 776 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) { 777 for (int level = 1; level <= pt->last_level; level++) 778 width += align(u_minify(pt->width0, level), halign); 779 res->swr.pitch = util_format_get_blocksize(fmt); 780 res->swr.qpitch = util_format_get_nblocksx(fmt, width); 781 } else { 782 // The pitch is the overall width of the texture in bytes. Most of the 783 // time this is the pitch of level 0 since all the other levels fit 784 // underneath it. However in some degenerate situations, the width of 785 // level1 + level2 may be larger. In that case, we use those 786 // widths. This can happen if, e.g. halign is 32, and the width of level 787 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also 788 // be 32 each, adding up to 64. 789 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt); 790 if (pt->last_level > 1) { 791 width = std::max<uint32_t>( 792 width, 793 align(u_minify(pt->width0, 1), halign) + 794 align(u_minify(pt->width0, 2), halign)); 795 } 796 res->swr.pitch = util_format_get_stride(fmt, width); 797 798 // The qpitch is controlled by either the height of the second LOD, or 799 // the combination of all the later LODs. 800 unsigned height = align(pt->height0, valign); 801 if (pt->last_level == 1) { 802 height += align(u_minify(pt->height0, 1), valign); 803 } else if (pt->last_level > 1) { 804 unsigned level1 = align(u_minify(pt->height0, 1), valign); 805 unsigned level2 = 0; 806 for (int level = 2; level <= pt->last_level; level++) { 807 level2 += align(u_minify(pt->height0, level), valign); 808 } 809 height += std::max(level1, level2); 810 } 811 res->swr.qpitch = util_format_get_nblocksy(fmt, height); 812 } 813 814 if (pt->target == PIPE_TEXTURE_3D) 815 res->swr.depth = pt->depth0; 816 else 817 res->swr.depth = pt->array_size; 818 819 // Fix up swr format if necessary so that LOD offset computation works 820 if (res->swr.format == (SWR_FORMAT)-1) { 821 switch (util_format_get_blocksize(fmt)) { 822 default: 823 unreachable("Unexpected format block size"); 824 case 1: res->swr.format = R8_UINT; break; 825 case 2: res->swr.format = R16_UINT; break; 826 case 4: res->swr.format = R32_UINT; break; 827 case 8: 828 if (util_format_is_compressed(fmt)) 829 res->swr.format = BC4_UNORM; 830 else 831 res->swr.format = R32G32_UINT; 832 break; 833 case 16: 834 if (util_format_is_compressed(fmt)) 835 res->swr.format = BC5_UNORM; 836 else 837 res->swr.format = R32G32B32A32_UINT; 838 break; 839 } 840 } 841 842 for (int level = 0; level <= pt->last_level; level++) { 843 res->mip_offsets[level] = 844 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr); 845 } 846 847 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch * 848 res->swr.pitch * res->swr.numSamples; 849 850 // Let non-sampled textures (e.g. buffer objects) bypass the size limit 851 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE) 852 return false; 853 854 if (allocate) { 855 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64); 856 if (!res->swr.xpBaseAddress) 857 return false; 858 859 if (res->has_depth && res->has_stencil) { 860 res->secondary = res->swr; 861 res->secondary.format = R8_UINT; 862 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt); 863 864 for (int level = 0; level <= pt->last_level; level++) { 865 res->secondary_mip_offsets[level] = 866 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary); 867 } 868 869 total_size = res->secondary.depth * res->secondary.qpitch * 870 res->secondary.pitch * res->secondary.numSamples; 871 872 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64); 873 if (!res->secondary.xpBaseAddress) { 874 AlignedFree((void *)res->swr.xpBaseAddress); 875 return false; 876 } 877 } 878 } 879 880 return true; 881} 882 883static boolean 884swr_can_create_resource(struct pipe_screen *screen, 885 const struct pipe_resource *templat) 886{ 887 struct swr_resource res; 888 memset(&res, 0, sizeof(res)); 889 res.base = *templat; 890 return swr_texture_layout(swr_screen(screen), &res, false); 891} 892 893/* Helper function that conditionally creates a single-sample resolve resource 894 * and attaches it to main multisample resource. */ 895static boolean 896swr_create_resolve_resource(struct pipe_screen *_screen, 897 struct swr_resource *msaa_res) 898{ 899 struct swr_screen *screen = swr_screen(_screen); 900 901 /* If resource is multisample, create a single-sample resolve resource */ 902 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable && 903 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) { 904 905 /* Create a single-sample copy of the resource. Copy the original 906 * resource parameters and set flag to prevent recursion when re-calling 907 * resource_create */ 908 struct pipe_resource alt_template = msaa_res->base; 909 alt_template.nr_samples = 0; 910 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE; 911 912 /* Note: Display_target is a special single-sample resource, only the 913 * display_target has been created already. */ 914 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT 915 | PIPE_BIND_SHARED)) { 916 /* Allocate the multisample buffers. */ 917 if (!swr_texture_layout(screen, msaa_res, true)) 918 return false; 919 920 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET 921 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */ 922 alt_template.bind = PIPE_BIND_RENDER_TARGET; 923 } 924 925 /* Allocate single-sample resolve surface */ 926 struct pipe_resource *alt; 927 alt = _screen->resource_create(_screen, &alt_template); 928 if (!alt) 929 return false; 930 931 /* Attach it to the multisample resource */ 932 msaa_res->resolve_target = alt; 933 934 /* Hang resolve surface state off the multisample surface state to so 935 * StoreTiles knows where to resolve the surface. */ 936 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr; 937 } 938 939 return true; /* success */ 940} 941 942static struct pipe_resource * 943swr_resource_create(struct pipe_screen *_screen, 944 const struct pipe_resource *templat) 945{ 946 struct swr_screen *screen = swr_screen(_screen); 947 struct swr_resource *res = CALLOC_STRUCT(swr_resource); 948 if (!res) 949 return NULL; 950 951 res->base = *templat; 952 pipe_reference_init(&res->base.reference, 1); 953 res->base.screen = &screen->base; 954 955 if (swr_resource_is_texture(&res->base)) { 956 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT 957 | PIPE_BIND_SHARED)) { 958 /* displayable surface 959 * first call swr_texture_layout without allocating to finish 960 * filling out the SWR_SURFACE_STATE in res */ 961 swr_texture_layout(screen, res, false); 962 if (!swr_displaytarget_layout(screen, res)) 963 goto fail; 964 } else { 965 /* texture map */ 966 if (!swr_texture_layout(screen, res, true)) 967 goto fail; 968 } 969 970 /* If resource was multisample, create resolve resource and attach 971 * it to multisample resource. */ 972 if (!swr_create_resolve_resource(_screen, res)) 973 goto fail; 974 975 } else { 976 /* other data (vertex buffer, const buffer, etc) */ 977 assert(util_format_get_blocksize(templat->format) == 1); 978 assert(templat->height0 == 1); 979 assert(templat->depth0 == 1); 980 assert(templat->last_level == 0); 981 982 /* Easiest to just call swr_texture_layout, as it sets up 983 * SWR_SURFACE_STATE in res */ 984 if (!swr_texture_layout(screen, res, true)) 985 goto fail; 986 } 987 988 return &res->base; 989 990fail: 991 FREE(res); 992 return NULL; 993} 994 995static void 996swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt) 997{ 998 struct swr_screen *screen = swr_screen(p_screen); 999 struct swr_resource *spr = swr_resource(pt); 1000 1001 if (spr->display_target) { 1002 /* If resource is display target, winsys manages the buffer and will 1003 * free it on displaytarget_destroy. */ 1004 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); 1005 1006 struct sw_winsys *winsys = screen->winsys; 1007 winsys->displaytarget_destroy(winsys, spr->display_target); 1008 1009 if (spr->swr.numSamples > 1) { 1010 /* Free an attached resolve resource */ 1011 struct swr_resource *alt = swr_resource(spr->resolve_target); 1012 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true); 1013 1014 /* Free multisample buffer */ 1015 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true); 1016 } 1017 } else { 1018 /* For regular resources, defer deletion */ 1019 swr_resource_unused(pt); 1020 1021 if (spr->swr.numSamples > 1) { 1022 /* Free an attached resolve resource */ 1023 struct swr_resource *alt = swr_resource(spr->resolve_target); 1024 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true); 1025 } 1026 1027 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true); 1028 swr_fence_work_free(screen->flush_fence, 1029 (void*)(spr->secondary.xpBaseAddress), true); 1030 1031 /* If work queue grows too large, submit a fence to force queue to 1032 * drain. This is mainly to decrease the amount of memory used by the 1033 * piglit streaming-texture-leak test */ 1034 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64) 1035 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence); 1036 } 1037 1038 FREE(spr); 1039} 1040 1041 1042static void 1043swr_flush_frontbuffer(struct pipe_screen *p_screen, 1044 struct pipe_resource *resource, 1045 unsigned level, 1046 unsigned layer, 1047 void *context_private, 1048 struct pipe_box *sub_box) 1049{ 1050 struct swr_screen *screen = swr_screen(p_screen); 1051 struct sw_winsys *winsys = screen->winsys; 1052 struct swr_resource *spr = swr_resource(resource); 1053 struct pipe_context *pipe = screen->pipe; 1054 struct swr_context *ctx = swr_context(pipe); 1055 1056 if (pipe) { 1057 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); 1058 swr_resource_unused(resource); 1059 ctx->api.pfnSwrEndFrame(ctx->swrContext); 1060 } 1061 1062 /* Multisample resolved into resolve_target at flush with store_resource */ 1063 if (pipe && spr->swr.numSamples > 1) { 1064 struct pipe_resource *resolve_target = spr->resolve_target; 1065 1066 /* Once resolved, copy into display target */ 1067 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr; 1068 1069 void *map = winsys->displaytarget_map(winsys, spr->display_target, 1070 PIPE_TRANSFER_WRITE); 1071 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height); 1072 winsys->displaytarget_unmap(winsys, spr->display_target); 1073 } 1074 1075 debug_assert(spr->display_target); 1076 if (spr->display_target) 1077 winsys->displaytarget_display( 1078 winsys, spr->display_target, context_private, sub_box); 1079} 1080 1081 1082void 1083swr_destroy_screen_internal(struct swr_screen **screen) 1084{ 1085 struct pipe_screen *p_screen = &(*screen)->base; 1086 1087 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0); 1088 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL); 1089 1090 JitDestroyContext((*screen)->hJitMgr); 1091 1092 if ((*screen)->pLibrary) 1093 util_dl_close((*screen)->pLibrary); 1094 1095 FREE(*screen); 1096 *screen = NULL; 1097} 1098 1099 1100static void 1101swr_destroy_screen(struct pipe_screen *p_screen) 1102{ 1103 struct swr_screen *screen = swr_screen(p_screen); 1104 struct sw_winsys *winsys = screen->winsys; 1105 1106 fprintf(stderr, "SWR destroy screen!\n"); 1107 1108 if (winsys->destroy) 1109 winsys->destroy(winsys); 1110 1111 swr_destroy_screen_internal(&screen); 1112} 1113 1114 1115static void 1116swr_validate_env_options(struct swr_screen *screen) 1117{ 1118 /* The client_copy_limit sets a maximum on the amount of user-buffer memory 1119 * copied to scratch space on a draw. Past this, the draw will access 1120 * user-buffer directly and then block. This is faster than queuing many 1121 * large client draws. */ 1122 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT; 1123 int client_copy_limit = 1124 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT); 1125 if (client_copy_limit > 0) 1126 screen->client_copy_limit = client_copy_limit; 1127 1128 /* XXX msaa under development, disable by default for now */ 1129 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */ 1130 1131 /* validate env override values, within range and power of 2 */ 1132 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1); 1133 if (msaa_max_count != 1) { 1134 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES) 1135 || !util_is_power_of_two_or_zero(msaa_max_count)) { 1136 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count); 1137 fprintf(stderr, "must be power of 2 between 1 and %d" \ 1138 " (or 1 to disable msaa)\n", 1139 SWR_MAX_NUM_MULTISAMPLES); 1140 msaa_max_count = 1; 1141 } 1142 1143 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count); 1144 if (msaa_max_count == 1) 1145 fprintf(stderr, "(msaa disabled)\n"); 1146 1147 screen->msaa_max_count = msaa_max_count; 1148 } 1149 1150 screen->msaa_force_enable = debug_get_bool_option( 1151 "SWR_MSAA_FORCE_ENABLE", false); 1152 if (screen->msaa_force_enable) 1153 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n"); 1154} 1155 1156 1157struct pipe_screen * 1158swr_create_screen_internal(struct sw_winsys *winsys) 1159{ 1160 struct swr_screen *screen = CALLOC_STRUCT(swr_screen); 1161 1162 if (!screen) 1163 return NULL; 1164 1165 if (!lp_build_init()) { 1166 FREE(screen); 1167 return NULL; 1168 } 1169 1170 screen->winsys = winsys; 1171 screen->base.get_name = swr_get_name; 1172 screen->base.get_vendor = swr_get_vendor; 1173 screen->base.is_format_supported = swr_is_format_supported; 1174 screen->base.context_create = swr_create_context; 1175 screen->base.can_create_resource = swr_can_create_resource; 1176 1177 screen->base.destroy = swr_destroy_screen; 1178 screen->base.get_param = swr_get_param; 1179 screen->base.get_shader_param = swr_get_shader_param; 1180 screen->base.get_paramf = swr_get_paramf; 1181 1182 screen->base.resource_create = swr_resource_create; 1183 screen->base.resource_destroy = swr_resource_destroy; 1184 1185 screen->base.flush_frontbuffer = swr_flush_frontbuffer; 1186 1187 // Pass in "" for architecture for run-time determination 1188 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr"); 1189 1190 swr_fence_init(&screen->base); 1191 1192 swr_validate_env_options(screen); 1193 1194 return &screen->base; 1195} 1196 1197