1b8e80941Smrg/* 2b8e80941Smrg * Copyright © 2014-2017 Broadcom 3b8e80941Smrg * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org> 4b8e80941Smrg * 5b8e80941Smrg * Permission is hereby granted, free of charge, to any person obtaining a 6b8e80941Smrg * copy of this software and associated documentation files (the "Software"), 7b8e80941Smrg * to deal in the Software without restriction, including without limitation 8b8e80941Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9b8e80941Smrg * and/or sell copies of the Software, and to permit persons to whom the 10b8e80941Smrg * Software is furnished to do so, subject to the following conditions: 11b8e80941Smrg * 12b8e80941Smrg * The above copyright notice and this permission notice (including the next 13b8e80941Smrg * paragraph) shall be included in all copies or substantial portions of the 14b8e80941Smrg * Software. 15b8e80941Smrg * 16b8e80941Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17b8e80941Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18b8e80941Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19b8e80941Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20b8e80941Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21b8e80941Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22b8e80941Smrg * IN THE SOFTWARE. 23b8e80941Smrg */ 24b8e80941Smrg 25b8e80941Smrg#ifndef VC5_CONTEXT_H 26b8e80941Smrg#define VC5_CONTEXT_H 27b8e80941Smrg 28b8e80941Smrg#ifdef V3D_VERSION 29b8e80941Smrg#include "broadcom/common/v3d_macros.h" 30b8e80941Smrg#endif 31b8e80941Smrg 32b8e80941Smrg#include <stdio.h> 33b8e80941Smrg 34b8e80941Smrg#include "pipe/p_context.h" 35b8e80941Smrg#include "pipe/p_state.h" 36b8e80941Smrg#include "util/bitset.h" 37b8e80941Smrg#include "util/slab.h" 38b8e80941Smrg#include "xf86drm.h" 39b8e80941Smrg#include "drm-uapi/v3d_drm.h" 40b8e80941Smrg#include "v3d_screen.h" 41b8e80941Smrg#include "broadcom/common/v3d_limits.h" 42b8e80941Smrg 43b8e80941Smrgstruct v3d_job; 44b8e80941Smrgstruct v3d_bo; 45b8e80941Smrgvoid v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo); 46b8e80941Smrg 47b8e80941Smrg#include "v3d_bufmgr.h" 48b8e80941Smrg#include "v3d_resource.h" 49b8e80941Smrg#include "v3d_cl.h" 50b8e80941Smrg 51b8e80941Smrg#ifdef USE_V3D_SIMULATOR 52b8e80941Smrg#define using_v3d_simulator true 53b8e80941Smrg#else 54b8e80941Smrg#define using_v3d_simulator false 55b8e80941Smrg#endif 56b8e80941Smrg 57b8e80941Smrg#define VC5_DIRTY_BLEND (1 << 0) 58b8e80941Smrg#define VC5_DIRTY_RASTERIZER (1 << 1) 59b8e80941Smrg#define VC5_DIRTY_ZSA (1 << 2) 60b8e80941Smrg#define VC5_DIRTY_FRAGTEX (1 << 3) 61b8e80941Smrg#define VC5_DIRTY_VERTTEX (1 << 4) 62b8e80941Smrg#define VC5_DIRTY_SHADER_IMAGE (1 << 5) 63b8e80941Smrg 64b8e80941Smrg#define VC5_DIRTY_BLEND_COLOR (1 << 7) 65b8e80941Smrg#define VC5_DIRTY_STENCIL_REF (1 << 8) 66b8e80941Smrg#define VC5_DIRTY_SAMPLE_STATE (1 << 9) 67b8e80941Smrg#define VC5_DIRTY_FRAMEBUFFER (1 << 10) 68b8e80941Smrg#define VC5_DIRTY_STIPPLE (1 << 11) 69b8e80941Smrg#define VC5_DIRTY_VIEWPORT (1 << 12) 70b8e80941Smrg#define VC5_DIRTY_CONSTBUF (1 << 13) 71b8e80941Smrg#define VC5_DIRTY_VTXSTATE (1 << 14) 72b8e80941Smrg#define VC5_DIRTY_VTXBUF (1 << 15) 73b8e80941Smrg#define VC5_DIRTY_SCISSOR (1 << 17) 74b8e80941Smrg#define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18) 75b8e80941Smrg#define VC5_DIRTY_PRIM_MODE (1 << 19) 76b8e80941Smrg#define VC5_DIRTY_CLIP (1 << 20) 77b8e80941Smrg#define VC5_DIRTY_UNCOMPILED_VS (1 << 21) 78b8e80941Smrg#define VC5_DIRTY_UNCOMPILED_FS (1 << 22) 79b8e80941Smrg#define VC5_DIRTY_COMPILED_CS (1 << 23) 80b8e80941Smrg#define VC5_DIRTY_COMPILED_VS (1 << 24) 81b8e80941Smrg#define VC5_DIRTY_COMPILED_FS (1 << 25) 82b8e80941Smrg#define VC5_DIRTY_FS_INPUTS (1 << 26) 83b8e80941Smrg#define VC5_DIRTY_STREAMOUT (1 << 27) 84b8e80941Smrg#define VC5_DIRTY_OQ (1 << 28) 85b8e80941Smrg#define VC5_DIRTY_CENTROID_FLAGS (1 << 29) 86b8e80941Smrg#define VC5_DIRTY_NOPERSPECTIVE_FLAGS (1 << 30) 87b8e80941Smrg#define VC5_DIRTY_SSBO (1 << 31) 88b8e80941Smrg 89b8e80941Smrg#define VC5_MAX_FS_INPUTS 64 90b8e80941Smrg 91b8e80941Smrgenum v3d_sampler_state_variant { 92b8e80941Smrg V3D_SAMPLER_STATE_BORDER_0, 93b8e80941Smrg V3D_SAMPLER_STATE_F16, 94b8e80941Smrg V3D_SAMPLER_STATE_F16_UNORM, 95b8e80941Smrg V3D_SAMPLER_STATE_F16_SNORM, 96b8e80941Smrg V3D_SAMPLER_STATE_F16_BGRA, 97b8e80941Smrg V3D_SAMPLER_STATE_F16_BGRA_UNORM, 98b8e80941Smrg V3D_SAMPLER_STATE_F16_BGRA_SNORM, 99b8e80941Smrg V3D_SAMPLER_STATE_F16_A, 100b8e80941Smrg V3D_SAMPLER_STATE_F16_A_SNORM, 101b8e80941Smrg V3D_SAMPLER_STATE_F16_A_UNORM, 102b8e80941Smrg V3D_SAMPLER_STATE_F16_LA, 103b8e80941Smrg V3D_SAMPLER_STATE_F16_LA_UNORM, 104b8e80941Smrg V3D_SAMPLER_STATE_F16_LA_SNORM, 105b8e80941Smrg V3D_SAMPLER_STATE_32, 106b8e80941Smrg V3D_SAMPLER_STATE_32_UNORM, 107b8e80941Smrg V3D_SAMPLER_STATE_32_SNORM, 108b8e80941Smrg V3D_SAMPLER_STATE_32_A, 109b8e80941Smrg V3D_SAMPLER_STATE_32_A_UNORM, 110b8e80941Smrg V3D_SAMPLER_STATE_32_A_SNORM, 111b8e80941Smrg V3D_SAMPLER_STATE_1010102U, 112b8e80941Smrg V3D_SAMPLER_STATE_16U, 113b8e80941Smrg V3D_SAMPLER_STATE_16I, 114b8e80941Smrg V3D_SAMPLER_STATE_8I, 115b8e80941Smrg V3D_SAMPLER_STATE_8U, 116b8e80941Smrg 117b8e80941Smrg V3D_SAMPLER_STATE_VARIANT_COUNT, 118b8e80941Smrg}; 119b8e80941Smrg 120b8e80941Smrgstruct v3d_sampler_view { 121b8e80941Smrg struct pipe_sampler_view base; 122b8e80941Smrg uint32_t p0; 123b8e80941Smrg uint32_t p1; 124b8e80941Smrg /* Precomputed swizzles to pass in to the shader key. */ 125b8e80941Smrg uint8_t swizzle[4]; 126b8e80941Smrg 127b8e80941Smrg uint8_t texture_shader_state[32]; 128b8e80941Smrg /* V3D 4.x: Texture state struct. */ 129b8e80941Smrg struct v3d_bo *bo; 130b8e80941Smrg 131b8e80941Smrg enum v3d_sampler_state_variant sampler_variant; 132b8e80941Smrg 133b8e80941Smrg /* Actual texture to be read by this sampler view. May be different 134b8e80941Smrg * from base.texture in the case of having a shadow tiled copy of a 135b8e80941Smrg * raster texture. 136b8e80941Smrg */ 137b8e80941Smrg struct pipe_resource *texture; 138b8e80941Smrg}; 139b8e80941Smrg 140b8e80941Smrgstruct v3d_sampler_state { 141b8e80941Smrg struct pipe_sampler_state base; 142b8e80941Smrg uint32_t p0; 143b8e80941Smrg uint32_t p1; 144b8e80941Smrg 145b8e80941Smrg /* V3D 3.x: Packed texture state. */ 146b8e80941Smrg uint8_t texture_shader_state[32]; 147b8e80941Smrg /* V3D 4.x: Sampler state struct. */ 148b8e80941Smrg struct pipe_resource *sampler_state; 149b8e80941Smrg uint32_t sampler_state_offset[V3D_SAMPLER_STATE_VARIANT_COUNT]; 150b8e80941Smrg 151b8e80941Smrg bool border_color_variants; 152b8e80941Smrg}; 153b8e80941Smrg 154b8e80941Smrgstruct v3d_texture_stateobj { 155b8e80941Smrg struct pipe_sampler_view *textures[V3D_MAX_TEXTURE_SAMPLERS]; 156b8e80941Smrg unsigned num_textures; 157b8e80941Smrg struct pipe_sampler_state *samplers[V3D_MAX_TEXTURE_SAMPLERS]; 158b8e80941Smrg unsigned num_samplers; 159b8e80941Smrg struct v3d_cl_reloc texture_state[V3D_MAX_TEXTURE_SAMPLERS]; 160b8e80941Smrg}; 161b8e80941Smrg 162b8e80941Smrgstruct v3d_shader_uniform_info { 163b8e80941Smrg enum quniform_contents *contents; 164b8e80941Smrg uint32_t *data; 165b8e80941Smrg uint32_t count; 166b8e80941Smrg}; 167b8e80941Smrg 168b8e80941Smrgstruct v3d_uncompiled_shader { 169b8e80941Smrg /** A name for this program, so you can track it in shader-db output. */ 170b8e80941Smrg uint32_t program_id; 171b8e80941Smrg /** How many variants of this program were compiled, for shader-db. */ 172b8e80941Smrg uint32_t compiled_variant_count; 173b8e80941Smrg struct pipe_shader_state base; 174b8e80941Smrg uint32_t num_tf_outputs; 175b8e80941Smrg struct v3d_varying_slot *tf_outputs; 176b8e80941Smrg uint16_t tf_specs[16]; 177b8e80941Smrg uint16_t tf_specs_psiz[16]; 178b8e80941Smrg uint32_t num_tf_specs; 179b8e80941Smrg}; 180b8e80941Smrg 181b8e80941Smrgstruct v3d_compiled_shader { 182b8e80941Smrg struct pipe_resource *resource; 183b8e80941Smrg uint32_t offset; 184b8e80941Smrg 185b8e80941Smrg union { 186b8e80941Smrg struct v3d_prog_data *base; 187b8e80941Smrg struct v3d_vs_prog_data *vs; 188b8e80941Smrg struct v3d_fs_prog_data *fs; 189b8e80941Smrg struct v3d_compute_prog_data *compute; 190b8e80941Smrg } prog_data; 191b8e80941Smrg 192b8e80941Smrg /** 193b8e80941Smrg * VC5_DIRTY_* flags that, when set in v3d->dirty, mean that the 194b8e80941Smrg * uniforms have to be rewritten (and therefore the shader state 195b8e80941Smrg * reemitted). 196b8e80941Smrg */ 197b8e80941Smrg uint32_t uniform_dirty_bits; 198b8e80941Smrg}; 199b8e80941Smrg 200b8e80941Smrgstruct v3d_program_stateobj { 201b8e80941Smrg struct v3d_uncompiled_shader *bind_vs, *bind_fs, *bind_compute; 202b8e80941Smrg struct v3d_compiled_shader *cs, *vs, *fs, *compute; 203b8e80941Smrg 204b8e80941Smrg struct hash_table *cache[MESA_SHADER_STAGES]; 205b8e80941Smrg 206b8e80941Smrg struct v3d_bo *spill_bo; 207b8e80941Smrg int spill_size_per_thread; 208b8e80941Smrg}; 209b8e80941Smrg 210b8e80941Smrgstruct v3d_constbuf_stateobj { 211b8e80941Smrg struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 212b8e80941Smrg uint32_t enabled_mask; 213b8e80941Smrg uint32_t dirty_mask; 214b8e80941Smrg}; 215b8e80941Smrg 216b8e80941Smrgstruct v3d_vertexbuf_stateobj { 217b8e80941Smrg struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 218b8e80941Smrg unsigned count; 219b8e80941Smrg uint32_t enabled_mask; 220b8e80941Smrg uint32_t dirty_mask; 221b8e80941Smrg}; 222b8e80941Smrg 223b8e80941Smrgstruct v3d_vertex_stateobj { 224b8e80941Smrg struct pipe_vertex_element pipe[V3D_MAX_VS_INPUTS / 4]; 225b8e80941Smrg unsigned num_elements; 226b8e80941Smrg 227b8e80941Smrg uint8_t attrs[16 * (V3D_MAX_VS_INPUTS / 4)]; 228b8e80941Smrg struct pipe_resource *defaults; 229b8e80941Smrg uint32_t defaults_offset; 230b8e80941Smrg}; 231b8e80941Smrg 232b8e80941Smrgstruct v3d_streamout_stateobj { 233b8e80941Smrg struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS]; 234b8e80941Smrg /* Number of vertices we've written into the buffer so far. */ 235b8e80941Smrg uint32_t offsets[PIPE_MAX_SO_BUFFERS]; 236b8e80941Smrg unsigned num_targets; 237b8e80941Smrg}; 238b8e80941Smrg 239b8e80941Smrgstruct v3d_ssbo_stateobj { 240b8e80941Smrg struct pipe_shader_buffer sb[PIPE_MAX_SHADER_BUFFERS]; 241b8e80941Smrg uint32_t enabled_mask; 242b8e80941Smrg}; 243b8e80941Smrg 244b8e80941Smrg/* Hash table key for v3d->jobs */ 245b8e80941Smrgstruct v3d_job_key { 246b8e80941Smrg struct pipe_surface *cbufs[4]; 247b8e80941Smrg struct pipe_surface *zsbuf; 248b8e80941Smrg}; 249b8e80941Smrg 250b8e80941Smrgenum v3d_ez_state { 251b8e80941Smrg VC5_EZ_UNDECIDED = 0, 252b8e80941Smrg VC5_EZ_GT_GE, 253b8e80941Smrg VC5_EZ_LT_LE, 254b8e80941Smrg VC5_EZ_DISABLED, 255b8e80941Smrg}; 256b8e80941Smrg 257b8e80941Smrgstruct v3d_image_view { 258b8e80941Smrg struct pipe_image_view base; 259b8e80941Smrg /* V3D 4.x texture shader state struct */ 260b8e80941Smrg struct pipe_resource *tex_state; 261b8e80941Smrg uint32_t tex_state_offset; 262b8e80941Smrg}; 263b8e80941Smrg 264b8e80941Smrgstruct v3d_shaderimg_stateobj { 265b8e80941Smrg struct v3d_image_view si[PIPE_MAX_SHADER_IMAGES]; 266b8e80941Smrg uint32_t enabled_mask; 267b8e80941Smrg}; 268b8e80941Smrg 269b8e80941Smrg/** 270b8e80941Smrg * A complete bin/render job. 271b8e80941Smrg * 272b8e80941Smrg * This is all of the state necessary to submit a bin/render to the kernel. 273b8e80941Smrg * We want to be able to have multiple in progress at a time, so that we don't 274b8e80941Smrg * need to flush an existing CL just to switch to rendering to a new render 275b8e80941Smrg * target (which would mean reading back from the old render target when 276b8e80941Smrg * starting to render to it again). 277b8e80941Smrg */ 278b8e80941Smrgstruct v3d_job { 279b8e80941Smrg struct v3d_context *v3d; 280b8e80941Smrg struct v3d_cl bcl; 281b8e80941Smrg struct v3d_cl rcl; 282b8e80941Smrg struct v3d_cl indirect; 283b8e80941Smrg struct v3d_bo *tile_alloc; 284b8e80941Smrg struct v3d_bo *tile_state; 285b8e80941Smrg uint32_t shader_rec_count; 286b8e80941Smrg 287b8e80941Smrg struct drm_v3d_submit_cl submit; 288b8e80941Smrg 289b8e80941Smrg /** 290b8e80941Smrg * Set of all BOs referenced by the job. This will be used for making 291b8e80941Smrg * the list of BOs that the kernel will need to have paged in to 292b8e80941Smrg * execute our job. 293b8e80941Smrg */ 294b8e80941Smrg struct set *bos; 295b8e80941Smrg 296b8e80941Smrg /** Sum of the sizes of the BOs referenced by the job. */ 297b8e80941Smrg uint32_t referenced_size; 298b8e80941Smrg 299b8e80941Smrg struct set *write_prscs; 300b8e80941Smrg 301b8e80941Smrg /* Size of the submit.bo_handles array. */ 302b8e80941Smrg uint32_t bo_handles_size; 303b8e80941Smrg 304b8e80941Smrg /** @{ Surfaces to submit rendering for. */ 305b8e80941Smrg struct pipe_surface *cbufs[4]; 306b8e80941Smrg struct pipe_surface *zsbuf; 307b8e80941Smrg /** @} */ 308b8e80941Smrg /** @{ 309b8e80941Smrg * Bounding box of the scissor across all queued drawing. 310b8e80941Smrg * 311b8e80941Smrg * Note that the max values are exclusive. 312b8e80941Smrg */ 313b8e80941Smrg uint32_t draw_min_x; 314b8e80941Smrg uint32_t draw_min_y; 315b8e80941Smrg uint32_t draw_max_x; 316b8e80941Smrg uint32_t draw_max_y; 317b8e80941Smrg /** @} */ 318b8e80941Smrg /** @{ 319b8e80941Smrg * Width/height of the color framebuffer being rendered to, 320b8e80941Smrg * for VC5_TILE_RENDERING_MODE_CONFIG. 321b8e80941Smrg */ 322b8e80941Smrg uint32_t draw_width; 323b8e80941Smrg uint32_t draw_height; 324b8e80941Smrg /** @} */ 325b8e80941Smrg /** @{ Tile information, depending on MSAA and float color buffer. */ 326b8e80941Smrg uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */ 327b8e80941Smrg uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */ 328b8e80941Smrg 329b8e80941Smrg uint32_t tile_width; /** @< Width of a tile. */ 330b8e80941Smrg uint32_t tile_height; /** @< Height of a tile. */ 331b8e80941Smrg /** maximum internal_bpp of all color render targets. */ 332b8e80941Smrg uint32_t internal_bpp; 333b8e80941Smrg 334b8e80941Smrg /** Whether the current rendering is in a 4X MSAA tile buffer. */ 335b8e80941Smrg bool msaa; 336b8e80941Smrg /** @} */ 337b8e80941Smrg 338b8e80941Smrg /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the 339b8e80941Smrg * first rendering. 340b8e80941Smrg */ 341b8e80941Smrg uint32_t clear; 342b8e80941Smrg /* Bitmask of PIPE_CLEAR_* of buffers that have been read by a draw 343b8e80941Smrg * call without having been cleared first. 344b8e80941Smrg */ 345b8e80941Smrg uint32_t load; 346b8e80941Smrg /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to 347b8e80941Smrg * (either clears or draws) and should be stored. 348b8e80941Smrg */ 349b8e80941Smrg uint32_t store; 350b8e80941Smrg uint32_t clear_color[4][4]; 351b8e80941Smrg float clear_z; 352b8e80941Smrg uint8_t clear_s; 353b8e80941Smrg 354b8e80941Smrg /** 355b8e80941Smrg * Set if some drawing (triangles, blits, or just a glClear()) has 356b8e80941Smrg * been done to the FBO, meaning that we need to 357b8e80941Smrg * DRM_IOCTL_VC5_SUBMIT_CL. 358b8e80941Smrg */ 359b8e80941Smrg bool needs_flush; 360b8e80941Smrg 361b8e80941Smrg /* Set if any shader has dirtied cachelines in the TMU that need to be 362b8e80941Smrg * flushed before job end. 363b8e80941Smrg */ 364b8e80941Smrg bool tmu_dirty_rcl; 365b8e80941Smrg 366b8e80941Smrg /** 367b8e80941Smrg * Set if a packet enabling TF has been emitted in the job (V3D 4.x). 368b8e80941Smrg */ 369b8e80941Smrg bool tf_enabled; 370b8e80941Smrg 371b8e80941Smrg /** 372b8e80941Smrg * Current EZ state for drawing. Updated at the start of draw after 373b8e80941Smrg * we've decided on the shader being rendered. 374b8e80941Smrg */ 375b8e80941Smrg enum v3d_ez_state ez_state; 376b8e80941Smrg /** 377b8e80941Smrg * The first EZ state that was used for drawing with a decided EZ 378b8e80941Smrg * direction (so either UNDECIDED, GT, or LT). 379b8e80941Smrg */ 380b8e80941Smrg enum v3d_ez_state first_ez_state; 381b8e80941Smrg 382b8e80941Smrg /** 383b8e80941Smrg * Number of draw calls (not counting full buffer clears) queued in 384b8e80941Smrg * the current job. 385b8e80941Smrg */ 386b8e80941Smrg uint32_t draw_calls_queued; 387b8e80941Smrg 388b8e80941Smrg struct v3d_job_key key; 389b8e80941Smrg}; 390b8e80941Smrg 391b8e80941Smrgstruct v3d_context { 392b8e80941Smrg struct pipe_context base; 393b8e80941Smrg 394b8e80941Smrg int fd; 395b8e80941Smrg struct v3d_screen *screen; 396b8e80941Smrg 397b8e80941Smrg /** The 3D rendering job for the currently bound FBO. */ 398b8e80941Smrg struct v3d_job *job; 399b8e80941Smrg 400b8e80941Smrg /* Map from struct v3d_job_key to the job for that FBO. 401b8e80941Smrg */ 402b8e80941Smrg struct hash_table *jobs; 403b8e80941Smrg 404b8e80941Smrg /** 405b8e80941Smrg * Map from v3d_resource to a job writing to that resource. 406b8e80941Smrg * 407b8e80941Smrg * Primarily for flushing jobs rendering to textures that are now 408b8e80941Smrg * being read from. 409b8e80941Smrg */ 410b8e80941Smrg struct hash_table *write_jobs; 411b8e80941Smrg 412b8e80941Smrg struct slab_child_pool transfer_pool; 413b8e80941Smrg struct blitter_context *blitter; 414b8e80941Smrg 415b8e80941Smrg /** bitfield of VC5_DIRTY_* */ 416b8e80941Smrg uint32_t dirty; 417b8e80941Smrg 418b8e80941Smrg struct primconvert_context *primconvert; 419b8e80941Smrg 420b8e80941Smrg uint32_t next_uncompiled_program_id; 421b8e80941Smrg uint64_t next_compiled_program_id; 422b8e80941Smrg 423b8e80941Smrg struct v3d_compiler_state *compiler_state; 424b8e80941Smrg 425b8e80941Smrg uint8_t prim_mode; 426b8e80941Smrg 427b8e80941Smrg /** Maximum index buffer valid for the current shader_rec. */ 428b8e80941Smrg uint32_t max_index; 429b8e80941Smrg 430b8e80941Smrg /** Sync object that our RCL or TFU job will update as its out_sync. */ 431b8e80941Smrg uint32_t out_sync; 432b8e80941Smrg 433b8e80941Smrg /* Stream uploader used by gallium internals. This could also be used 434b8e80941Smrg * by driver internals, but we tend to use the v3d_cl.h interfaces 435b8e80941Smrg * instead. 436b8e80941Smrg */ 437b8e80941Smrg struct u_upload_mgr *uploader; 438b8e80941Smrg /* State uploader used inside the driver. This is for packing bits of 439b8e80941Smrg * long-term state inside buffers, since the kernel interfaces 440b8e80941Smrg * allocate a page at a time. 441b8e80941Smrg */ 442b8e80941Smrg struct u_upload_mgr *state_uploader; 443b8e80941Smrg 444b8e80941Smrg /** @{ Current pipeline state objects */ 445b8e80941Smrg struct pipe_scissor_state scissor; 446b8e80941Smrg struct v3d_blend_state *blend; 447b8e80941Smrg struct v3d_rasterizer_state *rasterizer; 448b8e80941Smrg struct v3d_depth_stencil_alpha_state *zsa; 449b8e80941Smrg 450b8e80941Smrg struct v3d_program_stateobj prog; 451b8e80941Smrg uint32_t compute_num_workgroups[3]; 452b8e80941Smrg struct v3d_bo *compute_shared_memory; 453b8e80941Smrg 454b8e80941Smrg struct v3d_vertex_stateobj *vtx; 455b8e80941Smrg 456b8e80941Smrg struct { 457b8e80941Smrg struct pipe_blend_color f; 458b8e80941Smrg uint16_t hf[4]; 459b8e80941Smrg } blend_color; 460b8e80941Smrg struct pipe_stencil_ref stencil_ref; 461b8e80941Smrg unsigned sample_mask; 462b8e80941Smrg struct pipe_framebuffer_state framebuffer; 463b8e80941Smrg 464b8e80941Smrg /* Per render target, whether we should swap the R and B fields in the 465b8e80941Smrg * shader's color output and in blending. If render targets disagree 466b8e80941Smrg * on the R/B swap and use the constant color, then we would need to 467b8e80941Smrg * fall back to in-shader blending. 468b8e80941Smrg */ 469b8e80941Smrg uint8_t swap_color_rb; 470b8e80941Smrg 471b8e80941Smrg /* Per render target, whether we should treat the dst alpha values as 472b8e80941Smrg * one in blending. 473b8e80941Smrg * 474b8e80941Smrg * For RGBX formats, the tile buffer's alpha channel will be 475b8e80941Smrg * undefined. 476b8e80941Smrg */ 477b8e80941Smrg uint8_t blend_dst_alpha_one; 478b8e80941Smrg 479b8e80941Smrg bool active_queries; 480b8e80941Smrg 481b8e80941Smrg uint32_t tf_prims_generated; 482b8e80941Smrg uint32_t prims_generated; 483b8e80941Smrg 484b8e80941Smrg struct pipe_poly_stipple stipple; 485b8e80941Smrg struct pipe_clip_state clip; 486b8e80941Smrg struct pipe_viewport_state viewport; 487b8e80941Smrg struct v3d_ssbo_stateobj ssbo[PIPE_SHADER_TYPES]; 488b8e80941Smrg struct v3d_shaderimg_stateobj shaderimg[PIPE_SHADER_TYPES]; 489b8e80941Smrg struct v3d_constbuf_stateobj constbuf[PIPE_SHADER_TYPES]; 490b8e80941Smrg struct v3d_texture_stateobj tex[PIPE_SHADER_TYPES]; 491b8e80941Smrg struct v3d_vertexbuf_stateobj vertexbuf; 492b8e80941Smrg struct v3d_streamout_stateobj streamout; 493b8e80941Smrg struct v3d_bo *current_oq; 494b8e80941Smrg struct pipe_debug_callback debug; 495b8e80941Smrg /** @} */ 496b8e80941Smrg}; 497b8e80941Smrg 498b8e80941Smrgstruct v3d_rasterizer_state { 499b8e80941Smrg struct pipe_rasterizer_state base; 500b8e80941Smrg 501b8e80941Smrg float point_size; 502b8e80941Smrg 503b8e80941Smrg uint8_t depth_offset[9]; 504b8e80941Smrg uint8_t depth_offset_z16[9]; 505b8e80941Smrg}; 506b8e80941Smrg 507b8e80941Smrgstruct v3d_depth_stencil_alpha_state { 508b8e80941Smrg struct pipe_depth_stencil_alpha_state base; 509b8e80941Smrg 510b8e80941Smrg enum v3d_ez_state ez_state; 511b8e80941Smrg 512b8e80941Smrg uint8_t stencil_front[6]; 513b8e80941Smrg uint8_t stencil_back[6]; 514b8e80941Smrg}; 515b8e80941Smrg 516b8e80941Smrgstruct v3d_blend_state { 517b8e80941Smrg struct pipe_blend_state base; 518b8e80941Smrg 519b8e80941Smrg /* Per-RT mask of whether blending is enabled. */ 520b8e80941Smrg uint8_t blend_enables; 521b8e80941Smrg}; 522b8e80941Smrg 523b8e80941Smrg#define perf_debug(...) do { \ 524b8e80941Smrg if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF)) \ 525b8e80941Smrg fprintf(stderr, __VA_ARGS__); \ 526b8e80941Smrg if (unlikely(v3d->debug.debug_message)) \ 527b8e80941Smrg pipe_debug_message(&v3d->debug, PERF_INFO, __VA_ARGS__); \ 528b8e80941Smrg} while (0) 529b8e80941Smrg 530b8e80941Smrg#define foreach_bit(b, mask) \ 531b8e80941Smrg for (uint32_t _m = (mask), b; _m && ({(b) = u_bit_scan(&_m); 1;});) 532b8e80941Smrg 533b8e80941Smrgstatic inline struct v3d_context * 534b8e80941Smrgv3d_context(struct pipe_context *pcontext) 535b8e80941Smrg{ 536b8e80941Smrg return (struct v3d_context *)pcontext; 537b8e80941Smrg} 538b8e80941Smrg 539b8e80941Smrgstatic inline struct v3d_sampler_view * 540b8e80941Smrgv3d_sampler_view(struct pipe_sampler_view *psview) 541b8e80941Smrg{ 542b8e80941Smrg return (struct v3d_sampler_view *)psview; 543b8e80941Smrg} 544b8e80941Smrg 545b8e80941Smrgstatic inline struct v3d_sampler_state * 546b8e80941Smrgv3d_sampler_state(struct pipe_sampler_state *psampler) 547b8e80941Smrg{ 548b8e80941Smrg return (struct v3d_sampler_state *)psampler; 549b8e80941Smrg} 550b8e80941Smrg 551b8e80941Smrgstruct pipe_context *v3d_context_create(struct pipe_screen *pscreen, 552b8e80941Smrg void *priv, unsigned flags); 553b8e80941Smrgvoid v3d_program_init(struct pipe_context *pctx); 554b8e80941Smrgvoid v3d_program_fini(struct pipe_context *pctx); 555b8e80941Smrgvoid v3d_query_init(struct pipe_context *pctx); 556b8e80941Smrg 557b8e80941Smrgvoid v3d_simulator_init(struct v3d_screen *screen); 558b8e80941Smrgvoid v3d_simulator_destroy(struct v3d_screen *screen); 559b8e80941Smrguint32_t v3d_simulator_get_spill(uint32_t spill_size); 560b8e80941Smrgint v3d_simulator_ioctl(int fd, unsigned long request, void *arg); 561b8e80941Smrgvoid v3d_simulator_open_from_handle(int fd, int handle, uint32_t size); 562b8e80941Smrg 563b8e80941Smrgstatic inline int 564b8e80941Smrgv3d_ioctl(int fd, unsigned long request, void *arg) 565b8e80941Smrg{ 566b8e80941Smrg if (using_v3d_simulator) 567b8e80941Smrg return v3d_simulator_ioctl(fd, request, arg); 568b8e80941Smrg else 569b8e80941Smrg return drmIoctl(fd, request, arg); 570b8e80941Smrg} 571b8e80941Smrg 572b8e80941Smrgvoid v3d_set_shader_uniform_dirty_flags(struct v3d_compiled_shader *shader); 573b8e80941Smrgstruct v3d_cl_reloc v3d_write_uniforms(struct v3d_context *v3d, 574b8e80941Smrg struct v3d_compiled_shader *shader, 575b8e80941Smrg enum pipe_shader_type stage); 576b8e80941Smrg 577b8e80941Smrgvoid v3d_flush(struct pipe_context *pctx); 578b8e80941Smrgvoid v3d_job_init(struct v3d_context *v3d); 579b8e80941Smrgstruct v3d_job *v3d_get_job(struct v3d_context *v3d, 580b8e80941Smrg struct pipe_surface **cbufs, 581b8e80941Smrg struct pipe_surface *zsbuf); 582b8e80941Smrgstruct v3d_job *v3d_get_job_for_fbo(struct v3d_context *v3d); 583b8e80941Smrgvoid v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo); 584b8e80941Smrgvoid v3d_job_add_write_resource(struct v3d_job *job, struct pipe_resource *prsc); 585b8e80941Smrgvoid v3d_job_submit(struct v3d_context *v3d, struct v3d_job *job); 586b8e80941Smrgvoid v3d_flush_jobs_writing_resource(struct v3d_context *v3d, 587b8e80941Smrg struct pipe_resource *prsc); 588b8e80941Smrgvoid v3d_flush_jobs_reading_resource(struct v3d_context *v3d, 589b8e80941Smrg struct pipe_resource *prsc); 590b8e80941Smrgvoid v3d_update_compiled_shaders(struct v3d_context *v3d, uint8_t prim_mode); 591b8e80941Smrgvoid v3d_update_compiled_cs(struct v3d_context *v3d); 592b8e80941Smrg 593b8e80941Smrgbool v3d_rt_format_supported(const struct v3d_device_info *devinfo, 594b8e80941Smrg enum pipe_format f); 595b8e80941Smrgbool v3d_tex_format_supported(const struct v3d_device_info *devinfo, 596b8e80941Smrg enum pipe_format f); 597b8e80941Smrguint8_t v3d_get_rt_format(const struct v3d_device_info *devinfo, enum pipe_format f); 598b8e80941Smrguint8_t v3d_get_tex_format(const struct v3d_device_info *devinfo, enum pipe_format f); 599b8e80941Smrguint8_t v3d_get_tex_return_size(const struct v3d_device_info *devinfo, 600b8e80941Smrg enum pipe_format f, 601b8e80941Smrg enum pipe_tex_compare compare); 602b8e80941Smrguint8_t v3d_get_tex_return_channels(const struct v3d_device_info *devinfo, 603b8e80941Smrg enum pipe_format f); 604b8e80941Smrgconst uint8_t *v3d_get_format_swizzle(const struct v3d_device_info *devinfo, 605b8e80941Smrg enum pipe_format f); 606b8e80941Smrgvoid v3d_get_internal_type_bpp_for_output_format(const struct v3d_device_info *devinfo, 607b8e80941Smrg uint32_t format, 608b8e80941Smrg uint32_t *type, 609b8e80941Smrg uint32_t *bpp); 610b8e80941Smrgbool v3d_tfu_supports_tex_format(const struct v3d_device_info *devinfo, 611b8e80941Smrg uint32_t tex_format); 612b8e80941Smrg 613b8e80941Smrgvoid v3d_init_query_functions(struct v3d_context *v3d); 614b8e80941Smrgvoid v3d_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info); 615b8e80941Smrgvoid v3d_blitter_save(struct v3d_context *v3d); 616b8e80941Smrgboolean v3d_generate_mipmap(struct pipe_context *pctx, 617b8e80941Smrg struct pipe_resource *prsc, 618b8e80941Smrg enum pipe_format format, 619b8e80941Smrg unsigned int base_level, 620b8e80941Smrg unsigned int last_level, 621b8e80941Smrg unsigned int first_layer, 622b8e80941Smrg unsigned int last_layer); 623b8e80941Smrg 624b8e80941Smrgstruct v3d_fence *v3d_fence_create(struct v3d_context *v3d); 625b8e80941Smrg 626b8e80941Smrg#ifdef v3dX 627b8e80941Smrg# include "v3dx_context.h" 628b8e80941Smrg#else 629b8e80941Smrg# define v3dX(x) v3d33_##x 630b8e80941Smrg# include "v3dx_context.h" 631b8e80941Smrg# undef v3dX 632b8e80941Smrg 633b8e80941Smrg# define v3dX(x) v3d41_##x 634b8e80941Smrg# include "v3dx_context.h" 635b8e80941Smrg# undef v3dX 636b8e80941Smrg#endif 637b8e80941Smrg 638b8e80941Smrg#endif /* VC5_CONTEXT_H */ 639