1/* 2 * Copyright 2014, 2015 Red Hat. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef VIRGL_HW_H 24#define VIRGL_HW_H 25 26struct virgl_box { 27 uint32_t x, y, z; 28 uint32_t w, h, d; 29}; 30 31/* formats known by the HW device - based on gallium subset */ 32enum virgl_formats { 33 VIRGL_FORMAT_B8G8R8A8_UNORM = 1, 34 VIRGL_FORMAT_B8G8R8X8_UNORM = 2, 35 VIRGL_FORMAT_A8R8G8B8_UNORM = 3, 36 VIRGL_FORMAT_X8R8G8B8_UNORM = 4, 37 VIRGL_FORMAT_B5G5R5A1_UNORM = 5, 38 VIRGL_FORMAT_B4G4R4A4_UNORM = 6, 39 VIRGL_FORMAT_B5G6R5_UNORM = 7, 40 VIRGL_FORMAT_R10G10B10A2_UNORM = 8, 41 VIRGL_FORMAT_L8_UNORM = 9, /**< ubyte luminance */ 42 VIRGL_FORMAT_A8_UNORM = 10, /**< ubyte alpha */ 43 VIRGL_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */ 44 VIRGL_FORMAT_L16_UNORM = 13, /**< ushort luminance */ 45 46 VIRGL_FORMAT_Z16_UNORM = 16, 47 VIRGL_FORMAT_Z32_UNORM = 17, 48 VIRGL_FORMAT_Z32_FLOAT = 18, 49 VIRGL_FORMAT_Z24_UNORM_S8_UINT = 19, 50 VIRGL_FORMAT_S8_UINT_Z24_UNORM = 20, 51 VIRGL_FORMAT_Z24X8_UNORM = 21, 52 VIRGL_FORMAT_S8_UINT = 23, /**< ubyte stencil */ 53 54 VIRGL_FORMAT_R32_FLOAT = 28, 55 VIRGL_FORMAT_R32G32_FLOAT = 29, 56 VIRGL_FORMAT_R32G32B32_FLOAT = 30, 57 VIRGL_FORMAT_R32G32B32A32_FLOAT = 31, 58 59 VIRGL_FORMAT_R16_UNORM = 48, 60 VIRGL_FORMAT_R16G16_UNORM = 49, 61 62 VIRGL_FORMAT_R16G16B16A16_UNORM = 51, 63 64 VIRGL_FORMAT_R16_SNORM = 56, 65 VIRGL_FORMAT_R16G16_SNORM = 57, 66 VIRGL_FORMAT_R16G16B16A16_SNORM = 59, 67 68 VIRGL_FORMAT_R8_UNORM = 64, 69 VIRGL_FORMAT_R8G8_UNORM = 65, 70 71 VIRGL_FORMAT_R8G8B8A8_UNORM = 67, 72 73 VIRGL_FORMAT_R8_SNORM = 74, 74 VIRGL_FORMAT_R8G8_SNORM = 75, 75 VIRGL_FORMAT_R8G8B8_SNORM = 76, 76 VIRGL_FORMAT_R8G8B8A8_SNORM = 77, 77 78 VIRGL_FORMAT_R16_FLOAT = 91, 79 VIRGL_FORMAT_R16G16_FLOAT = 92, 80 VIRGL_FORMAT_R16G16B16_FLOAT = 93, 81 VIRGL_FORMAT_R16G16B16A16_FLOAT = 94, 82 83 VIRGL_FORMAT_L8_SRGB = 95, 84 VIRGL_FORMAT_L8A8_SRGB = 96, 85 VIRGL_FORMAT_B8G8R8A8_SRGB = 100, 86 VIRGL_FORMAT_B8G8R8X8_SRGB = 101, 87 VIRGL_FORMAT_R8G8B8A8_SRGB = 104, 88 89 /* compressed formats */ 90 VIRGL_FORMAT_DXT1_RGB = 105, 91 VIRGL_FORMAT_DXT1_RGBA = 106, 92 VIRGL_FORMAT_DXT3_RGBA = 107, 93 VIRGL_FORMAT_DXT5_RGBA = 108, 94 95 /* sRGB, compressed */ 96 VIRGL_FORMAT_DXT1_SRGB = 109, 97 VIRGL_FORMAT_DXT1_SRGBA = 110, 98 VIRGL_FORMAT_DXT3_SRGBA = 111, 99 VIRGL_FORMAT_DXT5_SRGBA = 112, 100 101 /* rgtc compressed */ 102 VIRGL_FORMAT_RGTC1_UNORM = 113, 103 VIRGL_FORMAT_RGTC1_SNORM = 114, 104 VIRGL_FORMAT_RGTC2_UNORM = 115, 105 VIRGL_FORMAT_RGTC2_SNORM = 116, 106 107 VIRGL_FORMAT_A8B8G8R8_UNORM = 121, 108 VIRGL_FORMAT_B5G5R5X1_UNORM = 122, 109 VIRGL_FORMAT_R11G11B10_FLOAT = 124, 110 VIRGL_FORMAT_R9G9B9E5_FLOAT = 125, 111 VIRGL_FORMAT_Z32_FLOAT_S8X24_UINT = 126, 112 113 VIRGL_FORMAT_B10G10R10A2_UNORM = 131, 114 VIRGL_FORMAT_R8G8B8X8_UNORM = 134, 115 VIRGL_FORMAT_B4G4R4X4_UNORM = 135, 116 VIRGL_FORMAT_X24S8_UINT = 136, 117 VIRGL_FORMAT_S8X24_UINT = 137, 118 VIRGL_FORMAT_B2G3R3_UNORM = 139, 119 120 VIRGL_FORMAT_L16A16_UNORM = 140, 121 VIRGL_FORMAT_A16_UNORM = 141, 122 123 VIRGL_FORMAT_A8_SNORM = 147, 124 VIRGL_FORMAT_L8_SNORM = 148, 125 VIRGL_FORMAT_L8A8_SNORM = 149, 126 127 VIRGL_FORMAT_A16_SNORM = 151, 128 VIRGL_FORMAT_L16_SNORM = 152, 129 VIRGL_FORMAT_L16A16_SNORM = 153, 130 131 VIRGL_FORMAT_A16_FLOAT = 155, 132 VIRGL_FORMAT_L16_FLOAT = 156, 133 VIRGL_FORMAT_L16A16_FLOAT = 157, 134 135 VIRGL_FORMAT_A32_FLOAT = 159, 136 VIRGL_FORMAT_L32_FLOAT = 160, 137 VIRGL_FORMAT_L32A32_FLOAT = 161, 138 139 VIRGL_FORMAT_R8_UINT = 177, 140 VIRGL_FORMAT_R8G8_UINT = 178, 141 VIRGL_FORMAT_R8G8B8_UINT = 179, 142 VIRGL_FORMAT_R8G8B8A8_UINT = 180, 143 144 VIRGL_FORMAT_R8_SINT = 181, 145 VIRGL_FORMAT_R8G8_SINT = 182, 146 VIRGL_FORMAT_R8G8B8_SINT = 183, 147 VIRGL_FORMAT_R8G8B8A8_SINT = 184, 148 149 VIRGL_FORMAT_R16_UINT = 185, 150 VIRGL_FORMAT_R16G16_UINT = 186, 151 VIRGL_FORMAT_R16G16B16_UINT = 187, 152 VIRGL_FORMAT_R16G16B16A16_UINT = 188, 153 154 VIRGL_FORMAT_R16_SINT = 189, 155 VIRGL_FORMAT_R16G16_SINT = 190, 156 VIRGL_FORMAT_R16G16B16_SINT = 191, 157 VIRGL_FORMAT_R16G16B16A16_SINT = 192, 158 VIRGL_FORMAT_R32_UINT = 193, 159 VIRGL_FORMAT_R32G32_UINT = 194, 160 VIRGL_FORMAT_R32G32B32_UINT = 195, 161 VIRGL_FORMAT_R32G32B32A32_UINT = 196, 162 163 VIRGL_FORMAT_R32_SINT = 197, 164 VIRGL_FORMAT_R32G32_SINT = 198, 165 VIRGL_FORMAT_R32G32B32_SINT = 199, 166 VIRGL_FORMAT_R32G32B32A32_SINT = 200, 167 168 VIRGL_FORMAT_A8_UINT = 201, 169 VIRGL_FORMAT_L8_UINT = 203, 170 VIRGL_FORMAT_L8A8_UINT = 204, 171 172 VIRGL_FORMAT_A8_SINT = 205, 173 VIRGL_FORMAT_L8_SINT = 207, 174 VIRGL_FORMAT_L8A8_SINT = 208, 175 176 VIRGL_FORMAT_A16_UINT = 209, 177 VIRGL_FORMAT_L16_UINT = 211, 178 VIRGL_FORMAT_L16A16_UINT = 212, 179 180 VIRGL_FORMAT_A16_SINT = 213, 181 VIRGL_FORMAT_L16_SINT = 215, 182 VIRGL_FORMAT_L16A16_SINT = 216, 183 184 VIRGL_FORMAT_A32_UINT = 217, 185 VIRGL_FORMAT_L32_UINT = 219, 186 VIRGL_FORMAT_L32A32_UINT = 220, 187 188 VIRGL_FORMAT_A32_SINT = 221, 189 VIRGL_FORMAT_L32_SINT = 223, 190 VIRGL_FORMAT_L32A32_SINT = 224, 191 192 VIRGL_FORMAT_B10G10R10A2_UINT = 225, 193 VIRGL_FORMAT_R8G8B8X8_SNORM = 229, 194 195 VIRGL_FORMAT_R8G8B8X8_SRGB = 230, 196 197 VIRGL_FORMAT_R8G8B8X8_UINT = 231, 198 VIRGL_FORMAT_R8G8B8X8_SINT = 232, 199 VIRGL_FORMAT_B10G10R10X2_UNORM = 233, 200 VIRGL_FORMAT_R16G16B16X16_UNORM = 234, 201 VIRGL_FORMAT_R16G16B16X16_SNORM = 235, 202 VIRGL_FORMAT_R16G16B16X16_FLOAT = 236, 203 VIRGL_FORMAT_R16G16B16X16_UINT = 237, 204 VIRGL_FORMAT_R16G16B16X16_SINT = 238, 205 206 VIRGL_FORMAT_R10G10B10A2_UINT = 253, 207 208 VIRGL_FORMAT_BPTC_RGBA_UNORM = 255, 209 VIRGL_FORMAT_BPTC_SRGBA = 256, 210 VIRGL_FORMAT_BPTC_RGB_FLOAT = 257, 211 VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258, 212 213 VIRGL_FORMAT_R10G10B10X2_UNORM = 308, 214 VIRGL_FORMAT_A4B4G4R4_UNORM = 311, 215 VIRGL_FORMAT_MAX, 216}; 217 218/* These are used by the capability_bits field in virgl_caps_v2. */ 219#define VIRGL_CAP_NONE 0 220#define VIRGL_CAP_TGSI_INVARIANT (1 << 0) 221#define VIRGL_CAP_TEXTURE_VIEW (1 << 1) 222#define VIRGL_CAP_SET_MIN_SAMPLES (1 << 2) 223#define VIRGL_CAP_COPY_IMAGE (1 << 3) 224#define VIRGL_CAP_TGSI_PRECISE (1 << 4) 225#define VIRGL_CAP_TXQS (1 << 5) 226#define VIRGL_CAP_MEMORY_BARRIER (1 << 6) 227#define VIRGL_CAP_COMPUTE_SHADER (1 << 7) 228#define VIRGL_CAP_FB_NO_ATTACH (1 << 8) 229#define VIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9) 230#define VIRGL_CAP_TGSI_FBFETCH (1 << 10) 231#define VIRGL_CAP_SHADER_CLOCK (1 << 11) 232#define VIRGL_CAP_TEXTURE_BARRIER (1 << 12) 233#define VIRGL_CAP_TGSI_COMPONENTS (1 << 13) 234#define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14) 235#define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15) 236#define VIRGL_CAP_QBO (1 << 16) 237#define VIRGL_CAP_TRANSFER (1 << 17) 238#define VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18) 239#define VIRGL_CAP_FAKE_FP64 (1 << 19) 240#define VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20) 241#define VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21) 242#define VIRGL_CAP_INDIRECT_PARAMS (1 << 22) 243#define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23) 244#define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25) 245 246 247/* virgl bind flags - these are compatible with mesa 10.5 gallium. 248 * but are fixed, no other should be passed to virgl either. 249 */ 250#define VIRGL_BIND_DEPTH_STENCIL (1 << 0) 251#define VIRGL_BIND_RENDER_TARGET (1 << 1) 252#define VIRGL_BIND_SAMPLER_VIEW (1 << 3) 253#define VIRGL_BIND_VERTEX_BUFFER (1 << 4) 254#define VIRGL_BIND_INDEX_BUFFER (1 << 5) 255#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6) 256#define VIRGL_BIND_DISPLAY_TARGET (1 << 7) 257#define VIRGL_BIND_COMMAND_ARGS (1 << 8) 258#define VIRGL_BIND_STREAM_OUTPUT (1 << 11) 259#define VIRGL_BIND_SHADER_BUFFER (1 << 14) 260#define VIRGL_BIND_QUERY_BUFFER (1 << 15) 261#define VIRGL_BIND_CURSOR (1 << 16) 262#define VIRGL_BIND_CUSTOM (1 << 17) 263#define VIRGL_BIND_SCANOUT (1 << 18) 264 265struct virgl_caps_bool_set1 { 266 unsigned indep_blend_enable:1; 267 unsigned indep_blend_func:1; 268 unsigned cube_map_array:1; 269 unsigned shader_stencil_export:1; 270 unsigned conditional_render:1; 271 unsigned start_instance:1; 272 unsigned primitive_restart:1; 273 unsigned blend_eq_sep:1; 274 unsigned instanceid:1; 275 unsigned vertex_element_instance_divisor:1; 276 unsigned seamless_cube_map:1; 277 unsigned occlusion_query:1; 278 unsigned timer_query:1; 279 unsigned streamout_pause_resume:1; 280 unsigned texture_multisample:1; 281 unsigned fragment_coord_conventions:1; 282 unsigned depth_clip_disable:1; 283 unsigned seamless_cube_map_per_texture:1; 284 unsigned ubo:1; 285 unsigned color_clamping:1; /* not in GL 3.1 core profile */ 286 unsigned poly_stipple:1; /* not in GL 3.1 core profile */ 287 unsigned mirror_clamp:1; 288 unsigned texture_query_lod:1; 289 unsigned has_fp64:1; 290 unsigned has_tessellation_shaders:1; 291 unsigned has_indirect_draw:1; 292 unsigned has_sample_shading:1; 293 unsigned has_cull:1; 294 unsigned conditional_render_inverted:1; 295 unsigned derivative_control:1; 296 unsigned polygon_offset_clamp:1; 297 unsigned transform_feedback_overflow_query:1; 298 /* DO NOT ADD ANYMORE MEMBERS - need to add another 32-bit to v2 caps */ 299}; 300 301/* endless expansion capabilites - current gallium has 252 formats */ 302struct virgl_supported_format_mask { 303 uint32_t bitmask[16]; 304}; 305/* capabilities set 2 - version 1 - 32-bit and float values */ 306struct virgl_caps_v1 { 307 uint32_t max_version; 308 struct virgl_supported_format_mask sampler; 309 struct virgl_supported_format_mask render; 310 struct virgl_supported_format_mask depthstencil; 311 struct virgl_supported_format_mask vertexbuffer; 312 struct virgl_caps_bool_set1 bset; 313 uint32_t glsl_level; 314 uint32_t max_texture_array_layers; 315 uint32_t max_streamout_buffers; 316 uint32_t max_dual_source_render_targets; 317 uint32_t max_render_targets; 318 uint32_t max_samples; 319 uint32_t prim_mask; 320 uint32_t max_tbo_size; 321 uint32_t max_uniform_blocks; 322 uint32_t max_viewports; 323 uint32_t max_texture_gather_components; 324}; 325 326/* 327 * This struct should be growable when used in capset 2, 328 * so we shouldn't have to add a v3 ever. 329 */ 330struct virgl_caps_v2 { 331 struct virgl_caps_v1 v1; 332 float min_aliased_point_size; 333 float max_aliased_point_size; 334 float min_smooth_point_size; 335 float max_smooth_point_size; 336 float min_aliased_line_width; 337 float max_aliased_line_width; 338 float min_smooth_line_width; 339 float max_smooth_line_width; 340 float max_texture_lod_bias; 341 uint32_t max_geom_output_vertices; 342 uint32_t max_geom_total_output_components; 343 uint32_t max_vertex_outputs; 344 uint32_t max_vertex_attribs; 345 uint32_t max_shader_patch_varyings; 346 int32_t min_texel_offset; 347 int32_t max_texel_offset; 348 int32_t min_texture_gather_offset; 349 int32_t max_texture_gather_offset; 350 uint32_t texture_buffer_offset_alignment; 351 uint32_t uniform_buffer_offset_alignment; 352 uint32_t shader_buffer_offset_alignment; 353 uint32_t capability_bits; 354 uint32_t sample_locations[8]; 355 uint32_t max_vertex_attrib_stride; 356 uint32_t max_shader_buffer_frag_compute; 357 uint32_t max_shader_buffer_other_stages; 358 uint32_t max_shader_image_frag_compute; 359 uint32_t max_shader_image_other_stages; 360 uint32_t max_image_samples; 361 uint32_t max_compute_work_group_invocations; 362 uint32_t max_compute_shared_memory_size; 363 uint32_t max_compute_grid_size[3]; 364 uint32_t max_compute_block_size[3]; 365 uint32_t max_texture_2d_size; 366 uint32_t max_texture_3d_size; 367 uint32_t max_texture_cube_size; 368 uint32_t max_combined_shader_buffers; 369 uint32_t max_atomic_counters[6]; 370 uint32_t max_atomic_counter_buffers[6]; 371 uint32_t max_combined_atomic_counters; 372 uint32_t max_combined_atomic_counter_buffers; 373 uint32_t host_feature_check_version; 374 struct virgl_supported_format_mask supported_readback_formats; 375}; 376 377union virgl_caps { 378 uint32_t max_version; 379 struct virgl_caps_v1 v1; 380 struct virgl_caps_v2 v2; 381}; 382 383enum virgl_errors { 384 VIRGL_ERROR_NONE, 385 VIRGL_ERROR_UNKNOWN, 386 VIRGL_ERROR_UNKNOWN_RESOURCE_FORMAT, 387}; 388 389enum virgl_ctx_errors { 390 VIRGL_ERROR_CTX_NONE, 391 VIRGL_ERROR_CTX_UNKNOWN, 392 VIRGL_ERROR_CTX_ILLEGAL_SHADER, 393 VIRGL_ERROR_CTX_ILLEGAL_HANDLE, 394 VIRGL_ERROR_CTX_ILLEGAL_RESOURCE, 395 VIRGL_ERROR_CTX_ILLEGAL_SURFACE, 396 VIRGL_ERROR_CTX_ILLEGAL_VERTEX_FORMAT, 397 VIRGL_ERROR_CTX_ILLEGAL_CMD_BUFFER, 398}; 399 400 401#define VIRGL_RESOURCE_Y_0_TOP (1 << 0) 402#endif 403