1/************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifndef PIPE_DEFINES_H 29#define PIPE_DEFINES_H 30 31#include "p_compiler.h" 32 33#ifdef __cplusplus 34extern "C" { 35#endif 36 37/** 38 * Gallium error codes. 39 * 40 * - A zero value always means success. 41 * - A negative value always means failure. 42 * - The meaning of a positive value is function dependent. 43 */ 44enum pipe_error 45{ 46 PIPE_OK = 0, 47 PIPE_ERROR = -1, /**< Generic error */ 48 PIPE_ERROR_BAD_INPUT = -2, 49 PIPE_ERROR_OUT_OF_MEMORY = -3, 50 PIPE_ERROR_RETRY = -4 51 /* TODO */ 52}; 53 54enum pipe_blendfactor { 55 PIPE_BLENDFACTOR_ONE = 1, 56 PIPE_BLENDFACTOR_SRC_COLOR, 57 PIPE_BLENDFACTOR_SRC_ALPHA, 58 PIPE_BLENDFACTOR_DST_ALPHA, 59 PIPE_BLENDFACTOR_DST_COLOR, 60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE, 61 PIPE_BLENDFACTOR_CONST_COLOR, 62 PIPE_BLENDFACTOR_CONST_ALPHA, 63 PIPE_BLENDFACTOR_SRC1_COLOR, 64 PIPE_BLENDFACTOR_SRC1_ALPHA, 65 66 PIPE_BLENDFACTOR_ZERO = 0x11, 67 PIPE_BLENDFACTOR_INV_SRC_COLOR, 68 PIPE_BLENDFACTOR_INV_SRC_ALPHA, 69 PIPE_BLENDFACTOR_INV_DST_ALPHA, 70 PIPE_BLENDFACTOR_INV_DST_COLOR, 71 72 PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17, 73 PIPE_BLENDFACTOR_INV_CONST_ALPHA, 74 PIPE_BLENDFACTOR_INV_SRC1_COLOR, 75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA, 76}; 77 78enum pipe_blend_func { 79 PIPE_BLEND_ADD, 80 PIPE_BLEND_SUBTRACT, 81 PIPE_BLEND_REVERSE_SUBTRACT, 82 PIPE_BLEND_MIN, 83 PIPE_BLEND_MAX, 84}; 85 86enum pipe_logicop { 87 PIPE_LOGICOP_CLEAR, 88 PIPE_LOGICOP_NOR, 89 PIPE_LOGICOP_AND_INVERTED, 90 PIPE_LOGICOP_COPY_INVERTED, 91 PIPE_LOGICOP_AND_REVERSE, 92 PIPE_LOGICOP_INVERT, 93 PIPE_LOGICOP_XOR, 94 PIPE_LOGICOP_NAND, 95 PIPE_LOGICOP_AND, 96 PIPE_LOGICOP_EQUIV, 97 PIPE_LOGICOP_NOOP, 98 PIPE_LOGICOP_OR_INVERTED, 99 PIPE_LOGICOP_COPY, 100 PIPE_LOGICOP_OR_REVERSE, 101 PIPE_LOGICOP_OR, 102 PIPE_LOGICOP_SET, 103}; 104 105#define PIPE_MASK_R 0x1 106#define PIPE_MASK_G 0x2 107#define PIPE_MASK_B 0x4 108#define PIPE_MASK_A 0x8 109#define PIPE_MASK_RGBA 0xf 110#define PIPE_MASK_Z 0x10 111#define PIPE_MASK_S 0x20 112#define PIPE_MASK_ZS 0x30 113#define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS) 114 115 116/** 117 * Inequality functions. Used for depth test, stencil compare, alpha 118 * test, shadow compare, etc. 119 */ 120enum pipe_compare_func { 121 PIPE_FUNC_NEVER, 122 PIPE_FUNC_LESS, 123 PIPE_FUNC_EQUAL, 124 PIPE_FUNC_LEQUAL, 125 PIPE_FUNC_GREATER, 126 PIPE_FUNC_NOTEQUAL, 127 PIPE_FUNC_GEQUAL, 128 PIPE_FUNC_ALWAYS, 129}; 130 131/** Polygon fill mode */ 132enum { 133 PIPE_POLYGON_MODE_FILL, 134 PIPE_POLYGON_MODE_LINE, 135 PIPE_POLYGON_MODE_POINT, 136 PIPE_POLYGON_MODE_FILL_RECTANGLE, 137}; 138 139/** Polygon face specification, eg for culling */ 140#define PIPE_FACE_NONE 0 141#define PIPE_FACE_FRONT 1 142#define PIPE_FACE_BACK 2 143#define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK) 144 145/** Stencil ops */ 146enum pipe_stencil_op { 147 PIPE_STENCIL_OP_KEEP, 148 PIPE_STENCIL_OP_ZERO, 149 PIPE_STENCIL_OP_REPLACE, 150 PIPE_STENCIL_OP_INCR, 151 PIPE_STENCIL_OP_DECR, 152 PIPE_STENCIL_OP_INCR_WRAP, 153 PIPE_STENCIL_OP_DECR_WRAP, 154 PIPE_STENCIL_OP_INVERT, 155}; 156 157/** Texture types. 158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D 159 */ 160enum pipe_texture_target 161{ 162 PIPE_BUFFER, 163 PIPE_TEXTURE_1D, 164 PIPE_TEXTURE_2D, 165 PIPE_TEXTURE_3D, 166 PIPE_TEXTURE_CUBE, 167 PIPE_TEXTURE_RECT, 168 PIPE_TEXTURE_1D_ARRAY, 169 PIPE_TEXTURE_2D_ARRAY, 170 PIPE_TEXTURE_CUBE_ARRAY, 171 PIPE_MAX_TEXTURE_TYPES, 172}; 173 174enum pipe_tex_face { 175 PIPE_TEX_FACE_POS_X, 176 PIPE_TEX_FACE_NEG_X, 177 PIPE_TEX_FACE_POS_Y, 178 PIPE_TEX_FACE_NEG_Y, 179 PIPE_TEX_FACE_POS_Z, 180 PIPE_TEX_FACE_NEG_Z, 181 PIPE_TEX_FACE_MAX, 182}; 183 184enum pipe_tex_wrap { 185 PIPE_TEX_WRAP_REPEAT, 186 PIPE_TEX_WRAP_CLAMP, 187 PIPE_TEX_WRAP_CLAMP_TO_EDGE, 188 PIPE_TEX_WRAP_CLAMP_TO_BORDER, 189 PIPE_TEX_WRAP_MIRROR_REPEAT, 190 PIPE_TEX_WRAP_MIRROR_CLAMP, 191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE, 192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER, 193}; 194 195/** Between mipmaps, ie mipfilter */ 196enum pipe_tex_mipfilter { 197 PIPE_TEX_MIPFILTER_NEAREST, 198 PIPE_TEX_MIPFILTER_LINEAR, 199 PIPE_TEX_MIPFILTER_NONE, 200}; 201 202/** Within a mipmap, ie min/mag filter */ 203enum pipe_tex_filter { 204 PIPE_TEX_FILTER_NEAREST, 205 PIPE_TEX_FILTER_LINEAR, 206}; 207 208enum pipe_tex_compare { 209 PIPE_TEX_COMPARE_NONE, 210 PIPE_TEX_COMPARE_R_TO_TEXTURE, 211}; 212 213/** 214 * Clear buffer bits 215 */ 216#define PIPE_CLEAR_DEPTH (1 << 0) 217#define PIPE_CLEAR_STENCIL (1 << 1) 218#define PIPE_CLEAR_COLOR0 (1 << 2) 219#define PIPE_CLEAR_COLOR1 (1 << 3) 220#define PIPE_CLEAR_COLOR2 (1 << 4) 221#define PIPE_CLEAR_COLOR3 (1 << 5) 222#define PIPE_CLEAR_COLOR4 (1 << 6) 223#define PIPE_CLEAR_COLOR5 (1 << 7) 224#define PIPE_CLEAR_COLOR6 (1 << 8) 225#define PIPE_CLEAR_COLOR7 (1 << 9) 226/** Combined flags */ 227/** All color buffers currently bound */ 228#define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \ 229 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \ 230 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \ 231 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7) 232#define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL) 233 234/** 235 * Transfer object usage flags 236 */ 237enum pipe_transfer_usage 238{ 239 /** 240 * Resource contents read back (or accessed directly) at transfer 241 * create time. 242 */ 243 PIPE_TRANSFER_READ = (1 << 0), 244 245 /** 246 * Resource contents will be written back at transfer_unmap 247 * time (or modified as a result of being accessed directly). 248 */ 249 PIPE_TRANSFER_WRITE = (1 << 1), 250 251 /** 252 * Read/modify/write 253 */ 254 PIPE_TRANSFER_READ_WRITE = PIPE_TRANSFER_READ | PIPE_TRANSFER_WRITE, 255 256 /** 257 * The transfer should map the texture storage directly. The driver may 258 * return NULL if that isn't possible, and the state tracker needs to cope 259 * with that and use an alternative path without this flag. 260 * 261 * E.g. the state tracker could have a simpler path which maps textures and 262 * does read/modify/write cycles on them directly, and a more complicated 263 * path which uses minimal read and write transfers. 264 */ 265 PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2), 266 267 /** 268 * Discards the memory within the mapped region. 269 * 270 * It should not be used with PIPE_TRANSFER_READ. 271 * 272 * See also: 273 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag. 274 */ 275 PIPE_TRANSFER_DISCARD_RANGE = (1 << 8), 276 277 /** 278 * Fail if the resource cannot be mapped immediately. 279 * 280 * See also: 281 * - Direct3D's D3DLOCK_DONOTWAIT flag. 282 * - Mesa's MESA_MAP_NOWAIT_BIT flag. 283 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag. 284 */ 285 PIPE_TRANSFER_DONTBLOCK = (1 << 9), 286 287 /** 288 * Do not attempt to synchronize pending operations on the resource when mapping. 289 * 290 * It should not be used with PIPE_TRANSFER_READ. 291 * 292 * See also: 293 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag. 294 * - Direct3D's D3DLOCK_NOOVERWRITE flag. 295 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag. 296 */ 297 PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10), 298 299 /** 300 * Written ranges will be notified later with 301 * pipe_context::transfer_flush_region. 302 * 303 * It should not be used with PIPE_TRANSFER_READ. 304 * 305 * See also: 306 * - pipe_context::transfer_flush_region 307 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag. 308 */ 309 PIPE_TRANSFER_FLUSH_EXPLICIT = (1 << 11), 310 311 /** 312 * Discards all memory backing the resource. 313 * 314 * It should not be used with PIPE_TRANSFER_READ. 315 * 316 * This is equivalent to: 317 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT 318 * - BufferData(NULL) on a GL buffer 319 * - Direct3D's D3DLOCK_DISCARD flag. 320 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag. 321 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag 322 * - D3D10's D3D10_MAP_WRITE_DISCARD flag. 323 */ 324 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE = (1 << 12), 325 326 /** 327 * Allows the resource to be used for rendering while mapped. 328 * 329 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating 330 * the resource. 331 * 332 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER) 333 * must be called to ensure the device can see what the CPU has written. 334 */ 335 PIPE_TRANSFER_PERSISTENT = (1 << 13), 336 337 /** 338 * If PERSISTENT is set, this ensures any writes done by the device are 339 * immediately visible to the CPU and vice versa. 340 * 341 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating 342 * the resource. 343 */ 344 PIPE_TRANSFER_COHERENT = (1 << 14), 345 346 /** 347 * This and higher bits are reserved for private use by drivers. Drivers 348 * should use this as (PIPE_TRANSFER_DRV_PRV << i). 349 */ 350 PIPE_TRANSFER_DRV_PRV = (1 << 24) 351}; 352 353/** 354 * Flags for the flush function. 355 */ 356enum pipe_flush_flags 357{ 358 PIPE_FLUSH_END_OF_FRAME = (1 << 0), 359 PIPE_FLUSH_DEFERRED = (1 << 1), 360 PIPE_FLUSH_FENCE_FD = (1 << 2), 361 PIPE_FLUSH_ASYNC = (1 << 3), 362 PIPE_FLUSH_HINT_FINISH = (1 << 4), 363 PIPE_FLUSH_TOP_OF_PIPE = (1 << 5), 364 PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6), 365}; 366 367/** 368 * Flags for pipe_context::dump_debug_state. 369 */ 370#define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0) 371 372/** 373 * Create a compute-only context. Use in pipe_screen::context_create. 374 * This disables draw, blit, and clear*, render_condition, and other graphics 375 * functions. Interop with other graphics contexts is still allowed. 376 * This allows scheduling jobs on a compute-only hardware command queue that 377 * can run in parallel with graphics without stalling it. 378 */ 379#define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0) 380 381/** 382 * Gather debug information and expect that pipe_context::dump_debug_state 383 * will be called. Use in pipe_screen::context_create. 384 */ 385#define PIPE_CONTEXT_DEBUG (1 << 1) 386 387/** 388 * Whether out-of-bounds shader loads must return zero and out-of-bounds 389 * shader stores must be dropped. 390 */ 391#define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2) 392 393/** 394 * Prefer threaded pipe_context. It also implies that video codec functions 395 * will not be used. (they will be either no-ops or NULL when threading is 396 * enabled) 397 */ 398#define PIPE_CONTEXT_PREFER_THREADED (1 << 3) 399 400/** 401 * Create a high priority context. 402 */ 403#define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4) 404 405/** 406 * Create a low priority context. 407 */ 408#define PIPE_CONTEXT_LOW_PRIORITY (1 << 5) 409 410/** Stop execution if the device is reset. */ 411#define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6) 412 413/** 414 * Flags for pipe_context::memory_barrier. 415 */ 416#define PIPE_BARRIER_MAPPED_BUFFER (1 << 0) 417#define PIPE_BARRIER_SHADER_BUFFER (1 << 1) 418#define PIPE_BARRIER_QUERY_BUFFER (1 << 2) 419#define PIPE_BARRIER_VERTEX_BUFFER (1 << 3) 420#define PIPE_BARRIER_INDEX_BUFFER (1 << 4) 421#define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5) 422#define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6) 423#define PIPE_BARRIER_TEXTURE (1 << 7) 424#define PIPE_BARRIER_IMAGE (1 << 8) 425#define PIPE_BARRIER_FRAMEBUFFER (1 << 9) 426#define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10) 427#define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11) 428#define PIPE_BARRIER_UPDATE_BUFFER (1 << 12) 429#define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13) 430#define PIPE_BARRIER_ALL ((1 << 14) - 1) 431 432#define PIPE_BARRIER_UPDATE \ 433 (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE) 434 435/** 436 * Flags for pipe_context::texture_barrier. 437 */ 438#define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0) 439#define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1) 440 441/** 442 * Resource binding flags -- state tracker must specify in advance all 443 * the ways a resource might be used. 444 */ 445#define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */ 446#define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */ 447#define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */ 448#define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */ 449#define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */ 450#define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */ 451#define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */ 452#define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */ 453/* gap */ 454#define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */ 455#define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */ 456#define PIPE_BIND_CUSTOM (1 << 12) /* state-tracker/winsys usages */ 457#define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */ 458#define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */ 459#define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */ 460#define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */ 461#define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */ 462#define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */ 463 464/** 465 * The first two flags above were previously part of the amorphous 466 * TEXTURE_USAGE, most of which are now descriptions of the ways a 467 * particular texture can be bound to the gallium pipeline. The two flags 468 * below do not fit within that and probably need to be migrated to some 469 * other place. 470 * 471 * It seems like scanout is used by the Xorg state tracker to ask for 472 * a texture suitable for actual scanout (hence the name), which 473 * implies extra layout constraints on some hardware. It may also 474 * have some special meaning regarding mouse cursor images. 475 * 476 * The shared flag is quite underspecified, but certainly isn't a 477 * binding flag - it seems more like a message to the winsys to create 478 * a shareable allocation. 479 * 480 * The third flag has been added to be able to force textures to be created 481 * in linear mode (no tiling). 482 */ 483#define PIPE_BIND_SCANOUT (1 << 19) /* */ 484#define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */ 485#define PIPE_BIND_LINEAR (1 << 21) 486 487 488/** 489 * Flags for the driver about resource behaviour: 490 */ 491#define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0) 492#define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1) 493#define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2) 494#define PIPE_RESOURCE_FLAG_SPARSE (1 << 3) 495#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 8) /* driver/winsys private */ 496#define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */ 497 498/** 499 * Hint about the expected lifecycle of a resource. 500 * Sorted according to GPU vs CPU access. 501 */ 502enum pipe_resource_usage { 503 PIPE_USAGE_DEFAULT, /* fast GPU access */ 504 PIPE_USAGE_IMMUTABLE, /* fast GPU access, immutable */ 505 PIPE_USAGE_DYNAMIC, /* uploaded data is used multiple times */ 506 PIPE_USAGE_STREAM, /* uploaded data is used once */ 507 PIPE_USAGE_STAGING, /* fast CPU access */ 508}; 509 510/** 511 * Shaders 512 */ 513enum pipe_shader_type { 514 PIPE_SHADER_VERTEX, 515 PIPE_SHADER_FRAGMENT, 516 PIPE_SHADER_GEOMETRY, 517 PIPE_SHADER_TESS_CTRL, 518 PIPE_SHADER_TESS_EVAL, 519 PIPE_SHADER_COMPUTE, 520 PIPE_SHADER_TYPES, 521}; 522 523/** 524 * Primitive types: 525 */ 526enum pipe_prim_type { 527 PIPE_PRIM_POINTS, 528 PIPE_PRIM_LINES, 529 PIPE_PRIM_LINE_LOOP, 530 PIPE_PRIM_LINE_STRIP, 531 PIPE_PRIM_TRIANGLES, 532 PIPE_PRIM_TRIANGLE_STRIP, 533 PIPE_PRIM_TRIANGLE_FAN, 534 PIPE_PRIM_QUADS, 535 PIPE_PRIM_QUAD_STRIP, 536 PIPE_PRIM_POLYGON, 537 PIPE_PRIM_LINES_ADJACENCY, 538 PIPE_PRIM_LINE_STRIP_ADJACENCY, 539 PIPE_PRIM_TRIANGLES_ADJACENCY, 540 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY, 541 PIPE_PRIM_PATCHES, 542 PIPE_PRIM_MAX, 543}; 544 545/** 546 * Tessellator spacing types 547 */ 548enum pipe_tess_spacing { 549 PIPE_TESS_SPACING_FRACTIONAL_ODD, 550 PIPE_TESS_SPACING_FRACTIONAL_EVEN, 551 PIPE_TESS_SPACING_EQUAL, 552}; 553 554/** 555 * Query object types 556 */ 557enum pipe_query_type { 558 PIPE_QUERY_OCCLUSION_COUNTER, 559 PIPE_QUERY_OCCLUSION_PREDICATE, 560 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE, 561 PIPE_QUERY_TIMESTAMP, 562 PIPE_QUERY_TIMESTAMP_DISJOINT, 563 PIPE_QUERY_TIME_ELAPSED, 564 PIPE_QUERY_PRIMITIVES_GENERATED, 565 PIPE_QUERY_PRIMITIVES_EMITTED, 566 PIPE_QUERY_SO_STATISTICS, 567 PIPE_QUERY_SO_OVERFLOW_PREDICATE, 568 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE, 569 PIPE_QUERY_GPU_FINISHED, 570 PIPE_QUERY_PIPELINE_STATISTICS, 571 PIPE_QUERY_PIPELINE_STATISTICS_SINGLE, 572 PIPE_QUERY_TYPES, 573 /* start of driver queries, see pipe_screen::get_driver_query_info */ 574 PIPE_QUERY_DRIVER_SPECIFIC = 256, 575}; 576 577/** 578 * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries. 579 */ 580enum pipe_statistics_query_index { 581 PIPE_STAT_QUERY_IA_VERTICES, 582 PIPE_STAT_QUERY_IA_PRIMITIVES, 583 PIPE_STAT_QUERY_VS_INVOCATIONS, 584 PIPE_STAT_QUERY_GS_INVOCATIONS, 585 PIPE_STAT_QUERY_GS_PRIMITIVES, 586 PIPE_STAT_QUERY_C_INVOCATIONS, 587 PIPE_STAT_QUERY_C_PRIMITIVES, 588 PIPE_STAT_QUERY_PS_INVOCATIONS, 589 PIPE_STAT_QUERY_HS_INVOCATIONS, 590 PIPE_STAT_QUERY_DS_INVOCATIONS, 591 PIPE_STAT_QUERY_CS_INVOCATIONS, 592}; 593 594/** 595 * Conditional rendering modes 596 */ 597enum pipe_render_cond_flag { 598 PIPE_RENDER_COND_WAIT, 599 PIPE_RENDER_COND_NO_WAIT, 600 PIPE_RENDER_COND_BY_REGION_WAIT, 601 PIPE_RENDER_COND_BY_REGION_NO_WAIT, 602}; 603 604/** 605 * Point sprite coord modes 606 */ 607enum pipe_sprite_coord_mode { 608 PIPE_SPRITE_COORD_UPPER_LEFT, 609 PIPE_SPRITE_COORD_LOWER_LEFT, 610}; 611 612/** 613 * Texture & format swizzles 614 */ 615enum pipe_swizzle { 616 PIPE_SWIZZLE_X, 617 PIPE_SWIZZLE_Y, 618 PIPE_SWIZZLE_Z, 619 PIPE_SWIZZLE_W, 620 PIPE_SWIZZLE_0, 621 PIPE_SWIZZLE_1, 622 PIPE_SWIZZLE_NONE, 623 PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */ 624}; 625 626#define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull 627 628 629/** 630 * Device reset status. 631 */ 632enum pipe_reset_status 633{ 634 PIPE_NO_RESET, 635 PIPE_GUILTY_CONTEXT_RESET, 636 PIPE_INNOCENT_CONTEXT_RESET, 637 PIPE_UNKNOWN_CONTEXT_RESET, 638}; 639 640 641/** 642 * Conservative rasterization modes. 643 */ 644enum pipe_conservative_raster_mode 645{ 646 PIPE_CONSERVATIVE_RASTER_OFF, 647 648 /** 649 * The post-snap mode means the conservative rasterization occurs after 650 * the conversion from floating-point to fixed-point coordinates 651 * on the subpixel grid. 652 */ 653 PIPE_CONSERVATIVE_RASTER_POST_SNAP, 654 655 /** 656 * The pre-snap mode means the conservative rasterization occurs before 657 * the conversion from floating-point to fixed-point coordinates. 658 */ 659 PIPE_CONSERVATIVE_RASTER_PRE_SNAP, 660}; 661 662 663/** 664 * resource_get_handle flags. 665 */ 666/* Requires pipe_context::flush_resource before external use. */ 667#define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0) 668/* Expected external use of the resource: */ 669#define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1) 670#define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2) 671 672/** 673 * pipe_image_view access flags. 674 */ 675#define PIPE_IMAGE_ACCESS_READ (1 << 0) 676#define PIPE_IMAGE_ACCESS_WRITE (1 << 1) 677#define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \ 678 PIPE_IMAGE_ACCESS_WRITE) 679 680/** 681 * Implementation capabilities/limits which are queried through 682 * pipe_screen::get_param() 683 */ 684enum pipe_cap 685{ 686 PIPE_CAP_NPOT_TEXTURES, 687 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS, 688 PIPE_CAP_ANISOTROPIC_FILTER, 689 PIPE_CAP_POINT_SPRITE, 690 PIPE_CAP_MAX_RENDER_TARGETS, 691 PIPE_CAP_OCCLUSION_QUERY, 692 PIPE_CAP_QUERY_TIME_ELAPSED, 693 PIPE_CAP_TEXTURE_SWIZZLE, 694 PIPE_CAP_MAX_TEXTURE_2D_LEVELS, 695 PIPE_CAP_MAX_TEXTURE_3D_LEVELS, 696 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS, 697 PIPE_CAP_TEXTURE_MIRROR_CLAMP, 698 PIPE_CAP_BLEND_EQUATION_SEPARATE, 699 PIPE_CAP_SM3, 700 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS, 701 PIPE_CAP_PRIMITIVE_RESTART, 702 /** blend enables and write masks per rendertarget */ 703 PIPE_CAP_INDEP_BLEND_ENABLE, 704 /** different blend funcs per rendertarget */ 705 PIPE_CAP_INDEP_BLEND_FUNC, 706 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS, 707 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 708 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 709 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 710 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 711 PIPE_CAP_DEPTH_CLIP_DISABLE, 712 PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE, 713 PIPE_CAP_SHADER_STENCIL_EXPORT, 714 PIPE_CAP_TGSI_INSTANCEID, 715 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR, 716 PIPE_CAP_FRAGMENT_COLOR_CLAMPED, 717 PIPE_CAP_MIXED_COLORBUFFER_FORMATS, 718 PIPE_CAP_SEAMLESS_CUBE_MAP, 719 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE, 720 PIPE_CAP_MIN_TEXEL_OFFSET, 721 PIPE_CAP_MAX_TEXEL_OFFSET, 722 PIPE_CAP_CONDITIONAL_RENDER, 723 PIPE_CAP_TEXTURE_BARRIER, 724 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS, 725 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS, 726 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME, 727 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS, 728 PIPE_CAP_VERTEX_COLOR_UNCLAMPED, 729 PIPE_CAP_VERTEX_COLOR_CLAMPED, 730 PIPE_CAP_GLSL_FEATURE_LEVEL, 731 PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY, 732 PIPE_CAP_ESSL_FEATURE_LEVEL, 733 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION, 734 PIPE_CAP_USER_VERTEX_BUFFERS, 735 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY, 736 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY, 737 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY, 738 PIPE_CAP_COMPUTE, 739 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT, 740 PIPE_CAP_START_INSTANCE, 741 PIPE_CAP_QUERY_TIMESTAMP, 742 PIPE_CAP_TEXTURE_MULTISAMPLE, 743 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, 744 PIPE_CAP_CUBE_MAP_ARRAY, 745 PIPE_CAP_TEXTURE_BUFFER_OBJECTS, 746 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT, 747 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY, 748 PIPE_CAP_TGSI_TEXCOORD, 749 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER, 750 PIPE_CAP_QUERY_PIPELINE_STATISTICS, 751 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK, 752 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE, 753 PIPE_CAP_MAX_VIEWPORTS, 754 PIPE_CAP_ENDIANNESS, 755 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES, 756 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT, 757 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES, 758 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS, 759 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS, 760 PIPE_CAP_TEXTURE_GATHER_SM5, 761 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT, 762 PIPE_CAP_FAKE_SW_MSAA, 763 PIPE_CAP_TEXTURE_QUERY_LOD, 764 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET, 765 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET, 766 PIPE_CAP_SAMPLE_SHADING, 767 PIPE_CAP_TEXTURE_GATHER_OFFSETS, 768 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION, 769 PIPE_CAP_MAX_VERTEX_STREAMS, 770 PIPE_CAP_DRAW_INDIRECT, 771 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE, 772 PIPE_CAP_VENDOR_ID, 773 PIPE_CAP_DEVICE_ID, 774 PIPE_CAP_ACCELERATED, 775 PIPE_CAP_VIDEO_MEMORY, 776 PIPE_CAP_UMA, 777 PIPE_CAP_CONDITIONAL_RENDER_INVERTED, 778 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE, 779 PIPE_CAP_SAMPLER_VIEW_TARGET, 780 PIPE_CAP_CLIP_HALFZ, 781 PIPE_CAP_VERTEXID_NOBASE, 782 PIPE_CAP_POLYGON_OFFSET_CLAMP, 783 PIPE_CAP_MULTISAMPLE_Z_RESOLVE, 784 PIPE_CAP_RESOURCE_FROM_USER_MEMORY, 785 PIPE_CAP_DEVICE_RESET_STATUS_QUERY, 786 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS, 787 PIPE_CAP_TEXTURE_FLOAT_LINEAR, 788 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR, 789 PIPE_CAP_DEPTH_BOUNDS_TEST, 790 PIPE_CAP_TGSI_TXQS, 791 PIPE_CAP_FORCE_PERSAMPLE_INTERP, 792 PIPE_CAP_SHAREABLE_SHADERS, 793 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS, 794 PIPE_CAP_CLEAR_TEXTURE, 795 PIPE_CAP_DRAW_PARAMETERS, 796 PIPE_CAP_TGSI_PACK_HALF_FLOAT, 797 PIPE_CAP_MULTI_DRAW_INDIRECT, 798 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS, 799 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL, 800 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL, 801 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT, 802 PIPE_CAP_INVALIDATE_BUFFER, 803 PIPE_CAP_GENERATE_MIPMAP, 804 PIPE_CAP_STRING_MARKER, 805 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS, 806 PIPE_CAP_QUERY_BUFFER_OBJECT, 807 PIPE_CAP_QUERY_MEMORY_INFO, 808 PIPE_CAP_PCI_GROUP, 809 PIPE_CAP_PCI_BUS, 810 PIPE_CAP_PCI_DEVICE, 811 PIPE_CAP_PCI_FUNCTION, 812 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT, 813 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR, 814 PIPE_CAP_CULL_DISTANCE, 815 PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES, 816 PIPE_CAP_TGSI_VOTE, 817 PIPE_CAP_MAX_WINDOW_RECTANGLES, 818 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED, 819 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS, 820 PIPE_CAP_RASTERIZER_SUBPIXEL_BITS, 821 PIPE_CAP_MIXED_COLOR_DEPTH_BITS, 822 PIPE_CAP_TGSI_ARRAY_COMPONENTS, 823 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS, 824 PIPE_CAP_TGSI_CAN_READ_OUTPUTS, 825 PIPE_CAP_NATIVE_FENCE_FD, 826 PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY, 827 PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS, 828 PIPE_CAP_TGSI_FS_FBFETCH, 829 PIPE_CAP_TGSI_MUL_ZERO_WINS, 830 PIPE_CAP_DOUBLES, 831 PIPE_CAP_INT64, 832 PIPE_CAP_INT64_DIVMOD, 833 PIPE_CAP_TGSI_TEX_TXF_LZ, 834 PIPE_CAP_TGSI_CLOCK, 835 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE, 836 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE, 837 PIPE_CAP_TGSI_BALLOT, 838 PIPE_CAP_TGSI_TES_LAYER_VIEWPORT, 839 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX, 840 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION, 841 PIPE_CAP_POST_DEPTH_COVERAGE, 842 PIPE_CAP_BINDLESS_TEXTURE, 843 PIPE_CAP_NIR_SAMPLERS_AS_DEREF, 844 PIPE_CAP_QUERY_SO_OVERFLOW, 845 PIPE_CAP_MEMOBJ, 846 PIPE_CAP_LOAD_CONSTBUF, 847 PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS, 848 PIPE_CAP_TILE_RASTER_ORDER, 849 PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES, 850 PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS, 851 PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET, 852 PIPE_CAP_CONTEXT_PRIORITY_MASK, 853 PIPE_CAP_FENCE_SIGNAL, 854 PIPE_CAP_CONSTBUF0_FLAGS, 855 PIPE_CAP_PACKED_UNIFORMS, 856 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES, 857 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES, 858 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES, 859 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES, 860 PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS, 861 PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE, 862 PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE, 863 PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS, 864 PIPE_CAP_MAX_GS_INVOCATIONS, 865 PIPE_CAP_MAX_SHADER_BUFFER_SIZE, 866 PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE, 867 PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS, 868 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS, 869 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS, 870 PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET, 871 PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET, 872 PIPE_CAP_SURFACE_SAMPLE_COUNT, 873 PIPE_CAP_TGSI_ATOMFADD, 874 PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE, 875 PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND, 876 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL, 877 PIPE_CAP_NIR_COMPACT_ARRAYS, 878 PIPE_CAP_MAX_VARYINGS, 879 PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK, 880 PIPE_CAP_COMPUTE_SHADER_DERIVATIVES, 881 PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS, 882 PIPE_CAP_IMAGE_LOAD_FORMATTED, 883 PIPE_CAP_MAX_FRAMES_IN_FLIGHT, 884 PIPE_CAP_DMABUF, 885 PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA, 886 PIPE_CAP_TGSI_DIV, 887}; 888 889/** 890 * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should 891 * return a bitmask of the supported priorities. If the driver does not 892 * support prioritized contexts, it can return 0. 893 * 894 * Note that these match __DRI2_RENDER_HAS_CONTEXT_PRIORITY_* 895 */ 896#define PIPE_CONTEXT_PRIORITY_LOW (1 << 0) 897#define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1) 898#define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2) 899 900#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0) 901#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1) 902 903enum pipe_endian 904{ 905 PIPE_ENDIAN_LITTLE = 0, 906 PIPE_ENDIAN_BIG = 1, 907#if defined(PIPE_ARCH_LITTLE_ENDIAN) 908 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE 909#elif defined(PIPE_ARCH_BIG_ENDIAN) 910 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG 911#endif 912}; 913 914/** 915 * Implementation limits which are queried through 916 * pipe_screen::get_paramf() 917 */ 918enum pipe_capf 919{ 920 PIPE_CAPF_MAX_LINE_WIDTH, 921 PIPE_CAPF_MAX_LINE_WIDTH_AA, 922 PIPE_CAPF_MAX_POINT_WIDTH, 923 PIPE_CAPF_MAX_POINT_WIDTH_AA, 924 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY, 925 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS, 926 PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE, 927 PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE, 928 PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY, 929}; 930 931/** Shader caps not specific to any single stage */ 932enum pipe_shader_cap 933{ 934 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */ 935 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS, 936 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS, 937 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS, 938 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH, 939 PIPE_SHADER_CAP_MAX_INPUTS, 940 PIPE_SHADER_CAP_MAX_OUTPUTS, 941 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE, 942 PIPE_SHADER_CAP_MAX_CONST_BUFFERS, 943 PIPE_SHADER_CAP_MAX_TEMPS, 944 /* boolean caps */ 945 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED, 946 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR, 947 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR, 948 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR, 949 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR, 950 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */ 951 PIPE_SHADER_CAP_INTEGERS, 952 PIPE_SHADER_CAP_INT64_ATOMICS, 953 PIPE_SHADER_CAP_FP16, 954 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS, 955 PIPE_SHADER_CAP_PREFERRED_IR, 956 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, 957 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, 958 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ 959 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, 960 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED, 961 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, 962 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT, 963 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, 964 PIPE_SHADER_CAP_SUPPORTED_IRS, 965 PIPE_SHADER_CAP_MAX_SHADER_IMAGES, 966 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD, 967 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS, 968 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED, 969 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS, 970 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS, 971 PIPE_SHADER_CAP_SCALAR_ISA, 972}; 973 974/** 975 * Shader intermediate representation. 976 * 977 * Note that if the driver requests something other than TGSI, it must 978 * always be prepared to receive TGSI in addition to its preferred IR. 979 * If the driver requests TGSI as its preferred IR, it will *always* 980 * get TGSI. 981 * 982 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with 983 * state trackers that only understand TGSI. 984 */ 985enum pipe_shader_ir 986{ 987 PIPE_SHADER_IR_TGSI = 0, 988 PIPE_SHADER_IR_NATIVE, 989 PIPE_SHADER_IR_NIR, 990}; 991 992/** 993 * Compute-specific implementation capability. They can be queried 994 * using pipe_screen::get_compute_param. 995 */ 996enum pipe_compute_cap 997{ 998 PIPE_COMPUTE_CAP_ADDRESS_BITS, 999 PIPE_COMPUTE_CAP_IR_TARGET, 1000 PIPE_COMPUTE_CAP_GRID_DIMENSION, 1001 PIPE_COMPUTE_CAP_MAX_GRID_SIZE, 1002 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE, 1003 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, 1004 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, 1005 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE, 1006 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE, 1007 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE, 1008 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 1009 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY, 1010 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS, 1011 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED, 1012 PIPE_COMPUTE_CAP_SUBGROUP_SIZE, 1013 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK, 1014}; 1015 1016/** 1017 * Types of parameters for pipe_context::set_context_param. 1018 */ 1019enum pipe_context_param 1020{ 1021 /* A hint for the driver that it should pin its execution threads to 1022 * a group of cores sharing a specific L3 cache if the CPU has multiple 1023 * L3 caches. This is needed for good multithreading performance on 1024 * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have 1025 * any internal threads or don't run on affected CPUs can ignore this. 1026 */ 1027 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE, 1028}; 1029 1030/** 1031 * Composite query types 1032 */ 1033 1034/** 1035 * Query result for PIPE_QUERY_SO_STATISTICS. 1036 */ 1037struct pipe_query_data_so_statistics 1038{ 1039 uint64_t num_primitives_written; 1040 uint64_t primitives_storage_needed; 1041}; 1042 1043/** 1044 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT. 1045 */ 1046struct pipe_query_data_timestamp_disjoint 1047{ 1048 uint64_t frequency; 1049 boolean disjoint; 1050}; 1051 1052/** 1053 * Query result for PIPE_QUERY_PIPELINE_STATISTICS. 1054 */ 1055struct pipe_query_data_pipeline_statistics 1056{ 1057 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */ 1058 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */ 1059 uint64_t vs_invocations; /**< Num vertex shader invocations. */ 1060 uint64_t gs_invocations; /**< Num geometry shader invocations. */ 1061 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */ 1062 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */ 1063 uint64_t c_primitives; /**< Num primitives that were rendered. */ 1064 uint64_t ps_invocations; /**< Num pixel shader invocations. */ 1065 uint64_t hs_invocations; /**< Num hull shader invocations. */ 1066 uint64_t ds_invocations; /**< Num domain shader invocations. */ 1067 uint64_t cs_invocations; /**< Num compute shader invocations. */ 1068}; 1069 1070/** 1071 * For batch queries. 1072 */ 1073union pipe_numeric_type_union 1074{ 1075 uint64_t u64; 1076 uint32_t u32; 1077 float f; 1078}; 1079 1080/** 1081 * Query result (returned by pipe_context::get_query_result). 1082 */ 1083union pipe_query_result 1084{ 1085 /* PIPE_QUERY_OCCLUSION_PREDICATE */ 1086 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */ 1087 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */ 1088 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */ 1089 /* PIPE_QUERY_GPU_FINISHED */ 1090 boolean b; 1091 1092 /* PIPE_QUERY_OCCLUSION_COUNTER */ 1093 /* PIPE_QUERY_TIMESTAMP */ 1094 /* PIPE_QUERY_TIME_ELAPSED */ 1095 /* PIPE_QUERY_PRIMITIVES_GENERATED */ 1096 /* PIPE_QUERY_PRIMITIVES_EMITTED */ 1097 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */ 1098 /* PIPE_DRIVER_QUERY_TYPE_BYTES */ 1099 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */ 1100 /* PIPE_DRIVER_QUERY_TYPE_HZ */ 1101 uint64_t u64; 1102 1103 /* PIPE_DRIVER_QUERY_TYPE_UINT */ 1104 uint32_t u32; 1105 1106 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */ 1107 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */ 1108 float f; 1109 1110 /* PIPE_QUERY_SO_STATISTICS */ 1111 struct pipe_query_data_so_statistics so_statistics; 1112 1113 /* PIPE_QUERY_TIMESTAMP_DISJOINT */ 1114 struct pipe_query_data_timestamp_disjoint timestamp_disjoint; 1115 1116 /* PIPE_QUERY_PIPELINE_STATISTICS */ 1117 struct pipe_query_data_pipeline_statistics pipeline_statistics; 1118 1119 /* batch queries (variable length) */ 1120 union pipe_numeric_type_union batch[1]; 1121}; 1122 1123enum pipe_query_value_type 1124{ 1125 PIPE_QUERY_TYPE_I32, 1126 PIPE_QUERY_TYPE_U32, 1127 PIPE_QUERY_TYPE_I64, 1128 PIPE_QUERY_TYPE_U64, 1129}; 1130 1131union pipe_color_union 1132{ 1133 float f[4]; 1134 int i[4]; 1135 unsigned int ui[4]; 1136}; 1137 1138enum pipe_driver_query_type 1139{ 1140 PIPE_DRIVER_QUERY_TYPE_UINT64, 1141 PIPE_DRIVER_QUERY_TYPE_UINT, 1142 PIPE_DRIVER_QUERY_TYPE_FLOAT, 1143 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE, 1144 PIPE_DRIVER_QUERY_TYPE_BYTES, 1145 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS, 1146 PIPE_DRIVER_QUERY_TYPE_HZ, 1147 PIPE_DRIVER_QUERY_TYPE_DBM, 1148 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE, 1149 PIPE_DRIVER_QUERY_TYPE_VOLTS, 1150 PIPE_DRIVER_QUERY_TYPE_AMPS, 1151 PIPE_DRIVER_QUERY_TYPE_WATTS, 1152}; 1153 1154/* Whether an average value per frame or a cumulative value should be 1155 * displayed. 1156 */ 1157enum pipe_driver_query_result_type 1158{ 1159 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 1160 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE, 1161}; 1162 1163/** 1164 * Some hardware requires some hardware-specific queries to be submitted 1165 * as batched queries. The corresponding query objects are created using 1166 * create_batch_query, and at most one such query may be active at 1167 * any time. 1168 */ 1169#define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0) 1170 1171/* Do not list this query in the HUD. */ 1172#define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1) 1173 1174struct pipe_driver_query_info 1175{ 1176 const char *name; 1177 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */ 1178 union pipe_numeric_type_union max_value; /* max value that can be returned */ 1179 enum pipe_driver_query_type type; 1180 enum pipe_driver_query_result_type result_type; 1181 unsigned group_id; 1182 unsigned flags; 1183}; 1184 1185struct pipe_driver_query_group_info 1186{ 1187 const char *name; 1188 unsigned max_active_queries; 1189 unsigned num_queries; 1190}; 1191 1192enum pipe_fd_type 1193{ 1194 PIPE_FD_TYPE_NATIVE_SYNC, 1195 PIPE_FD_TYPE_SYNCOBJ, 1196}; 1197 1198enum pipe_debug_type 1199{ 1200 PIPE_DEBUG_TYPE_OUT_OF_MEMORY = 1, 1201 PIPE_DEBUG_TYPE_ERROR, 1202 PIPE_DEBUG_TYPE_SHADER_INFO, 1203 PIPE_DEBUG_TYPE_PERF_INFO, 1204 PIPE_DEBUG_TYPE_INFO, 1205 PIPE_DEBUG_TYPE_FALLBACK, 1206 PIPE_DEBUG_TYPE_CONFORMANCE, 1207}; 1208 1209#define PIPE_UUID_SIZE 16 1210 1211#ifdef __cplusplus 1212} 1213#endif 1214 1215#endif 1216