1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include <errno.h>
25
26#include "program/prog_instruction.h"
27
28#include "blorp_priv.h"
29#include "compiler/brw_compiler.h"
30#include "compiler/brw_nir.h"
31
32void
33blorp_init(struct blorp_context *blorp, void *driver_ctx,
34           struct isl_device *isl_dev)
35{
36   blorp->driver_ctx = driver_ctx;
37   blorp->isl_dev = isl_dev;
38}
39
40void
41blorp_finish(struct blorp_context *blorp)
42{
43   blorp->driver_ctx = NULL;
44}
45
46void
47blorp_batch_init(struct blorp_context *blorp,
48                 struct blorp_batch *batch, void *driver_batch,
49                 enum blorp_batch_flags flags)
50{
51   batch->blorp = blorp;
52   batch->driver_batch = driver_batch;
53   batch->flags = flags;
54}
55
56void
57blorp_batch_finish(struct blorp_batch *batch)
58{
59   batch->blorp = NULL;
60}
61
62void
63brw_blorp_surface_info_init(struct blorp_context *blorp,
64                            struct brw_blorp_surface_info *info,
65                            const struct blorp_surf *surf,
66                            unsigned int level, unsigned int layer,
67                            enum isl_format format, bool is_render_target)
68{
69   assert(level < surf->surf->levels);
70   assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
71                       surf->surf->logical_level0_px.array_len));
72
73   info->enabled = true;
74
75   if (format == ISL_FORMAT_UNSUPPORTED)
76      format = surf->surf->format;
77
78   info->surf = *surf->surf;
79   info->addr = surf->addr;
80
81   info->aux_usage = surf->aux_usage;
82   if (info->aux_usage != ISL_AUX_USAGE_NONE) {
83      info->aux_surf = *surf->aux_surf;
84      info->aux_addr = surf->aux_addr;
85      assert(level < info->aux_surf.levels);
86      assert(layer < MAX2(info->aux_surf.logical_level0_px.depth >> level,
87                          info->aux_surf.logical_level0_px.array_len));
88   }
89
90   info->clear_color = surf->clear_color;
91   info->clear_color_addr = surf->clear_color_addr;
92
93   info->view = (struct isl_view) {
94      .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
95                                  ISL_SURF_USAGE_TEXTURE_BIT,
96      .format = format,
97      .base_level = level,
98      .levels = 1,
99      .swizzle = ISL_SWIZZLE_IDENTITY,
100   };
101
102   info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
103                               info->surf.logical_level0_px.array_len);
104
105   if (!is_render_target &&
106       (info->surf.dim == ISL_SURF_DIM_3D ||
107        info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
108      /* 3-D textures don't support base_array layer and neither do 2-D
109       * multisampled textures on IVB so we need to pass it through the
110       * sampler in those cases.  These are also two cases where we are
111       * guaranteed that we won't be doing any funny surface hacks.
112       */
113      info->view.base_array_layer = 0;
114      info->z_offset = layer;
115   } else {
116      info->view.base_array_layer = layer;
117
118      assert(info->view.array_len >= info->view.base_array_layer);
119      info->view.array_len -= info->view.base_array_layer;
120      info->z_offset = 0;
121   }
122
123   /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
124    * layered rendering.
125    */
126   if (is_render_target && blorp->isl_dev->info->gen <= 6)
127      info->view.array_len = MIN2(info->view.array_len, 512);
128
129   if (surf->tile_x_sa || surf->tile_y_sa) {
130      /* This is only allowed on simple 2D surfaces without MSAA */
131      assert(info->surf.dim == ISL_SURF_DIM_2D);
132      assert(info->surf.samples == 1);
133      assert(info->surf.levels == 1);
134      assert(info->surf.logical_level0_px.array_len == 1);
135      assert(info->aux_usage == ISL_AUX_USAGE_NONE);
136
137      info->tile_x_sa = surf->tile_x_sa;
138      info->tile_y_sa = surf->tile_y_sa;
139
140      /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
141       * place the image at the tile boundary and offset our sampling or
142       * rendering.  For this reason, we need to grow the image by the offset
143       * to ensure that the hardware doesn't think we've gone past the edge.
144       */
145      info->surf.logical_level0_px.w += surf->tile_x_sa;
146      info->surf.logical_level0_px.h += surf->tile_y_sa;
147      info->surf.phys_level0_sa.w += surf->tile_x_sa;
148      info->surf.phys_level0_sa.h += surf->tile_y_sa;
149   }
150}
151
152
153void
154blorp_params_init(struct blorp_params *params)
155{
156   memset(params, 0, sizeof(*params));
157   params->num_samples = 1;
158   params->num_draw_buffers = 1;
159   params->num_layers = 1;
160}
161
162void
163brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
164{
165   memset(wm_key, 0, sizeof(*wm_key));
166   wm_key->nr_color_regions = 1;
167   for (int i = 0; i < MAX_SAMPLERS; i++)
168      wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
169}
170
171const unsigned *
172blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
173                 struct nir_shader *nir,
174                 struct brw_wm_prog_key *wm_key,
175                 bool use_repclear,
176                 struct brw_wm_prog_data *wm_prog_data)
177{
178   const struct brw_compiler *compiler = blorp->compiler;
179
180   nir->options =
181      compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
182
183   memset(wm_prog_data, 0, sizeof(*wm_prog_data));
184
185   assert(exec_list_is_empty(&nir->uniforms));
186   wm_prog_data->base.nr_params = 0;
187   wm_prog_data->base.param = NULL;
188
189   /* BLORP always uses the first two binding table entries:
190    * - Surface 0 is the render target (which always start from 0)
191    * - Surface 1 is the source texture
192    */
193   wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
194
195   nir = brw_preprocess_nir(compiler, nir, NULL);
196   nir_remove_dead_variables(nir, nir_var_shader_in);
197   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
198
199   if (blorp->compiler->devinfo->gen < 6) {
200      if (nir->info.fs.uses_discard)
201         wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
202
203      wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
204   }
205
206   const unsigned *program =
207      brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
208                     wm_prog_data, nir, NULL, -1, -1, -1, false, use_repclear,
209                     NULL, NULL);
210
211   return program;
212}
213
214const unsigned *
215blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
216                 struct nir_shader *nir,
217                 struct brw_vs_prog_data *vs_prog_data)
218{
219   const struct brw_compiler *compiler = blorp->compiler;
220
221   nir->options =
222      compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
223
224   nir = brw_preprocess_nir(compiler, nir, NULL);
225   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
226
227   vs_prog_data->inputs_read = nir->info.inputs_read;
228
229   brw_compute_vue_map(compiler->devinfo,
230                       &vs_prog_data->base.vue_map,
231                       nir->info.outputs_written,
232                       nir->info.separate_shader);
233
234   struct brw_vs_prog_key vs_key = { 0, };
235
236   const unsigned *program =
237      brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
238                     &vs_key, vs_prog_data, nir, -1, NULL);
239
240   return program;
241}
242
243struct blorp_sf_key {
244   enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
245
246   struct brw_sf_prog_key key;
247};
248
249bool
250blorp_ensure_sf_program(struct blorp_batch *batch,
251                        struct blorp_params *params)
252{
253   struct blorp_context *blorp = batch->blorp;
254   const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
255   assert(params->wm_prog_data);
256
257   /* Gen6+ doesn't need a strips and fans program */
258   if (blorp->compiler->devinfo->gen >= 6)
259      return true;
260
261   struct blorp_sf_key key = {
262      .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
263   };
264
265   /* Everything gets compacted in vertex setup, so we just need a
266    * pass-through for the correct number of input varyings.
267    */
268   const uint64_t slots_valid = VARYING_BIT_POS |
269      ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
270
271   key.key.attrs = slots_valid;
272   key.key.primitive = BRW_SF_PRIM_TRIANGLES;
273   key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
274
275   STATIC_ASSERT(sizeof(key.key.interp_mode) ==
276                 sizeof(wm_prog_data->interp_mode));
277   memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
278          sizeof(key.key.interp_mode));
279
280   if (blorp->lookup_shader(batch, &key, sizeof(key),
281                            &params->sf_prog_kernel, &params->sf_prog_data))
282      return true;
283
284   void *mem_ctx = ralloc_context(NULL);
285
286   const unsigned *program;
287   unsigned program_size;
288
289   struct brw_vue_map vue_map;
290   brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false);
291
292   struct brw_sf_prog_data prog_data_tmp;
293   program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
294                            &prog_data_tmp, &vue_map, &program_size);
295
296   bool result =
297      blorp->upload_shader(batch, &key, sizeof(key), program, program_size,
298                           (void *)&prog_data_tmp, sizeof(prog_data_tmp),
299                           &params->sf_prog_kernel, &params->sf_prog_data);
300
301   ralloc_free(mem_ctx);
302
303   return result;
304}
305
306void
307blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
308             uint32_t level, uint32_t start_layer, uint32_t num_layers,
309             enum isl_aux_op op)
310{
311   struct blorp_params params;
312   blorp_params_init(&params);
313
314   params.hiz_op = op;
315   params.full_surface_hiz_op = true;
316
317   for (uint32_t a = 0; a < num_layers; a++) {
318      const uint32_t layer = start_layer + a;
319
320      brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level,
321                                  layer, surf->surf->format, true);
322
323      /* Align the rectangle primitive to 8x4 pixels.
324       *
325       * During fast depth clears, the emitted rectangle primitive  must be
326       * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
327       * 11.5.3.1 Depth Buffer Clear (and the matching section in the
328       * Sandybridge PRM):
329       *
330       *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
331       *     aligned to an 8x4 pixel block relative to the upper left corner
332       *     of the depth buffer [...]
333       *
334       * For hiz resolves, the rectangle must also be 8x4 aligned. Item
335       * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
336       * Ivybridge simulator require the alignment.
337       *
338       * To be safe, let's just align the rect for all hiz operations and all
339       * hardware generations.
340       *
341       * However, for some miptree slices of a Z24 texture, emitting an 8x4
342       * aligned rectangle that covers the slice may clobber adjacent slices
343       * if we strictly adhered to the texture alignments specified in the
344       * PRM.  The Ivybridge PRM, Section "Alignment Unit Size", states that
345       * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
346       * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
347       * 8, which prevents the clobbering.
348       */
349      params.x1 = minify(params.depth.surf.logical_level0_px.width,
350                         params.depth.view.base_level);
351      params.y1 = minify(params.depth.surf.logical_level0_px.height,
352                         params.depth.view.base_level);
353      params.x1 = ALIGN(params.x1, 8);
354      params.y1 = ALIGN(params.y1, 4);
355
356      if (params.depth.view.base_level == 0) {
357         /* TODO: What about MSAA? */
358         params.depth.surf.logical_level0_px.width = params.x1;
359         params.depth.surf.logical_level0_px.height = params.y1;
360      }
361
362      params.dst.surf.samples = params.depth.surf.samples;
363      params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
364      params.depth_format =
365         isl_format_get_depth_format(surf->surf->format, false);
366      params.num_samples = params.depth.surf.samples;
367
368      batch->blorp->exec(batch, &params);
369   }
370}
371