1/* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef BLORP_GENX_EXEC_H 25#define BLORP_GENX_EXEC_H 26 27#include "blorp_priv.h" 28#include "dev/gen_device_info.h" 29#include "common/gen_sample_positions.h" 30#include "genxml/gen_macros.h" 31 32/** 33 * This file provides the blorp pipeline setup and execution functionality. 34 * It defines the following function: 35 * 36 * static void 37 * blorp_exec(struct blorp_context *blorp, void *batch_data, 38 * const struct blorp_params *params); 39 * 40 * It is the job of whoever includes this header to wrap this in something 41 * to get an externally visible symbol. 42 * 43 * In order for the blorp_exec function to work, the driver must provide 44 * implementations of the following static helper functions. 45 */ 46 47static void * 48blorp_emit_dwords(struct blorp_batch *batch, unsigned n); 49 50static uint64_t 51blorp_emit_reloc(struct blorp_batch *batch, 52 void *location, struct blorp_address address, uint32_t delta); 53 54static void * 55blorp_alloc_dynamic_state(struct blorp_batch *batch, 56 uint32_t size, 57 uint32_t alignment, 58 uint32_t *offset); 59static void * 60blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size, 61 struct blorp_address *addr); 62static void 63blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch, 64 const struct blorp_address *addrs, 65 unsigned num_vbs); 66 67#if GEN_GEN >= 8 68static struct blorp_address 69blorp_get_workaround_page(struct blorp_batch *batch); 70#endif 71 72static void 73blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries, 74 unsigned state_size, unsigned state_alignment, 75 uint32_t *bt_offset, uint32_t *surface_offsets, 76 void **surface_maps); 77 78static void 79blorp_flush_range(struct blorp_batch *batch, void *start, size_t size); 80 81static void 82blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset, 83 struct blorp_address address, uint32_t delta); 84 85static uint64_t 86blorp_get_surface_address(struct blorp_batch *batch, 87 struct blorp_address address); 88 89#if GEN_GEN >= 7 && GEN_GEN < 10 90static struct blorp_address 91blorp_get_surface_base_address(struct blorp_batch *batch); 92#endif 93 94static void 95blorp_emit_urb_config(struct blorp_batch *batch, 96 unsigned vs_entry_size, unsigned sf_entry_size); 97 98static void 99blorp_emit_pipeline(struct blorp_batch *batch, 100 const struct blorp_params *params); 101 102/***** BEGIN blorp_exec implementation ******/ 103 104static uint64_t 105_blorp_combine_address(struct blorp_batch *batch, void *location, 106 struct blorp_address address, uint32_t delta) 107{ 108 if (address.buffer == NULL) { 109 return address.offset + delta; 110 } else { 111 return blorp_emit_reloc(batch, location, address, delta); 112 } 113} 114 115#define __gen_address_type struct blorp_address 116#define __gen_user_data struct blorp_batch 117#define __gen_combine_address _blorp_combine_address 118 119#include "genxml/genX_pack.h" 120 121#define _blorp_cmd_length(cmd) cmd ## _length 122#define _blorp_cmd_length_bias(cmd) cmd ## _length_bias 123#define _blorp_cmd_header(cmd) cmd ## _header 124#define _blorp_cmd_pack(cmd) cmd ## _pack 125 126#define blorp_emit(batch, cmd, name) \ 127 for (struct cmd name = { _blorp_cmd_header(cmd) }, \ 128 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \ 129 __builtin_expect(_dst != NULL, 1); \ 130 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \ 131 _dst = NULL) 132 133#define blorp_emitn(batch, cmd, n, ...) ({ \ 134 uint32_t *_dw = blorp_emit_dwords(batch, n); \ 135 if (_dw) { \ 136 struct cmd template = { \ 137 _blorp_cmd_header(cmd), \ 138 .DWordLength = n - _blorp_cmd_length_bias(cmd), \ 139 __VA_ARGS__ \ 140 }; \ 141 _blorp_cmd_pack(cmd)(batch, _dw, &template); \ 142 } \ 143 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \ 144 }) 145 146#define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; }) 147 148#define blorp_emit_dynamic(batch, state, name, align, offset) \ 149 for (struct state name = STRUCT_ZERO(state), \ 150 *_dst = blorp_alloc_dynamic_state(batch, \ 151 _blorp_cmd_length(state) * 4, \ 152 align, offset); \ 153 __builtin_expect(_dst != NULL, 1); \ 154 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \ 155 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \ 156 _dst = NULL) 157 158/* 3DSTATE_URB 159 * 3DSTATE_URB_VS 160 * 3DSTATE_URB_HS 161 * 3DSTATE_URB_DS 162 * 3DSTATE_URB_GS 163 * 164 * Assign the entire URB to the VS. Even though the VS disabled, URB space 165 * is still needed because the clipper loads the VUE's from the URB. From 166 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE, 167 * Dword 1.15:0 "VS Number of URB Entries": 168 * This field is always used (even if VS Function Enable is DISABLED). 169 * 170 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can 171 * safely ignore it because this batch contains only one draw call. 172 * Because of URB corruption caused by allocating a previous GS unit 173 * URB entry to the VS unit, software is required to send a “GS NULL 174 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0) 175 * plus a dummy DRAW call before any case where VS will be taking over 176 * GS URB space. 177 * 178 * If the 3DSTATE_URB_VS is emitted, than the others must be also. 179 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS: 180 * 181 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be 182 * programmed in order for the programming of this state to be 183 * valid. 184 */ 185static void 186emit_urb_config(struct blorp_batch *batch, 187 const struct blorp_params *params) 188{ 189 /* Once vertex fetcher has written full VUE entries with complete 190 * header the space requirement is as follows per vertex (in bytes): 191 * 192 * Header Position Program constants 193 * +--------+------------+-------------------+ 194 * | 16 | 16 | n x 16 | 195 * +--------+------------+-------------------+ 196 * 197 * where 'n' stands for number of varying inputs expressed as vec4s. 198 */ 199 const unsigned num_varyings = 200 params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0; 201 const unsigned total_needed = 16 + 16 + num_varyings * 16; 202 203 /* The URB size is expressed in units of 64 bytes (512 bits) */ 204 const unsigned vs_entry_size = DIV_ROUND_UP(total_needed, 64); 205 206 const unsigned sf_entry_size = 207 params->sf_prog_data ? params->sf_prog_data->urb_entry_size : 0; 208 209 blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size); 210} 211 212#if GEN_GEN >= 7 213static void 214blorp_emit_memcpy(struct blorp_batch *batch, 215 struct blorp_address dst, 216 struct blorp_address src, 217 uint32_t size); 218#endif 219 220static void 221blorp_emit_vertex_data(struct blorp_batch *batch, 222 const struct blorp_params *params, 223 struct blorp_address *addr, 224 uint32_t *size) 225{ 226 const float vertices[] = { 227 /* v0 */ (float)params->x1, (float)params->y1, params->z, 228 /* v1 */ (float)params->x0, (float)params->y1, params->z, 229 /* v2 */ (float)params->x0, (float)params->y0, params->z, 230 }; 231 232 void *data = blorp_alloc_vertex_buffer(batch, sizeof(vertices), addr); 233 memcpy(data, vertices, sizeof(vertices)); 234 *size = sizeof(vertices); 235 blorp_flush_range(batch, data, *size); 236} 237 238static void 239blorp_emit_input_varying_data(struct blorp_batch *batch, 240 const struct blorp_params *params, 241 struct blorp_address *addr, 242 uint32_t *size) 243{ 244 const unsigned vec4_size_in_bytes = 4 * sizeof(float); 245 const unsigned max_num_varyings = 246 DIV_ROUND_UP(sizeof(params->wm_inputs), vec4_size_in_bytes); 247 const unsigned num_varyings = 248 params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0; 249 250 *size = 16 + num_varyings * vec4_size_in_bytes; 251 252 const uint32_t *const inputs_src = (const uint32_t *)¶ms->wm_inputs; 253 void *data = blorp_alloc_vertex_buffer(batch, *size, addr); 254 uint32_t *inputs = data; 255 256 /* Copy in the VS inputs */ 257 assert(sizeof(params->vs_inputs) == 16); 258 memcpy(inputs, ¶ms->vs_inputs, sizeof(params->vs_inputs)); 259 inputs += 4; 260 261 if (params->wm_prog_data) { 262 /* Walk over the attribute slots, determine if the attribute is used by 263 * the program and when necessary copy the values from the input storage 264 * to the vertex data buffer. 265 */ 266 for (unsigned i = 0; i < max_num_varyings; i++) { 267 const gl_varying_slot attr = VARYING_SLOT_VAR0 + i; 268 269 const int input_index = params->wm_prog_data->urb_setup[attr]; 270 if (input_index < 0) 271 continue; 272 273 memcpy(inputs, inputs_src + i * 4, vec4_size_in_bytes); 274 275 inputs += 4; 276 } 277 } 278 279 blorp_flush_range(batch, data, *size); 280 281 if (params->dst_clear_color_as_input) { 282#if GEN_GEN >= 7 283 /* In this case, the clear color isn't known statically and instead 284 * comes in through an indirect which we have to copy into the vertex 285 * buffer before we execute the 3DPRIMITIVE. We already copied the 286 * value of params->wm_inputs.clear_color into the vertex buffer in the 287 * loop above. Now we emit code to stomp it from the GPU with the 288 * actual clear color value. 289 */ 290 assert(num_varyings == 1); 291 292 /* The clear color is the first thing after the header */ 293 struct blorp_address clear_color_input_addr = *addr; 294 clear_color_input_addr.offset += 16; 295 296 const unsigned clear_color_size = 297 GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4; 298 blorp_emit_memcpy(batch, clear_color_input_addr, 299 params->dst.clear_color_addr, 300 clear_color_size); 301#else 302 unreachable("MCS partial resolve is not a thing on SNB and earlier"); 303#endif 304 } 305} 306 307static void 308blorp_fill_vertex_buffer_state(struct blorp_batch *batch, 309 struct GENX(VERTEX_BUFFER_STATE) *vb, 310 unsigned idx, 311 struct blorp_address addr, uint32_t size, 312 uint32_t stride) 313{ 314 vb[idx].VertexBufferIndex = idx; 315 vb[idx].BufferStartingAddress = addr; 316 vb[idx].BufferPitch = stride; 317 318#if GEN_GEN >= 6 319 vb[idx].MOCS = addr.mocs; 320#endif 321 322#if GEN_GEN >= 7 323 vb[idx].AddressModifyEnable = true; 324#endif 325 326#if GEN_GEN >= 8 327 vb[idx].BufferSize = size; 328#elif GEN_GEN >= 5 329 vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA; 330 vb[idx].EndAddress = vb[idx].BufferStartingAddress; 331 vb[idx].EndAddress.offset += size - 1; 332#elif GEN_GEN == 4 333 vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA; 334 vb[idx].MaxIndex = stride > 0 ? size / stride : 0; 335#endif 336} 337 338static void 339blorp_emit_vertex_buffers(struct blorp_batch *batch, 340 const struct blorp_params *params) 341{ 342 struct GENX(VERTEX_BUFFER_STATE) vb[3]; 343 uint32_t num_vbs = 2; 344 memset(vb, 0, sizeof(vb)); 345 346 struct blorp_address addrs[2] = {}; 347 uint32_t size; 348 blorp_emit_vertex_data(batch, params, &addrs[0], &size); 349 blorp_fill_vertex_buffer_state(batch, vb, 0, addrs[0], size, 350 3 * sizeof(float)); 351 352 blorp_emit_input_varying_data(batch, params, &addrs[1], &size); 353 blorp_fill_vertex_buffer_state(batch, vb, 1, addrs[1], size, 0); 354 355 blorp_vf_invalidate_for_vb_48b_transitions(batch, addrs, num_vbs); 356 357 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); 358 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); 359 if (!dw) 360 return; 361 362 for (unsigned i = 0; i < num_vbs; i++) { 363 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]); 364 dw += GENX(VERTEX_BUFFER_STATE_length); 365 } 366} 367 368static void 369blorp_emit_vertex_elements(struct blorp_batch *batch, 370 const struct blorp_params *params) 371{ 372 const unsigned num_varyings = 373 params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0; 374 bool need_ndc = batch->blorp->compiler->devinfo->gen <= 5; 375 const unsigned num_elements = 2 + need_ndc + num_varyings; 376 377 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; 378 memset(ve, 0, num_elements * sizeof(*ve)); 379 380 /* Setup VBO for the rectangle primitive.. 381 * 382 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three 383 * vertices. The vertices reside in screen space with DirectX 384 * coordinates (that is, (0, 0) is the upper left corner). 385 * 386 * v2 ------ implied 387 * | | 388 * | | 389 * v1 ----- v0 390 * 391 * Since the VS is disabled, the clipper loads each VUE directly from 392 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and 393 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows: 394 * dw0: Reserved, MBZ. 395 * dw1: Render Target Array Index. Below vertex fetcher gets programmed 396 * to assign this with primitive instance identifier which will be 397 * used for layered clears. All other renders have only one instance 398 * and therefore the value will be effectively zero. 399 * dw2: Viewport Index. The HiZ op disables viewport mapping and 400 * scissoring, so set the dword to 0. 401 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, 402 * so set the dword to 0. 403 * dw4: Vertex Position X. 404 * dw5: Vertex Position Y. 405 * dw6: Vertex Position Z. 406 * dw7: Vertex Position W. 407 * 408 * dw8: Flat vertex input 0 409 * dw9: Flat vertex input 1 410 * ... 411 * dwn: Flat vertex input n - 8 412 * 413 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1 414 * "Vertex URB Entry (VUE) Formats". 415 * 416 * Only vertex position X and Y are going to be variable, Z is fixed to 417 * zero and W to one. Header words dw0,2,3 are zero. There is no need to 418 * include the fixed values in the vertex buffer. Vertex fetcher can be 419 * instructed to fill vertex elements with constant values of one and zero 420 * instead of reading them from the buffer. 421 * Flat inputs are program constants that are not interpolated. Moreover 422 * their values will be the same between vertices. 423 * 424 * See the vertex element setup below. 425 */ 426 unsigned slot = 0; 427 428 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { 429 .VertexBufferIndex = 1, 430 .Valid = true, 431 .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, 432 .SourceElementOffset = 0, 433 .Component0Control = VFCOMP_STORE_SRC, 434 435 /* From Gen8 onwards hardware is no more instructed to overwrite 436 * components using an element specifier. Instead one has separate 437 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it. 438 */ 439#if GEN_GEN >= 8 440 .Component1Control = VFCOMP_STORE_0, 441#elif GEN_GEN >= 5 442 .Component1Control = VFCOMP_STORE_IID, 443#else 444 .Component1Control = VFCOMP_STORE_0, 445#endif 446 .Component2Control = VFCOMP_STORE_0, 447 .Component3Control = VFCOMP_STORE_0, 448#if GEN_GEN <= 5 449 .DestinationElementOffset = slot * 4, 450#endif 451 }; 452 slot++; 453 454#if GEN_GEN <= 5 455 /* On Iron Lake and earlier, a native device coordinates version of the 456 * position goes right after the normal VUE header and before position. 457 * Since w == 1 for all of our coordinates, this is just a copy of the 458 * position. 459 */ 460 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { 461 .VertexBufferIndex = 0, 462 .Valid = true, 463 .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT, 464 .SourceElementOffset = 0, 465 .Component0Control = VFCOMP_STORE_SRC, 466 .Component1Control = VFCOMP_STORE_SRC, 467 .Component2Control = VFCOMP_STORE_SRC, 468 .Component3Control = VFCOMP_STORE_1_FP, 469 .DestinationElementOffset = slot * 4, 470 }; 471 slot++; 472#endif 473 474 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { 475 .VertexBufferIndex = 0, 476 .Valid = true, 477 .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT, 478 .SourceElementOffset = 0, 479 .Component0Control = VFCOMP_STORE_SRC, 480 .Component1Control = VFCOMP_STORE_SRC, 481 .Component2Control = VFCOMP_STORE_SRC, 482 .Component3Control = VFCOMP_STORE_1_FP, 483#if GEN_GEN <= 5 484 .DestinationElementOffset = slot * 4, 485#endif 486 }; 487 slot++; 488 489 for (unsigned i = 0; i < num_varyings; ++i) { 490 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) { 491 .VertexBufferIndex = 1, 492 .Valid = true, 493 .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT, 494 .SourceElementOffset = 16 + i * 4 * sizeof(float), 495 .Component0Control = VFCOMP_STORE_SRC, 496 .Component1Control = VFCOMP_STORE_SRC, 497 .Component2Control = VFCOMP_STORE_SRC, 498 .Component3Control = VFCOMP_STORE_SRC, 499#if GEN_GEN <= 5 500 .DestinationElementOffset = slot * 4, 501#endif 502 }; 503 slot++; 504 } 505 506 const unsigned num_dwords = 507 1 + GENX(VERTEX_ELEMENT_STATE_length) * num_elements; 508 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_ELEMENTS), num_dwords); 509 if (!dw) 510 return; 511 512 for (unsigned i = 0; i < num_elements; i++) { 513 GENX(VERTEX_ELEMENT_STATE_pack)(batch, dw, &ve[i]); 514 dw += GENX(VERTEX_ELEMENT_STATE_length); 515 } 516 517 blorp_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) { 518 vf.StatisticsEnable = false; 519 } 520 521#if GEN_GEN >= 8 522 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with 523 * primitive instance identifier. This is used for layered clears. 524 */ 525 blorp_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs) { 526 sgvs.InstanceIDEnable = true; 527 sgvs.InstanceIDComponentNumber = COMP_1; 528 sgvs.InstanceIDElementOffset = 0; 529 } 530 531 for (unsigned i = 0; i < num_elements; i++) { 532 blorp_emit(batch, GENX(3DSTATE_VF_INSTANCING), vf) { 533 vf.VertexElementIndex = i; 534 vf.InstancingEnable = false; 535 } 536 } 537 538 blorp_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) { 539 topo.PrimitiveTopologyType = _3DPRIM_RECTLIST; 540 } 541#endif 542} 543 544/* 3DSTATE_VIEWPORT_STATE_POINTERS */ 545static uint32_t 546blorp_emit_cc_viewport(struct blorp_batch *batch) 547{ 548 uint32_t cc_vp_offset; 549 blorp_emit_dynamic(batch, GENX(CC_VIEWPORT), vp, 32, &cc_vp_offset) { 550 vp.MinimumDepth = 0.0; 551 vp.MaximumDepth = 1.0; 552 } 553 554#if GEN_GEN >= 7 555 blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), vsp) { 556 vsp.CCViewportPointer = cc_vp_offset; 557 } 558#elif GEN_GEN == 6 559 blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vsp) { 560 vsp.CCViewportStateChange = true; 561 vsp.PointertoCC_VIEWPORT = cc_vp_offset; 562 } 563#endif 564 565 return cc_vp_offset; 566} 567 568static uint32_t 569blorp_emit_sampler_state(struct blorp_batch *batch) 570{ 571 uint32_t offset; 572 blorp_emit_dynamic(batch, GENX(SAMPLER_STATE), sampler, 32, &offset) { 573 sampler.MipModeFilter = MIPFILTER_NONE; 574 sampler.MagModeFilter = MAPFILTER_LINEAR; 575 sampler.MinModeFilter = MAPFILTER_LINEAR; 576 sampler.MinLOD = 0; 577 sampler.MaxLOD = 0; 578 sampler.TCXAddressControlMode = TCM_CLAMP; 579 sampler.TCYAddressControlMode = TCM_CLAMP; 580 sampler.TCZAddressControlMode = TCM_CLAMP; 581 sampler.MaximumAnisotropy = RATIO21; 582 sampler.RAddressMinFilterRoundingEnable = true; 583 sampler.RAddressMagFilterRoundingEnable = true; 584 sampler.VAddressMinFilterRoundingEnable = true; 585 sampler.VAddressMagFilterRoundingEnable = true; 586 sampler.UAddressMinFilterRoundingEnable = true; 587 sampler.UAddressMagFilterRoundingEnable = true; 588#if GEN_GEN > 6 589 sampler.NonnormalizedCoordinateEnable = true; 590#endif 591 } 592 593#if GEN_GEN >= 7 594 blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS), ssp) { 595 ssp.PointertoPSSamplerState = offset; 596 } 597#elif GEN_GEN == 6 598 blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS), ssp) { 599 ssp.VSSamplerStateChange = true; 600 ssp.GSSamplerStateChange = true; 601 ssp.PSSamplerStateChange = true; 602 ssp.PointertoPSSamplerState = offset; 603 } 604#endif 605 606 return offset; 607} 608 609/* What follows is the code for setting up a "pipeline" on Sandy Bridge and 610 * later hardware. This file will be included by i965 for gen4-5 as well, so 611 * this code is guarded by GEN_GEN >= 6. 612 */ 613#if GEN_GEN >= 6 614 615static void 616blorp_emit_vs_config(struct blorp_batch *batch, 617 const struct blorp_params *params) 618{ 619 struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data; 620 assert(!vs_prog_data || GEN_GEN < 11 || 621 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8); 622 623 blorp_emit(batch, GENX(3DSTATE_VS), vs) { 624 if (vs_prog_data) { 625 vs.Enable = true; 626 627 vs.KernelStartPointer = params->vs_prog_kernel; 628 629 vs.DispatchGRFStartRegisterForURBData = 630 vs_prog_data->base.base.dispatch_grf_start_reg; 631 vs.VertexURBEntryReadLength = 632 vs_prog_data->base.urb_read_length; 633 vs.VertexURBEntryReadOffset = 0; 634 635 vs.MaximumNumberofThreads = 636 batch->blorp->isl_dev->info->max_vs_threads - 1; 637 638#if GEN_GEN >= 8 639 vs.SIMD8DispatchEnable = 640 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8; 641#endif 642 } 643 } 644} 645 646static void 647blorp_emit_sf_config(struct blorp_batch *batch, 648 const struct blorp_params *params) 649{ 650 const struct brw_wm_prog_data *prog_data = params->wm_prog_data; 651 652 /* 3DSTATE_SF 653 * 654 * Disable ViewportTransformEnable (dw2.1) 655 * 656 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D 657 * Primitives Overview": 658 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the 659 * use of screen- space coordinates). 660 * 661 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3) 662 * and BackFaceFillMode (dw2.5:6) to SOLID(0). 663 * 664 * From the Sandy Bridge PRM, Volume 2, Part 1, Section 665 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: 666 * SOLID: Any triangle or rectangle object found to be front-facing 667 * is rendered as a solid object. This setting is required when 668 * (rendering rectangle (RECTLIST) objects. 669 */ 670 671#if GEN_GEN >= 8 672 673 blorp_emit(batch, GENX(3DSTATE_SF), sf); 674 675 blorp_emit(batch, GENX(3DSTATE_RASTER), raster) { 676 raster.CullMode = CULLMODE_NONE; 677 } 678 679 blorp_emit(batch, GENX(3DSTATE_SBE), sbe) { 680 sbe.VertexURBEntryReadOffset = 1; 681 if (prog_data) { 682 sbe.NumberofSFOutputAttributes = prog_data->num_varying_inputs; 683 sbe.VertexURBEntryReadLength = brw_blorp_get_urb_length(prog_data); 684 sbe.ConstantInterpolationEnable = prog_data->flat_inputs; 685 } else { 686 sbe.NumberofSFOutputAttributes = 0; 687 sbe.VertexURBEntryReadLength = 1; 688 } 689 sbe.ForceVertexURBEntryReadLength = true; 690 sbe.ForceVertexURBEntryReadOffset = true; 691 692#if GEN_GEN >= 9 693 for (unsigned i = 0; i < 32; i++) 694 sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; 695#endif 696 } 697 698#elif GEN_GEN >= 7 699 700 blorp_emit(batch, GENX(3DSTATE_SF), sf) { 701 sf.FrontFaceFillMode = FILL_MODE_SOLID; 702 sf.BackFaceFillMode = FILL_MODE_SOLID; 703 704 sf.MultisampleRasterizationMode = params->num_samples > 1 ? 705 MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL; 706 707#if GEN_GEN == 7 708 sf.DepthBufferSurfaceFormat = params->depth_format; 709#endif 710 } 711 712 blorp_emit(batch, GENX(3DSTATE_SBE), sbe) { 713 sbe.VertexURBEntryReadOffset = 1; 714 if (prog_data) { 715 sbe.NumberofSFOutputAttributes = prog_data->num_varying_inputs; 716 sbe.VertexURBEntryReadLength = brw_blorp_get_urb_length(prog_data); 717 sbe.ConstantInterpolationEnable = prog_data->flat_inputs; 718 } else { 719 sbe.NumberofSFOutputAttributes = 0; 720 sbe.VertexURBEntryReadLength = 1; 721 } 722 } 723 724#else /* GEN_GEN <= 6 */ 725 726 blorp_emit(batch, GENX(3DSTATE_SF), sf) { 727 sf.FrontFaceFillMode = FILL_MODE_SOLID; 728 sf.BackFaceFillMode = FILL_MODE_SOLID; 729 730 sf.MultisampleRasterizationMode = params->num_samples > 1 ? 731 MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL; 732 733 sf.VertexURBEntryReadOffset = 1; 734 if (prog_data) { 735 sf.NumberofSFOutputAttributes = prog_data->num_varying_inputs; 736 sf.VertexURBEntryReadLength = brw_blorp_get_urb_length(prog_data); 737 sf.ConstantInterpolationEnable = prog_data->flat_inputs; 738 } else { 739 sf.NumberofSFOutputAttributes = 0; 740 sf.VertexURBEntryReadLength = 1; 741 } 742 } 743 744#endif /* GEN_GEN */ 745} 746 747static void 748blorp_emit_ps_config(struct blorp_batch *batch, 749 const struct blorp_params *params) 750{ 751 const struct brw_wm_prog_data *prog_data = params->wm_prog_data; 752 753 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be 754 * nonzero to prevent the GPU from hanging. While the documentation doesn't 755 * mention this explicitly, it notes that the valid range for the field is 756 * [1,39] = [2,40] threads, which excludes zero. 757 * 758 * To be safe (and to minimize extraneous code) we go ahead and fully 759 * configure the WM state whether or not there is a WM program. 760 */ 761 762#if GEN_GEN >= 8 763 764 blorp_emit(batch, GENX(3DSTATE_WM), wm); 765 766 blorp_emit(batch, GENX(3DSTATE_PS), ps) { 767 if (params->src.enabled) { 768 ps.SamplerCount = 1; /* Up to 4 samplers */ 769 ps.BindingTableEntryCount = 2; 770 } else { 771 ps.BindingTableEntryCount = 1; 772 } 773 774 /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to 775 * disable prefetching of binding tables on A0 and B0 steppings. 776 * TODO: Revisit this WA on C0 stepping. 777 */ 778 if (GEN_GEN == 11) 779 ps.BindingTableEntryCount = 0; 780 781 if (prog_data) { 782 ps._8PixelDispatchEnable = prog_data->dispatch_8; 783 ps._16PixelDispatchEnable = prog_data->dispatch_16; 784 ps._32PixelDispatchEnable = prog_data->dispatch_32; 785 786 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable: 787 * 788 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32 789 * Dispatch must not be enabled for PER_PIXEL dispatch mode." 790 * 791 * Since 16x MSAA is first introduced on SKL, we don't need to apply 792 * the workaround on any older hardware. 793 */ 794 if (GEN_GEN >= 9 && !prog_data->persample_dispatch && 795 params->num_samples == 16) { 796 assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable); 797 ps._32PixelDispatchEnable = false; 798 } 799 800 ps.DispatchGRFStartRegisterForConstantSetupData0 = 801 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0); 802 ps.DispatchGRFStartRegisterForConstantSetupData1 = 803 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1); 804 ps.DispatchGRFStartRegisterForConstantSetupData2 = 805 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2); 806 807 ps.KernelStartPointer0 = params->wm_prog_kernel + 808 brw_wm_prog_data_prog_offset(prog_data, ps, 0); 809 ps.KernelStartPointer1 = params->wm_prog_kernel + 810 brw_wm_prog_data_prog_offset(prog_data, ps, 1); 811 ps.KernelStartPointer2 = params->wm_prog_kernel + 812 brw_wm_prog_data_prog_offset(prog_data, ps, 2); 813 } 814 815 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64 816 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is 817 * k, it implies 2(k+1) threads. It implicitly scales for different GT 818 * levels (which have some # of PSDs). 819 * 820 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1. 821 */ 822 if (GEN_GEN >= 9) 823 ps.MaximumNumberofThreadsPerPSD = 64 - 1; 824 else 825 ps.MaximumNumberofThreadsPerPSD = 64 - 2; 826 827 switch (params->fast_clear_op) { 828 case ISL_AUX_OP_NONE: 829 break; 830#if GEN_GEN >= 9 831 case ISL_AUX_OP_PARTIAL_RESOLVE: 832 ps.RenderTargetResolveType = RESOLVE_PARTIAL; 833 break; 834 case ISL_AUX_OP_FULL_RESOLVE: 835 ps.RenderTargetResolveType = RESOLVE_FULL; 836 break; 837#else 838 case ISL_AUX_OP_FULL_RESOLVE: 839 ps.RenderTargetResolveEnable = true; 840 break; 841#endif 842 case ISL_AUX_OP_FAST_CLEAR: 843 ps.RenderTargetFastClearEnable = true; 844 break; 845 default: 846 unreachable("Invalid fast clear op"); 847 } 848 } 849 850 blorp_emit(batch, GENX(3DSTATE_PS_EXTRA), psx) { 851 if (prog_data) { 852 psx.PixelShaderValid = true; 853 psx.AttributeEnable = prog_data->num_varying_inputs > 0; 854 psx.PixelShaderIsPerSample = prog_data->persample_dispatch; 855 } 856 857 if (params->src.enabled) 858 psx.PixelShaderKillsPixel = true; 859 } 860 861#elif GEN_GEN >= 7 862 863 blorp_emit(batch, GENX(3DSTATE_WM), wm) { 864 switch (params->hiz_op) { 865 case ISL_AUX_OP_FAST_CLEAR: 866 wm.DepthBufferClear = true; 867 break; 868 case ISL_AUX_OP_FULL_RESOLVE: 869 wm.DepthBufferResolveEnable = true; 870 break; 871 case ISL_AUX_OP_AMBIGUATE: 872 wm.HierarchicalDepthBufferResolveEnable = true; 873 break; 874 case ISL_AUX_OP_NONE: 875 break; 876 default: 877 unreachable("not reached"); 878 } 879 880 if (prog_data) 881 wm.ThreadDispatchEnable = true; 882 883 if (params->src.enabled) 884 wm.PixelShaderKillsPixel = true; 885 886 if (params->num_samples > 1) { 887 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN; 888 wm.MultisampleDispatchMode = 889 (prog_data && prog_data->persample_dispatch) ? 890 MSDISPMODE_PERSAMPLE : MSDISPMODE_PERPIXEL; 891 } else { 892 wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL; 893 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE; 894 } 895 } 896 897 blorp_emit(batch, GENX(3DSTATE_PS), ps) { 898 ps.MaximumNumberofThreads = 899 batch->blorp->isl_dev->info->max_wm_threads - 1; 900 901#if GEN_IS_HASWELL 902 ps.SampleMask = 1; 903#endif 904 905 if (prog_data) { 906 ps._8PixelDispatchEnable = prog_data->dispatch_8; 907 ps._16PixelDispatchEnable = prog_data->dispatch_16; 908 ps._32PixelDispatchEnable = prog_data->dispatch_32; 909 910 ps.DispatchGRFStartRegisterForConstantSetupData0 = 911 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0); 912 ps.DispatchGRFStartRegisterForConstantSetupData1 = 913 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1); 914 ps.DispatchGRFStartRegisterForConstantSetupData2 = 915 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2); 916 917 ps.KernelStartPointer0 = params->wm_prog_kernel + 918 brw_wm_prog_data_prog_offset(prog_data, ps, 0); 919 ps.KernelStartPointer1 = params->wm_prog_kernel + 920 brw_wm_prog_data_prog_offset(prog_data, ps, 1); 921 ps.KernelStartPointer2 = params->wm_prog_kernel + 922 brw_wm_prog_data_prog_offset(prog_data, ps, 2); 923 924 ps.AttributeEnable = prog_data->num_varying_inputs > 0; 925 } else { 926 /* Gen7 hardware gets angry if we don't enable at least one dispatch 927 * mode, so just enable 16-pixel dispatch if we don't have a program. 928 */ 929 ps._16PixelDispatchEnable = true; 930 } 931 932 if (params->src.enabled) 933 ps.SamplerCount = 1; /* Up to 4 samplers */ 934 935 switch (params->fast_clear_op) { 936 case ISL_AUX_OP_NONE: 937 break; 938 case ISL_AUX_OP_FULL_RESOLVE: 939 ps.RenderTargetResolveEnable = true; 940 break; 941 case ISL_AUX_OP_FAST_CLEAR: 942 ps.RenderTargetFastClearEnable = true; 943 break; 944 default: 945 unreachable("Invalid fast clear op"); 946 } 947 } 948 949#else /* GEN_GEN <= 6 */ 950 951 blorp_emit(batch, GENX(3DSTATE_WM), wm) { 952 wm.MaximumNumberofThreads = 953 batch->blorp->isl_dev->info->max_wm_threads - 1; 954 955 switch (params->hiz_op) { 956 case ISL_AUX_OP_FAST_CLEAR: 957 wm.DepthBufferClear = true; 958 break; 959 case ISL_AUX_OP_FULL_RESOLVE: 960 wm.DepthBufferResolveEnable = true; 961 break; 962 case ISL_AUX_OP_AMBIGUATE: 963 wm.HierarchicalDepthBufferResolveEnable = true; 964 break; 965 case ISL_AUX_OP_NONE: 966 break; 967 default: 968 unreachable("not reached"); 969 } 970 971 if (prog_data) { 972 wm.ThreadDispatchEnable = true; 973 974 wm._8PixelDispatchEnable = prog_data->dispatch_8; 975 wm._16PixelDispatchEnable = prog_data->dispatch_16; 976 wm._32PixelDispatchEnable = prog_data->dispatch_32; 977 978 wm.DispatchGRFStartRegisterForConstantSetupData0 = 979 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 0); 980 wm.DispatchGRFStartRegisterForConstantSetupData1 = 981 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 1); 982 wm.DispatchGRFStartRegisterForConstantSetupData2 = 983 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 2); 984 985 wm.KernelStartPointer0 = params->wm_prog_kernel + 986 brw_wm_prog_data_prog_offset(prog_data, wm, 0); 987 wm.KernelStartPointer1 = params->wm_prog_kernel + 988 brw_wm_prog_data_prog_offset(prog_data, wm, 1); 989 wm.KernelStartPointer2 = params->wm_prog_kernel + 990 brw_wm_prog_data_prog_offset(prog_data, wm, 2); 991 992 wm.NumberofSFOutputAttributes = prog_data->num_varying_inputs; 993 } 994 995 if (params->src.enabled) { 996 wm.SamplerCount = 1; /* Up to 4 samplers */ 997 wm.PixelShaderKillsPixel = true; /* TODO: temporarily smash on */ 998 } 999 1000 if (params->num_samples > 1) { 1001 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN; 1002 wm.MultisampleDispatchMode = 1003 (prog_data && prog_data->persample_dispatch) ? 1004 MSDISPMODE_PERSAMPLE : MSDISPMODE_PERPIXEL; 1005 } else { 1006 wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL; 1007 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE; 1008 } 1009 } 1010 1011#endif /* GEN_GEN */ 1012} 1013 1014static uint32_t 1015blorp_emit_blend_state(struct blorp_batch *batch, 1016 const struct blorp_params *params) 1017{ 1018 struct GENX(BLEND_STATE) blend; 1019 memset(&blend, 0, sizeof(blend)); 1020 1021 uint32_t offset; 1022 int size = GENX(BLEND_STATE_length) * 4; 1023 size += GENX(BLEND_STATE_ENTRY_length) * 4 * params->num_draw_buffers; 1024 uint32_t *state = blorp_alloc_dynamic_state(batch, size, 64, &offset); 1025 uint32_t *pos = state; 1026 1027 GENX(BLEND_STATE_pack)(NULL, pos, &blend); 1028 pos += GENX(BLEND_STATE_length); 1029 1030 for (unsigned i = 0; i < params->num_draw_buffers; ++i) { 1031 struct GENX(BLEND_STATE_ENTRY) entry = { 1032 .PreBlendColorClampEnable = true, 1033 .PostBlendColorClampEnable = true, 1034 .ColorClampRange = COLORCLAMP_RTFORMAT, 1035 1036 .WriteDisableRed = params->color_write_disable[0], 1037 .WriteDisableGreen = params->color_write_disable[1], 1038 .WriteDisableBlue = params->color_write_disable[2], 1039 .WriteDisableAlpha = params->color_write_disable[3], 1040 }; 1041 GENX(BLEND_STATE_ENTRY_pack)(NULL, pos, &entry); 1042 pos += GENX(BLEND_STATE_ENTRY_length); 1043 } 1044 1045 blorp_flush_range(batch, state, size); 1046 1047#if GEN_GEN >= 7 1048 blorp_emit(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), sp) { 1049 sp.BlendStatePointer = offset; 1050#if GEN_GEN >= 8 1051 sp.BlendStatePointerValid = true; 1052#endif 1053 } 1054#endif 1055 1056#if GEN_GEN >= 8 1057 blorp_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) { 1058 ps_blend.HasWriteableRT = true; 1059 } 1060#endif 1061 1062 return offset; 1063} 1064 1065static uint32_t 1066blorp_emit_color_calc_state(struct blorp_batch *batch, 1067 MAYBE_UNUSED const struct blorp_params *params) 1068{ 1069 uint32_t offset; 1070 blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { 1071#if GEN_GEN <= 8 1072 cc.StencilReferenceValue = params->stencil_ref; 1073#endif 1074 } 1075 1076#if GEN_GEN >= 7 1077 blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), sp) { 1078 sp.ColorCalcStatePointer = offset; 1079#if GEN_GEN >= 8 1080 sp.ColorCalcStatePointerValid = true; 1081#endif 1082 } 1083#endif 1084 1085 return offset; 1086} 1087 1088static uint32_t 1089blorp_emit_depth_stencil_state(struct blorp_batch *batch, 1090 const struct blorp_params *params) 1091{ 1092#if GEN_GEN >= 8 1093 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = { 1094 GENX(3DSTATE_WM_DEPTH_STENCIL_header), 1095 }; 1096#else 1097 struct GENX(DEPTH_STENCIL_STATE) ds = { 0 }; 1098#endif 1099 1100 if (params->depth.enabled) { 1101 ds.DepthBufferWriteEnable = true; 1102 1103 switch (params->hiz_op) { 1104 case ISL_AUX_OP_NONE: 1105 ds.DepthTestEnable = true; 1106 ds.DepthTestFunction = COMPAREFUNCTION_ALWAYS; 1107 break; 1108 1109 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1: 1110 * - 7.5.3.1 Depth Buffer Clear 1111 * - 7.5.3.2 Depth Buffer Resolve 1112 * - 7.5.3.3 Hierarchical Depth Buffer Resolve 1113 */ 1114 case ISL_AUX_OP_FULL_RESOLVE: 1115 ds.DepthTestEnable = true; 1116 ds.DepthTestFunction = COMPAREFUNCTION_NEVER; 1117 break; 1118 1119 case ISL_AUX_OP_FAST_CLEAR: 1120 case ISL_AUX_OP_AMBIGUATE: 1121 ds.DepthTestEnable = false; 1122 break; 1123 case ISL_AUX_OP_PARTIAL_RESOLVE: 1124 unreachable("Invalid HIZ op"); 1125 } 1126 } 1127 1128 if (params->stencil.enabled) { 1129 ds.StencilBufferWriteEnable = true; 1130 ds.StencilTestEnable = true; 1131 ds.DoubleSidedStencilEnable = false; 1132 1133 ds.StencilTestFunction = COMPAREFUNCTION_ALWAYS; 1134 ds.StencilPassDepthPassOp = STENCILOP_REPLACE; 1135 1136 ds.StencilWriteMask = params->stencil_mask; 1137#if GEN_GEN >= 9 1138 ds.StencilReferenceValue = params->stencil_ref; 1139#endif 1140 } 1141 1142#if GEN_GEN >= 8 1143 uint32_t offset = 0; 1144 uint32_t *dw = blorp_emit_dwords(batch, 1145 GENX(3DSTATE_WM_DEPTH_STENCIL_length)); 1146 if (!dw) 1147 return 0; 1148 1149 GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &ds); 1150#else 1151 uint32_t offset; 1152 void *state = blorp_alloc_dynamic_state(batch, 1153 GENX(DEPTH_STENCIL_STATE_length) * 4, 1154 64, &offset); 1155 GENX(DEPTH_STENCIL_STATE_pack)(NULL, state, &ds); 1156 blorp_flush_range(batch, state, GENX(DEPTH_STENCIL_STATE_length) * 4); 1157#endif 1158 1159#if GEN_GEN == 7 1160 blorp_emit(batch, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), sp) { 1161 sp.PointertoDEPTH_STENCIL_STATE = offset; 1162 } 1163#endif 1164 1165 return offset; 1166} 1167 1168static void 1169blorp_emit_3dstate_multisample(struct blorp_batch *batch, 1170 const struct blorp_params *params) 1171{ 1172 blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { 1173 ms.NumberofMultisamples = __builtin_ffs(params->num_samples) - 1; 1174 1175#if GEN_GEN >= 8 1176 /* The PRM says that this bit is valid only for DX9: 1177 * 1178 * SW can choose to set this bit only for DX9 API. DX10/OGL API's 1179 * should not have any effect by setting or not setting this bit. 1180 */ 1181 ms.PixelPositionOffsetEnable = false; 1182#elif GEN_GEN >= 7 1183 1184 switch (params->num_samples) { 1185 case 1: 1186 GEN_SAMPLE_POS_1X(ms.Sample); 1187 break; 1188 case 2: 1189 GEN_SAMPLE_POS_2X(ms.Sample); 1190 break; 1191 case 4: 1192 GEN_SAMPLE_POS_4X(ms.Sample); 1193 break; 1194 case 8: 1195 GEN_SAMPLE_POS_8X(ms.Sample); 1196 break; 1197 default: 1198 break; 1199 } 1200#else 1201 GEN_SAMPLE_POS_4X(ms.Sample); 1202#endif 1203 ms.PixelLocation = CENTER; 1204 } 1205} 1206 1207static void 1208blorp_emit_pipeline(struct blorp_batch *batch, 1209 const struct blorp_params *params) 1210{ 1211 uint32_t blend_state_offset = 0; 1212 uint32_t color_calc_state_offset; 1213 uint32_t depth_stencil_state_offset; 1214 1215 emit_urb_config(batch, params); 1216 1217 if (params->wm_prog_data) { 1218 blend_state_offset = blorp_emit_blend_state(batch, params); 1219 } 1220 color_calc_state_offset = blorp_emit_color_calc_state(batch, params); 1221 depth_stencil_state_offset = blorp_emit_depth_stencil_state(batch, params); 1222 1223#if GEN_GEN == 6 1224 /* 3DSTATE_CC_STATE_POINTERS 1225 * 1226 * The pointer offsets are relative to 1227 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. 1228 * 1229 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE. 1230 * 1231 * The dynamic state emit helpers emit their own STATE_POINTERS packets on 1232 * gen7+. However, on gen6 and earlier, they're all lumpped together in 1233 * one CC_STATE_POINTERS packet so we have to emit that here. 1234 */ 1235 blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), cc) { 1236 cc.BLEND_STATEChange = true; 1237 cc.ColorCalcStatePointerValid = true; 1238 cc.DEPTH_STENCIL_STATEChange = true; 1239 cc.PointertoBLEND_STATE = blend_state_offset; 1240 cc.ColorCalcStatePointer = color_calc_state_offset; 1241 cc.PointertoDEPTH_STENCIL_STATE = depth_stencil_state_offset; 1242 } 1243#else 1244 (void)blend_state_offset; 1245 (void)color_calc_state_offset; 1246 (void)depth_stencil_state_offset; 1247#endif 1248 1249 blorp_emit(batch, GENX(3DSTATE_CONSTANT_VS), vs); 1250#if GEN_GEN >= 7 1251 blorp_emit(batch, GENX(3DSTATE_CONSTANT_HS), hs); 1252 blorp_emit(batch, GENX(3DSTATE_CONSTANT_DS), DS); 1253#endif 1254 blorp_emit(batch, GENX(3DSTATE_CONSTANT_GS), gs); 1255 blorp_emit(batch, GENX(3DSTATE_CONSTANT_PS), ps); 1256 1257 if (params->src.enabled) 1258 blorp_emit_sampler_state(batch); 1259 1260 blorp_emit_3dstate_multisample(batch, params); 1261 1262 blorp_emit(batch, GENX(3DSTATE_SAMPLE_MASK), mask) { 1263 mask.SampleMask = (1 << params->num_samples) - 1; 1264 } 1265 1266 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, 1267 * 3DSTATE_VS, Dword 5.0 "VS Function Enable": 1268 * 1269 * [DevSNB] A pipeline flush must be programmed prior to a 1270 * 3DSTATE_VS command that causes the VS Function Enable to 1271 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL 1272 * command with CS stall bit set and a post sync operation. 1273 * 1274 * We've already done one at the start of the BLORP operation. 1275 */ 1276 blorp_emit_vs_config(batch, params); 1277#if GEN_GEN >= 7 1278 blorp_emit(batch, GENX(3DSTATE_HS), hs); 1279 blorp_emit(batch, GENX(3DSTATE_TE), te); 1280 blorp_emit(batch, GENX(3DSTATE_DS), DS); 1281 blorp_emit(batch, GENX(3DSTATE_STREAMOUT), so); 1282#endif 1283 blorp_emit(batch, GENX(3DSTATE_GS), gs); 1284 1285 blorp_emit(batch, GENX(3DSTATE_CLIP), clip) { 1286 clip.PerspectiveDivideDisable = true; 1287 } 1288 1289 blorp_emit_sf_config(batch, params); 1290 blorp_emit_ps_config(batch, params); 1291 1292 blorp_emit_cc_viewport(batch); 1293} 1294 1295/******** This is the end of the pipeline setup code ********/ 1296 1297#endif /* GEN_GEN >= 6 */ 1298 1299#if GEN_GEN >= 7 1300static void 1301blorp_emit_memcpy(struct blorp_batch *batch, 1302 struct blorp_address dst, 1303 struct blorp_address src, 1304 uint32_t size) 1305{ 1306 assert(size % 4 == 0); 1307 1308 for (unsigned dw = 0; dw < size; dw += 4) { 1309#if GEN_GEN >= 8 1310 blorp_emit(batch, GENX(MI_COPY_MEM_MEM), cp) { 1311 cp.DestinationMemoryAddress = dst; 1312 cp.SourceMemoryAddress = src; 1313 } 1314#else 1315 /* IVB does not have a general purpose register for command streamer 1316 * commands. Therefore, we use an alternate temporary register. 1317 */ 1318#define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */ 1319 blorp_emit(batch, GENX(MI_LOAD_REGISTER_MEM), load) { 1320 load.RegisterAddress = BLORP_TEMP_REG; 1321 load.MemoryAddress = src; 1322 } 1323 blorp_emit(batch, GENX(MI_STORE_REGISTER_MEM), store) { 1324 store.RegisterAddress = BLORP_TEMP_REG; 1325 store.MemoryAddress = dst; 1326 } 1327#undef BLORP_TEMP_REG 1328#endif 1329 dst.offset += 4; 1330 src.offset += 4; 1331 } 1332} 1333#endif 1334 1335static void 1336blorp_emit_surface_state(struct blorp_batch *batch, 1337 const struct brw_blorp_surface_info *surface, 1338 enum isl_aux_op aux_op, 1339 void *state, uint32_t state_offset, 1340 const bool color_write_disables[4], 1341 bool is_render_target) 1342{ 1343 const struct isl_device *isl_dev = batch->blorp->isl_dev; 1344 struct isl_surf surf = surface->surf; 1345 1346 if (surf.dim == ISL_SURF_DIM_1D && 1347 surf.dim_layout == ISL_DIM_LAYOUT_GEN4_2D) { 1348 assert(surf.logical_level0_px.height == 1); 1349 surf.dim = ISL_SURF_DIM_2D; 1350 } 1351 1352 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */ 1353 enum isl_aux_usage aux_usage = surface->aux_usage; 1354 if (aux_usage == ISL_AUX_USAGE_HIZ) 1355 aux_usage = ISL_AUX_USAGE_NONE; 1356 1357 isl_channel_mask_t write_disable_mask = 0; 1358 if (is_render_target && GEN_GEN <= 5) { 1359 if (color_write_disables[0]) 1360 write_disable_mask |= ISL_CHANNEL_RED_BIT; 1361 if (color_write_disables[1]) 1362 write_disable_mask |= ISL_CHANNEL_GREEN_BIT; 1363 if (color_write_disables[2]) 1364 write_disable_mask |= ISL_CHANNEL_BLUE_BIT; 1365 if (color_write_disables[3]) 1366 write_disable_mask |= ISL_CHANNEL_ALPHA_BIT; 1367 } 1368 1369 const bool use_clear_address = 1370 GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL); 1371 1372 isl_surf_fill_state(batch->blorp->isl_dev, state, 1373 .surf = &surf, .view = &surface->view, 1374 .aux_surf = &surface->aux_surf, .aux_usage = aux_usage, 1375 .address = 1376 blorp_get_surface_address(batch, surface->addr), 1377 .aux_address = aux_usage == ISL_AUX_USAGE_NONE ? 0 : 1378 blorp_get_surface_address(batch, surface->aux_addr), 1379 .clear_address = !use_clear_address ? 0 : 1380 blorp_get_surface_address(batch, 1381 surface->clear_color_addr), 1382 .mocs = surface->addr.mocs, 1383 .clear_color = surface->clear_color, 1384 .use_clear_address = use_clear_address, 1385 .write_disables = write_disable_mask); 1386 1387 blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset, 1388 surface->addr, 0); 1389 1390 if (aux_usage != ISL_AUX_USAGE_NONE) { 1391 /* On gen7 and prior, the bottom 12 bits of the MCS base address are 1392 * used to store other information. This should be ok, however, because 1393 * surface buffer addresses are always 4K page alinged. 1394 */ 1395 assert((surface->aux_addr.offset & 0xfff) == 0); 1396 uint32_t *aux_addr = state + isl_dev->ss.aux_addr_offset; 1397 blorp_surface_reloc(batch, state_offset + isl_dev->ss.aux_addr_offset, 1398 surface->aux_addr, *aux_addr); 1399 } 1400 1401 if (aux_usage != ISL_AUX_USAGE_NONE && surface->clear_color_addr.buffer) { 1402#if GEN_GEN >= 10 1403 assert((surface->clear_color_addr.offset & 0x3f) == 0); 1404 uint32_t *clear_addr = state + isl_dev->ss.clear_color_state_offset; 1405 blorp_surface_reloc(batch, state_offset + 1406 isl_dev->ss.clear_color_state_offset, 1407 surface->clear_color_addr, *clear_addr); 1408#elif GEN_GEN >= 7 1409 /* Fast clears just whack the AUX surface and don't actually use the 1410 * clear color for anything. We can avoid the MI memcpy on that case. 1411 */ 1412 if (aux_op != ISL_AUX_OP_FAST_CLEAR) { 1413 struct blorp_address dst_addr = blorp_get_surface_base_address(batch); 1414 dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset; 1415 blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr, 1416 isl_dev->ss.clear_value_size); 1417 } 1418#else 1419 unreachable("Fast clears are only supported on gen7+"); 1420#endif 1421 } 1422 1423 blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4); 1424} 1425 1426static void 1427blorp_emit_null_surface_state(struct blorp_batch *batch, 1428 const struct brw_blorp_surface_info *surface, 1429 uint32_t *state) 1430{ 1431 struct GENX(RENDER_SURFACE_STATE) ss = { 1432 .SurfaceType = SURFTYPE_NULL, 1433 .SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM, 1434 .Width = surface->surf.logical_level0_px.width - 1, 1435 .Height = surface->surf.logical_level0_px.height - 1, 1436 .MIPCountLOD = surface->view.base_level, 1437 .MinimumArrayElement = surface->view.base_array_layer, 1438 .Depth = surface->view.array_len - 1, 1439 .RenderTargetViewExtent = surface->view.array_len - 1, 1440#if GEN_GEN >= 6 1441 .NumberofMultisamples = ffs(surface->surf.samples) - 1, 1442#endif 1443 1444#if GEN_GEN >= 7 1445 .SurfaceArray = surface->surf.dim != ISL_SURF_DIM_3D, 1446#endif 1447 1448#if GEN_GEN >= 8 1449 .TileMode = YMAJOR, 1450#else 1451 .TiledSurface = true, 1452#endif 1453 }; 1454 1455 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &ss); 1456 1457 blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4); 1458} 1459 1460static void 1461blorp_emit_surface_states(struct blorp_batch *batch, 1462 const struct blorp_params *params) 1463{ 1464 const struct isl_device *isl_dev = batch->blorp->isl_dev; 1465 uint32_t bind_offset = 0, surface_offsets[2]; 1466 void *surface_maps[2]; 1467 1468 MAYBE_UNUSED bool has_indirect_clear_color = false; 1469 if (params->use_pre_baked_binding_table) { 1470 bind_offset = params->pre_baked_binding_table_offset; 1471 } else { 1472 unsigned num_surfaces = 1 + params->src.enabled; 1473 blorp_alloc_binding_table(batch, num_surfaces, 1474 isl_dev->ss.size, isl_dev->ss.align, 1475 &bind_offset, surface_offsets, surface_maps); 1476 1477 if (params->dst.enabled) { 1478 blorp_emit_surface_state(batch, ¶ms->dst, 1479 params->fast_clear_op, 1480 surface_maps[BLORP_RENDERBUFFER_BT_INDEX], 1481 surface_offsets[BLORP_RENDERBUFFER_BT_INDEX], 1482 params->color_write_disable, true); 1483 if (params->dst.clear_color_addr.buffer != NULL) 1484 has_indirect_clear_color = true; 1485 } else { 1486 assert(params->depth.enabled || params->stencil.enabled); 1487 const struct brw_blorp_surface_info *surface = 1488 params->depth.enabled ? ¶ms->depth : ¶ms->stencil; 1489 blorp_emit_null_surface_state(batch, surface, 1490 surface_maps[BLORP_RENDERBUFFER_BT_INDEX]); 1491 } 1492 1493 if (params->src.enabled) { 1494 blorp_emit_surface_state(batch, ¶ms->src, 1495 params->fast_clear_op, 1496 surface_maps[BLORP_TEXTURE_BT_INDEX], 1497 surface_offsets[BLORP_TEXTURE_BT_INDEX], 1498 NULL, false); 1499 if (params->src.clear_color_addr.buffer != NULL) 1500 has_indirect_clear_color = true; 1501 } 1502 } 1503 1504#if GEN_GEN >= 7 1505 if (has_indirect_clear_color) { 1506 /* Updating a surface state object may require that the state cache be 1507 * invalidated. From the SKL PRM, Shared Functions -> State -> State 1508 * Caching: 1509 * 1510 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by 1511 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is 1512 * modified [...], the L1 state cache must be invalidated to ensure 1513 * the new surface or sampler state is fetched from system memory. 1514 */ 1515 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { 1516 pipe.StateCacheInvalidationEnable = true; 1517 } 1518 } 1519#endif 1520 1521#if GEN_GEN >= 7 1522 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), bt); 1523 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS), bt); 1524 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS), bt); 1525 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS), bt); 1526 1527 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS), bt) { 1528 bt.PointertoPSBindingTable = bind_offset; 1529 } 1530#elif GEN_GEN >= 6 1531 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS), bt) { 1532 bt.PSBindingTableChange = true; 1533 bt.PointertoPSBindingTable = bind_offset; 1534 } 1535#else 1536 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS), bt) { 1537 bt.PointertoPSBindingTable = bind_offset; 1538 } 1539#endif 1540} 1541 1542static void 1543blorp_emit_depth_stencil_config(struct blorp_batch *batch, 1544 const struct blorp_params *params) 1545{ 1546 const struct isl_device *isl_dev = batch->blorp->isl_dev; 1547 1548 uint32_t *dw = blorp_emit_dwords(batch, isl_dev->ds.size / 4); 1549 if (dw == NULL) 1550 return; 1551 1552 struct isl_depth_stencil_hiz_emit_info info = { }; 1553 1554 if (params->depth.enabled) { 1555 info.view = ¶ms->depth.view; 1556 info.mocs = params->depth.addr.mocs; 1557 } else if (params->stencil.enabled) { 1558 info.view = ¶ms->stencil.view; 1559 info.mocs = params->stencil.addr.mocs; 1560 } 1561 1562 if (params->depth.enabled) { 1563 info.depth_surf = ¶ms->depth.surf; 1564 1565 info.depth_address = 1566 blorp_emit_reloc(batch, dw + isl_dev->ds.depth_offset / 4, 1567 params->depth.addr, 0); 1568 1569 info.hiz_usage = params->depth.aux_usage; 1570 if (info.hiz_usage == ISL_AUX_USAGE_HIZ) { 1571 info.hiz_surf = ¶ms->depth.aux_surf; 1572 1573 struct blorp_address hiz_address = params->depth.aux_addr; 1574#if GEN_GEN == 6 1575 /* Sandy bridge hardware does not technically support mipmapped HiZ. 1576 * However, we have a special layout that allows us to make it work 1577 * anyway by manually offsetting to the specified miplevel. 1578 */ 1579 assert(info.hiz_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); 1580 uint32_t offset_B; 1581 isl_surf_get_image_offset_B_tile_sa(info.hiz_surf, 1582 info.view->base_level, 0, 0, 1583 &offset_B, NULL, NULL); 1584 hiz_address.offset += offset_B; 1585#endif 1586 1587 info.hiz_address = 1588 blorp_emit_reloc(batch, dw + isl_dev->ds.hiz_offset / 4, 1589 hiz_address, 0); 1590 1591 info.depth_clear_value = params->depth.clear_color.f32[0]; 1592 } 1593 } 1594 1595 if (params->stencil.enabled) { 1596 info.stencil_surf = ¶ms->stencil.surf; 1597 1598 struct blorp_address stencil_address = params->stencil.addr; 1599#if GEN_GEN == 6 1600 /* Sandy bridge hardware does not technically support mipmapped stencil. 1601 * However, we have a special layout that allows us to make it work 1602 * anyway by manually offsetting to the specified miplevel. 1603 */ 1604 assert(info.stencil_surf->dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ); 1605 uint32_t offset_B; 1606 isl_surf_get_image_offset_B_tile_sa(info.stencil_surf, 1607 info.view->base_level, 0, 0, 1608 &offset_B, NULL, NULL); 1609 stencil_address.offset += offset_B; 1610#endif 1611 1612 info.stencil_address = 1613 blorp_emit_reloc(batch, dw + isl_dev->ds.stencil_offset / 4, 1614 stencil_address, 0); 1615 } 1616 1617 isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info); 1618} 1619 1620#if GEN_GEN >= 8 1621/* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The 1622 * depth/stencil buffer extents are ignored to handle APIs which perform 1623 * clearing operations without such information. 1624 * */ 1625static void 1626blorp_emit_gen8_hiz_op(struct blorp_batch *batch, 1627 const struct blorp_params *params) 1628{ 1629 /* We should be performing an operation on a depth or stencil buffer. 1630 */ 1631 assert(params->depth.enabled || params->stencil.enabled); 1632 1633 /* The stencil buffer should only be enabled if a fast clear operation is 1634 * requested. 1635 */ 1636 if (params->stencil.enabled) 1637 assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR); 1638 1639 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP: 1640 * 1641 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change 1642 * the Number of Multisamples. This packet must not be used to change 1643 * Number of Multisamples in a rendering sequence. 1644 * 1645 * Since HIZ may be the first thing in a batch buffer, play safe and always 1646 * emit 3DSTATE_MULTISAMPLE. 1647 */ 1648 blorp_emit_3dstate_multisample(batch, params); 1649 1650 /* From the BDW PRM Volume 7, Depth Buffer Clear: 1651 * 1652 * The clear value must be between the min and max depth values 1653 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is 1654 * D32_FLOAT, then +/-DENORM values are also allowed. 1655 * 1656 * Set the bounds to match our hardware limits, [0.0, 1.0]. 1657 */ 1658 if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) { 1659 assert(params->depth.clear_color.f32[0] >= 0.0f); 1660 assert(params->depth.clear_color.f32[0] <= 1.0f); 1661 blorp_emit_cc_viewport(batch); 1662 } 1663 1664 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the 1665 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch 1666 * even when WM_HZ_OP is active. However, WM thread dispatch is normally 1667 * disabled for HiZ ops and it appears that force-enabling it can lead to 1668 * GPU hangs on at least Skylake. Since we don't know the current state of 1669 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP. 1670 */ 1671 blorp_emit(batch, GENX(3DSTATE_WM), wm); 1672 1673 /* If we can't alter the depth stencil config and multiple layers are 1674 * involved, the HiZ op will fail. This is because the op requires that a 1675 * new config is emitted for each additional layer. 1676 */ 1677 if (batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL) { 1678 assert(params->num_layers <= 1); 1679 } else { 1680 blorp_emit_depth_stencil_config(batch, params); 1681 } 1682 1683 blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp) { 1684 switch (params->hiz_op) { 1685 case ISL_AUX_OP_FAST_CLEAR: 1686 hzp.StencilBufferClearEnable = params->stencil.enabled; 1687 hzp.DepthBufferClearEnable = params->depth.enabled; 1688 hzp.StencilClearValue = params->stencil_ref; 1689 hzp.FullSurfaceDepthandStencilClear = params->full_surface_hiz_op; 1690 break; 1691 case ISL_AUX_OP_FULL_RESOLVE: 1692 assert(params->full_surface_hiz_op); 1693 hzp.DepthBufferResolveEnable = true; 1694 break; 1695 case ISL_AUX_OP_AMBIGUATE: 1696 assert(params->full_surface_hiz_op); 1697 hzp.HierarchicalDepthBufferResolveEnable = true; 1698 break; 1699 case ISL_AUX_OP_PARTIAL_RESOLVE: 1700 case ISL_AUX_OP_NONE: 1701 unreachable("Invalid HIZ op"); 1702 } 1703 1704 hzp.NumberofMultisamples = ffs(params->num_samples) - 1; 1705 hzp.SampleMask = 0xFFFF; 1706 1707 /* Due to a hardware issue, this bit MBZ */ 1708 assert(hzp.ScissorRectangleEnable == false); 1709 1710 /* Contrary to the HW docs both fields are inclusive */ 1711 hzp.ClearRectangleXMin = params->x0; 1712 hzp.ClearRectangleYMin = params->y0; 1713 1714 /* Contrary to the HW docs both fields are exclusive */ 1715 hzp.ClearRectangleXMax = params->x1; 1716 hzp.ClearRectangleYMax = params->y1; 1717 } 1718 1719 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set 1720 * to “Write Immediate Data” enabled. 1721 */ 1722 blorp_emit(batch, GENX(PIPE_CONTROL), pc) { 1723 pc.PostSyncOperation = WriteImmediateData; 1724 pc.Address = blorp_get_workaround_page(batch); 1725 } 1726 1727 blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp); 1728} 1729#endif 1730 1731static void 1732blorp_update_clear_color(struct blorp_batch *batch, 1733 const struct brw_blorp_surface_info *info, 1734 enum isl_aux_op op) 1735{ 1736 if (info->clear_color_addr.buffer && op == ISL_AUX_OP_FAST_CLEAR) { 1737#if GEN_GEN == 11 1738 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { 1739 pipe.CommandStreamerStallEnable = true; 1740 } 1741 1742 /* 2 QWORDS */ 1743 const unsigned inlinedata_dw = 2 * 2; 1744 const unsigned num_dwords = GENX(MI_ATOMIC_length) + inlinedata_dw; 1745 1746 struct blorp_address clear_addr = info->clear_color_addr; 1747 uint32_t *dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, 1748 .DataSize = MI_ATOMIC_QWORD, 1749 .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, 1750 .InlineData = true, 1751 .MemoryAddress = clear_addr); 1752 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ 1753 dw[2] = info->clear_color.u32[0]; 1754 dw[4] = info->clear_color.u32[1]; 1755 1756 clear_addr.offset += 8; 1757 dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, 1758 .DataSize = MI_ATOMIC_QWORD, 1759 .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, 1760 .CSSTALL = true, 1761 .ReturnDataControl = true, 1762 .InlineData = true, 1763 .MemoryAddress = clear_addr); 1764 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ 1765 dw[2] = info->clear_color.u32[2]; 1766 dw[4] = info->clear_color.u32[3]; 1767 1768 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { 1769 pipe.StateCacheInvalidationEnable = true; 1770 pipe.TextureCacheInvalidationEnable = true; 1771 } 1772#elif GEN_GEN >= 9 1773 for (int i = 0; i < 4; i++) { 1774 blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { 1775 sdi.Address = info->clear_color_addr; 1776 sdi.Address.offset += i * 4; 1777 sdi.ImmediateData = info->clear_color.u32[i]; 1778 } 1779 } 1780#elif GEN_GEN >= 7 1781 blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { 1782 sdi.Address = info->clear_color_addr; 1783 sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 | 1784 ISL_CHANNEL_SELECT_GREEN << 22 | 1785 ISL_CHANNEL_SELECT_BLUE << 19 | 1786 ISL_CHANNEL_SELECT_ALPHA << 16; 1787 if (isl_format_has_int_channel(info->view.format)) { 1788 for (unsigned i = 0; i < 4; i++) { 1789 assert(info->clear_color.u32[i] == 0 || 1790 info->clear_color.u32[i] == 1); 1791 } 1792 sdi.ImmediateData |= (info->clear_color.u32[0] != 0) << 31; 1793 sdi.ImmediateData |= (info->clear_color.u32[1] != 0) << 30; 1794 sdi.ImmediateData |= (info->clear_color.u32[2] != 0) << 29; 1795 sdi.ImmediateData |= (info->clear_color.u32[3] != 0) << 28; 1796 } else { 1797 for (unsigned i = 0; i < 4; i++) { 1798 assert(info->clear_color.f32[i] == 0.0f || 1799 info->clear_color.f32[i] == 1.0f); 1800 } 1801 sdi.ImmediateData |= (info->clear_color.f32[0] != 0.0f) << 31; 1802 sdi.ImmediateData |= (info->clear_color.f32[1] != 0.0f) << 30; 1803 sdi.ImmediateData |= (info->clear_color.f32[2] != 0.0f) << 29; 1804 sdi.ImmediateData |= (info->clear_color.f32[3] != 0.0f) << 28; 1805 } 1806 } 1807#endif 1808 } 1809} 1810 1811/** 1812 * \brief Execute a blit or render pass operation. 1813 * 1814 * To execute the operation, this function manually constructs and emits a 1815 * batch to draw a rectangle primitive. The batchbuffer is flushed before 1816 * constructing and after emitting the batch. 1817 * 1818 * This function alters no GL state. 1819 */ 1820static void 1821blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) 1822{ 1823 if (!(batch->flags & BLORP_BATCH_NO_UPDATE_CLEAR_COLOR)) { 1824 blorp_update_clear_color(batch, ¶ms->dst, params->fast_clear_op); 1825 blorp_update_clear_color(batch, ¶ms->depth, params->hiz_op); 1826 } 1827 1828#if GEN_GEN >= 8 1829 if (params->hiz_op != ISL_AUX_OP_NONE) { 1830 blorp_emit_gen8_hiz_op(batch, params); 1831 return; 1832 } 1833#endif 1834 1835 blorp_emit_vertex_buffers(batch, params); 1836 blorp_emit_vertex_elements(batch, params); 1837 1838 blorp_emit_pipeline(batch, params); 1839 1840 blorp_emit_surface_states(batch, params); 1841 1842 if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)) 1843 blorp_emit_depth_stencil_config(batch, params); 1844 1845 blorp_emit(batch, GENX(3DPRIMITIVE), prim) { 1846 prim.VertexAccessType = SEQUENTIAL; 1847 prim.PrimitiveTopologyType = _3DPRIM_RECTLIST; 1848#if GEN_GEN >= 7 1849 prim.PredicateEnable = batch->flags & BLORP_BATCH_PREDICATE_ENABLE; 1850#endif 1851 prim.VertexCountPerInstance = 3; 1852 prim.InstanceCount = params->num_layers; 1853 } 1854} 1855 1856#endif /* BLORP_GENX_EXEC_H */ 1857