1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28#ifndef BRW_FS_H 29#define BRW_FS_H 30 31#include "brw_shader.h" 32#include "brw_ir_fs.h" 33#include "brw_fs_builder.h" 34#include "compiler/nir/nir.h" 35 36struct bblock_t; 37namespace { 38 struct acp_entry; 39} 40 41namespace brw { 42 class fs_live_variables; 43} 44 45struct brw_gs_compile; 46 47static inline fs_reg 48offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta) 49{ 50 return offset(reg, bld.dispatch_width(), delta); 51} 52 53#define UBO_START ((1 << 16) - 4) 54 55/** 56 * The fragment shader front-end. 57 * 58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. 59 */ 60class fs_visitor : public backend_shader 61{ 62public: 63 fs_visitor(const struct brw_compiler *compiler, void *log_data, 64 void *mem_ctx, 65 const void *key, 66 struct brw_stage_prog_data *prog_data, 67 struct gl_program *prog, 68 const nir_shader *shader, 69 unsigned dispatch_width, 70 int shader_time_index, 71 const struct brw_vue_map *input_vue_map = NULL); 72 fs_visitor(const struct brw_compiler *compiler, void *log_data, 73 void *mem_ctx, 74 struct brw_gs_compile *gs_compile, 75 struct brw_gs_prog_data *prog_data, 76 const nir_shader *shader, 77 int shader_time_index); 78 void init(); 79 ~fs_visitor(); 80 81 fs_reg vgrf(const glsl_type *const type); 82 void import_uniforms(fs_visitor *v); 83 void setup_uniform_clipplane_values(); 84 void compute_clip_distance(); 85 86 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld, 87 const fs_reg &dst, 88 const fs_reg &surf_index, 89 const fs_reg &varying_offset, 90 uint32_t const_offset); 91 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf); 92 93 bool run_fs(bool allow_spilling, bool do_rep_send); 94 bool run_vs(); 95 bool run_tcs_single_patch(); 96 bool run_tes(); 97 bool run_gs(); 98 bool run_cs(unsigned min_dispatch_width); 99 void optimize(); 100 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling); 101 void setup_fs_payload_gen4(); 102 void setup_fs_payload_gen6(); 103 void setup_vs_payload(); 104 void setup_gs_payload(); 105 void setup_cs_payload(); 106 bool fixup_sends_duplicate_payload(); 107 void fixup_3src_null_dest(); 108 void assign_curb_setup(); 109 void calculate_urb_setup(); 110 void assign_urb_setup(); 111 void convert_attr_sources_to_hw_regs(fs_inst *inst); 112 void assign_vs_urb_setup(); 113 void assign_tcs_single_patch_urb_setup(); 114 void assign_tes_urb_setup(); 115 void assign_gs_urb_setup(); 116 bool assign_regs(bool allow_spilling, bool spill_all); 117 void assign_regs_trivial(); 118 void calculate_payload_ranges(int payload_node_count, 119 int *payload_last_use_ip); 120 void setup_payload_interference(struct ra_graph *g, int payload_reg_count, 121 int first_payload_node); 122 int choose_spill_reg(struct ra_graph *g); 123 void spill_reg(unsigned spill_reg); 124 void split_virtual_grfs(); 125 bool compact_virtual_grfs(); 126 void assign_constant_locations(); 127 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index, 128 unsigned *out_pull_index); 129 void lower_constant_loads(); 130 void invalidate_live_intervals(); 131 void calculate_live_intervals(); 132 void calculate_register_pressure(); 133 void validate(); 134 bool opt_algebraic(); 135 bool opt_redundant_discard_jumps(); 136 bool opt_cse(); 137 bool opt_cse_local(bblock_t *block); 138 bool opt_copy_propagation(); 139 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry); 140 bool try_constant_propagate(fs_inst *inst, acp_entry *entry); 141 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block, 142 exec_list *acp); 143 bool opt_drop_redundant_mov_to_flags(); 144 bool opt_register_renaming(); 145 bool opt_bank_conflicts(); 146 unsigned bank_conflict_cycles(const fs_inst *inst) const; 147 bool register_coalesce(); 148 bool compute_to_mrf(); 149 bool eliminate_find_live_channel(); 150 bool dead_code_eliminate(); 151 bool remove_duplicate_mrf_writes(); 152 bool remove_extra_rounding_modes(); 153 154 bool opt_sampler_eot(); 155 bool virtual_grf_interferes(int a, int b); 156 void schedule_instructions(instruction_scheduler_mode mode); 157 void insert_gen4_send_dependency_workarounds(); 158 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block, 159 fs_inst *inst); 160 void insert_gen4_post_send_dependency_workarounds(bblock_t *block, 161 fs_inst *inst); 162 void vfail(const char *msg, va_list args); 163 void fail(const char *msg, ...); 164 void limit_dispatch_width(unsigned n, const char *msg); 165 void lower_uniform_pull_constant_loads(); 166 bool lower_load_payload(); 167 bool lower_pack(); 168 bool lower_regioning(); 169 bool lower_logical_sends(); 170 bool lower_linterp(); 171 bool lower_integer_multiplication(); 172 bool lower_minmax(); 173 bool lower_simd_width(); 174 bool opt_combine_constants(); 175 176 void emit_dummy_fs(); 177 void emit_repclear_shader(); 178 void emit_fragcoord_interpolation(fs_reg wpos); 179 fs_reg *emit_frontfacing_interpolation(); 180 fs_reg *emit_samplepos_setup(); 181 fs_reg *emit_sampleid_setup(); 182 fs_reg *emit_samplemaskin_setup(); 183 void emit_interpolation_setup_gen4(); 184 void emit_interpolation_setup_gen6(); 185 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); 186 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components, 187 const fs_reg &texture, 188 const fs_reg &texture_handle); 189 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst); 190 fs_reg resolve_source_modifiers(const fs_reg &src); 191 void emit_discard_jump(); 192 void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr, 193 fs_reg result, fs_reg *op, unsigned fsign_src); 194 bool opt_peephole_sel(); 195 bool opt_peephole_csel(); 196 bool opt_peephole_predicated_break(); 197 bool opt_saturate_propagation(); 198 bool opt_cmod_propagation(); 199 bool opt_zero_samples(); 200 201 void emit_nir_code(); 202 void nir_setup_outputs(); 203 void nir_setup_uniforms(); 204 void nir_emit_system_values(); 205 void nir_emit_impl(nir_function_impl *impl); 206 void nir_emit_cf_list(exec_list *list); 207 void nir_emit_if(nir_if *if_stmt); 208 void nir_emit_loop(nir_loop *loop); 209 void nir_emit_block(nir_block *block); 210 void nir_emit_instr(nir_instr *instr); 211 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr); 212 bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result, 213 nir_alu_instr *instr); 214 void nir_emit_load_const(const brw::fs_builder &bld, 215 nir_load_const_instr *instr); 216 void nir_emit_vs_intrinsic(const brw::fs_builder &bld, 217 nir_intrinsic_instr *instr); 218 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld, 219 nir_intrinsic_instr *instr); 220 void nir_emit_gs_intrinsic(const brw::fs_builder &bld, 221 nir_intrinsic_instr *instr); 222 void nir_emit_fs_intrinsic(const brw::fs_builder &bld, 223 nir_intrinsic_instr *instr); 224 void nir_emit_cs_intrinsic(const brw::fs_builder &bld, 225 nir_intrinsic_instr *instr); 226 fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld, 227 nir_intrinsic_instr *instr); 228 fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld, 229 nir_intrinsic_instr *instr); 230 void nir_emit_intrinsic(const brw::fs_builder &bld, 231 nir_intrinsic_instr *instr); 232 void nir_emit_tes_intrinsic(const brw::fs_builder &bld, 233 nir_intrinsic_instr *instr); 234 void nir_emit_ssbo_atomic(const brw::fs_builder &bld, 235 int op, nir_intrinsic_instr *instr); 236 void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld, 237 int op, nir_intrinsic_instr *instr); 238 void nir_emit_shared_atomic(const brw::fs_builder &bld, 239 int op, nir_intrinsic_instr *instr); 240 void nir_emit_shared_atomic_float(const brw::fs_builder &bld, 241 int op, nir_intrinsic_instr *instr); 242 void nir_emit_global_atomic(const brw::fs_builder &bld, 243 int op, nir_intrinsic_instr *instr); 244 void nir_emit_global_atomic_float(const brw::fs_builder &bld, 245 int op, nir_intrinsic_instr *instr); 246 void nir_emit_texture(const brw::fs_builder &bld, 247 nir_tex_instr *instr); 248 void nir_emit_jump(const brw::fs_builder &bld, 249 nir_jump_instr *instr); 250 fs_reg get_nir_src(const nir_src &src); 251 fs_reg get_nir_src_imm(const nir_src &src); 252 fs_reg get_nir_dest(const nir_dest &dest); 253 fs_reg get_indirect_offset(nir_intrinsic_instr *instr); 254 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst, 255 unsigned wr_mask); 256 257 bool optimize_extract_to_float(nir_alu_instr *instr, 258 const fs_reg &result); 259 bool optimize_frontfacing_ternary(nir_alu_instr *instr, 260 const fs_reg &result); 261 262 void emit_alpha_test(); 263 fs_inst *emit_single_fb_write(const brw::fs_builder &bld, 264 fs_reg color1, fs_reg color2, 265 fs_reg src0_alpha, unsigned components); 266 void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha); 267 void emit_fb_writes(); 268 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld, 269 const fs_reg &dst, unsigned target); 270 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg()); 271 void set_gs_stream_control_data_bits(const fs_reg &vertex_count, 272 unsigned stream_id); 273 void emit_gs_control_data_bits(const fs_reg &vertex_count); 274 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src); 275 void emit_gs_vertex(const nir_src &vertex_count_nir_src, 276 unsigned stream_id); 277 void emit_gs_thread_end(); 278 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src, 279 unsigned base_offset, const nir_src &offset_src, 280 unsigned num_components, unsigned first_component); 281 void emit_cs_terminate(); 282 fs_reg *emit_cs_work_group_id_setup(); 283 284 void emit_barrier(); 285 286 void emit_shader_time_begin(); 287 void emit_shader_time_end(); 288 void SHADER_TIME_ADD(const brw::fs_builder &bld, 289 int shader_time_subindex, 290 fs_reg value); 291 292 fs_reg get_timestamp(const brw::fs_builder &bld); 293 294 fs_reg interp_reg(int location, int channel); 295 296 int implied_mrf_writes(fs_inst *inst) const; 297 298 virtual void dump_instructions(); 299 virtual void dump_instructions(const char *name); 300 void dump_instruction(backend_instruction *inst); 301 void dump_instruction(backend_instruction *inst, FILE *file); 302 303 const void *const key; 304 const struct brw_sampler_prog_key_data *key_tex; 305 306 struct brw_gs_compile *gs_compile; 307 308 struct brw_stage_prog_data *prog_data; 309 struct gl_program *prog; 310 311 const struct brw_vue_map *input_vue_map; 312 313 int *virtual_grf_start; 314 int *virtual_grf_end; 315 brw::fs_live_variables *live_intervals; 316 317 int *regs_live_at_ip; 318 319 /** Number of uniform variable components visited. */ 320 unsigned uniforms; 321 322 /** Byte-offset for the next available spot in the scratch space buffer. */ 323 unsigned last_scratch; 324 325 /** 326 * Array mapping UNIFORM register numbers to the pull parameter index, 327 * or -1 if this uniform register isn't being uploaded as a pull constant. 328 */ 329 int *pull_constant_loc; 330 331 /** 332 * Array mapping UNIFORM register numbers to the push parameter index, 333 * or -1 if this uniform register isn't being uploaded as a push constant. 334 */ 335 int *push_constant_loc; 336 337 fs_reg subgroup_id; 338 fs_reg frag_depth; 339 fs_reg frag_stencil; 340 fs_reg sample_mask; 341 fs_reg outputs[VARYING_SLOT_MAX]; 342 fs_reg dual_src_output; 343 int first_non_payload_grf; 344 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */ 345 unsigned max_grf; 346 347 fs_reg *nir_locals; 348 fs_reg *nir_ssa_values; 349 fs_reg *nir_system_values; 350 351 bool failed; 352 char *fail_msg; 353 354 /** Register numbers for thread payload fields. */ 355 struct thread_payload { 356 uint8_t subspan_coord_reg[2]; 357 uint8_t source_depth_reg[2]; 358 uint8_t source_w_reg[2]; 359 uint8_t aa_dest_stencil_reg[2]; 360 uint8_t dest_depth_reg[2]; 361 uint8_t sample_pos_reg[2]; 362 uint8_t sample_mask_in_reg[2]; 363 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2]; 364 uint8_t local_invocation_id_reg[2]; 365 366 /** The number of thread payload registers the hardware will supply. */ 367 uint8_t num_regs; 368 } payload; 369 370 bool source_depth_to_render_target; 371 bool runtime_check_aads_emit; 372 373 fs_reg pixel_x; 374 fs_reg pixel_y; 375 fs_reg wpos_w; 376 fs_reg pixel_w; 377 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT]; 378 fs_reg shader_start_time; 379 fs_reg userplane[MAX_CLIP_PLANES]; 380 fs_reg final_gs_vertex_count; 381 fs_reg control_data_bits; 382 fs_reg invocation_id; 383 384 unsigned grf_used; 385 bool spilled_any_registers; 386 387 const unsigned dispatch_width; /**< 8, 16 or 32 */ 388 unsigned max_dispatch_width; 389 390 int shader_time_index; 391 392 unsigned promoted_constants; 393 brw::fs_builder bld; 394 395private: 396 fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld, 397 nir_alu_instr *instr, 398 fs_reg *op, 399 bool need_dest); 400 401 void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr, 402 fs_reg *op); 403}; 404 405/** 406 * The fragment shader code generator. 407 * 408 * Translates FS IR to actual i965 assembly code. 409 */ 410class fs_generator 411{ 412public: 413 fs_generator(const struct brw_compiler *compiler, void *log_data, 414 void *mem_ctx, 415 struct brw_stage_prog_data *prog_data, 416 unsigned promoted_constants, 417 bool runtime_check_aads_emit, 418 gl_shader_stage stage); 419 ~fs_generator(); 420 421 void enable_debug(const char *shader_name); 422 int generate_code(const cfg_t *cfg, int dispatch_width); 423 const unsigned *get_assembly(); 424 425private: 426 void fire_fb_write(fs_inst *inst, 427 struct brw_reg payload, 428 struct brw_reg implied_header, 429 GLuint nr); 430 void generate_send(fs_inst *inst, 431 struct brw_reg dst, 432 struct brw_reg desc, 433 struct brw_reg ex_desc, 434 struct brw_reg payload, 435 struct brw_reg payload2); 436 void generate_fb_write(fs_inst *inst, struct brw_reg payload); 437 void generate_fb_read(fs_inst *inst, struct brw_reg dst, 438 struct brw_reg payload); 439 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload); 440 void generate_urb_write(fs_inst *inst, struct brw_reg payload); 441 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); 442 void generate_barrier(fs_inst *inst, struct brw_reg src); 443 bool generate_linterp(fs_inst *inst, struct brw_reg dst, 444 struct brw_reg *src); 445 void generate_tex(fs_inst *inst, struct brw_reg dst, 446 struct brw_reg surface_index, 447 struct brw_reg sampler_index); 448 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst, 449 struct brw_reg src, 450 struct brw_reg surf_index); 451 void generate_ddx(const fs_inst *inst, 452 struct brw_reg dst, struct brw_reg src); 453 void generate_ddy(const fs_inst *inst, 454 struct brw_reg dst, struct brw_reg src); 455 void generate_scratch_write(fs_inst *inst, struct brw_reg src); 456 void generate_scratch_read(fs_inst *inst, struct brw_reg dst); 457 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst); 458 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, 459 struct brw_reg index, 460 struct brw_reg offset); 461 void generate_uniform_pull_constant_load_gen7(fs_inst *inst, 462 struct brw_reg dst, 463 struct brw_reg surf_index, 464 struct brw_reg payload); 465 void generate_varying_pull_constant_load_gen4(fs_inst *inst, 466 struct brw_reg dst, 467 struct brw_reg index); 468 void generate_mov_dispatch_to_flags(fs_inst *inst); 469 470 void generate_pixel_interpolator_query(fs_inst *inst, 471 struct brw_reg dst, 472 struct brw_reg src, 473 struct brw_reg msg_data, 474 unsigned msg_type); 475 476 void generate_set_sample_id(fs_inst *inst, 477 struct brw_reg dst, 478 struct brw_reg src0, 479 struct brw_reg src1); 480 481 void generate_discard_jump(fs_inst *inst); 482 483 void generate_pack_half_2x16_split(fs_inst *inst, 484 struct brw_reg dst, 485 struct brw_reg x, 486 struct brw_reg y); 487 488 void generate_shader_time_add(fs_inst *inst, 489 struct brw_reg payload, 490 struct brw_reg offset, 491 struct brw_reg value); 492 493 void generate_mov_indirect(fs_inst *inst, 494 struct brw_reg dst, 495 struct brw_reg reg, 496 struct brw_reg indirect_byte_offset); 497 498 void generate_shuffle(fs_inst *inst, 499 struct brw_reg dst, 500 struct brw_reg src, 501 struct brw_reg idx); 502 503 void generate_quad_swizzle(const fs_inst *inst, 504 struct brw_reg dst, struct brw_reg src, 505 unsigned swiz); 506 507 bool patch_discard_jumps_to_fb_writes(); 508 509 const struct brw_compiler *compiler; 510 void *log_data; /* Passed to compiler->*_log functions */ 511 512 const struct gen_device_info *devinfo; 513 514 struct brw_codegen *p; 515 struct brw_stage_prog_data * const prog_data; 516 517 unsigned dispatch_width; /**< 8, 16 or 32 */ 518 519 exec_list discard_halt_patches; 520 unsigned promoted_constants; 521 bool runtime_check_aads_emit; 522 bool debug_flag; 523 const char *shader_name; 524 gl_shader_stage stage; 525 void *mem_ctx; 526}; 527 528namespace brw { 529 inline fs_reg 530 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2], 531 brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1) 532 { 533 if (!regs[0]) 534 return fs_reg(); 535 536 if (bld.dispatch_width() > 16) { 537 const fs_reg tmp = bld.vgrf(type, n); 538 const brw::fs_builder hbld = bld.exec_all().group(16, 0); 539 const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); 540 fs_reg *const components = new fs_reg[n * m]; 541 542 for (unsigned c = 0; c < n; c++) { 543 for (unsigned g = 0; g < m; g++) { 544 components[c * m + g] = 545 offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c); 546 } 547 } 548 549 hbld.LOAD_PAYLOAD(tmp, components, n * m, 0); 550 551 delete[] components; 552 return tmp; 553 554 } else { 555 return fs_reg(retype(brw_vec8_grf(regs[0], 0), type)); 556 } 557 } 558 559 bool 560 lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i); 561} 562 563void shuffle_from_32bit_read(const brw::fs_builder &bld, 564 const fs_reg &dst, 565 const fs_reg &src, 566 uint32_t first_component, 567 uint32_t components); 568 569fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld, 570 const fs_reg &src, 571 uint32_t first_component, 572 uint32_t components); 573 574fs_reg setup_imm_df(const brw::fs_builder &bld, 575 double v); 576 577fs_reg setup_imm_b(const brw::fs_builder &bld, 578 int8_t v); 579 580fs_reg setup_imm_ub(const brw::fs_builder &bld, 581 uint8_t v); 582 583enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode, 584 nir_intrinsic_op op); 585 586#endif /* BRW_FS_H */ 587