1/*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "brw_cfg.h"
25#include "brw_eu.h"
26#include "brw_fs.h"
27#include "brw_nir.h"
28#include "brw_vec4_tes.h"
29#include "dev/gen_debug.h"
30#include "main/uniforms.h"
31#include "util/macros.h"
32
33enum brw_reg_type
34brw_type_for_base_type(const struct glsl_type *type)
35{
36   switch (type->base_type) {
37   case GLSL_TYPE_FLOAT16:
38      return BRW_REGISTER_TYPE_HF;
39   case GLSL_TYPE_FLOAT:
40      return BRW_REGISTER_TYPE_F;
41   case GLSL_TYPE_INT:
42   case GLSL_TYPE_BOOL:
43   case GLSL_TYPE_SUBROUTINE:
44      return BRW_REGISTER_TYPE_D;
45   case GLSL_TYPE_INT16:
46      return BRW_REGISTER_TYPE_W;
47   case GLSL_TYPE_INT8:
48      return BRW_REGISTER_TYPE_B;
49   case GLSL_TYPE_UINT:
50      return BRW_REGISTER_TYPE_UD;
51   case GLSL_TYPE_UINT16:
52      return BRW_REGISTER_TYPE_UW;
53   case GLSL_TYPE_UINT8:
54      return BRW_REGISTER_TYPE_UB;
55   case GLSL_TYPE_ARRAY:
56      return brw_type_for_base_type(type->fields.array);
57   case GLSL_TYPE_STRUCT:
58   case GLSL_TYPE_INTERFACE:
59   case GLSL_TYPE_SAMPLER:
60   case GLSL_TYPE_ATOMIC_UINT:
61      /* These should be overridden with the type of the member when
62       * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
63       * way to trip up if we don't.
64       */
65      return BRW_REGISTER_TYPE_UD;
66   case GLSL_TYPE_IMAGE:
67      return BRW_REGISTER_TYPE_UD;
68   case GLSL_TYPE_DOUBLE:
69      return BRW_REGISTER_TYPE_DF;
70   case GLSL_TYPE_UINT64:
71      return BRW_REGISTER_TYPE_UQ;
72   case GLSL_TYPE_INT64:
73      return BRW_REGISTER_TYPE_Q;
74   case GLSL_TYPE_VOID:
75   case GLSL_TYPE_ERROR:
76   case GLSL_TYPE_FUNCTION:
77      unreachable("not reached");
78   }
79
80   return BRW_REGISTER_TYPE_F;
81}
82
83enum brw_conditional_mod
84brw_conditional_for_comparison(unsigned int op)
85{
86   switch (op) {
87   case ir_binop_less:
88      return BRW_CONDITIONAL_L;
89   case ir_binop_gequal:
90      return BRW_CONDITIONAL_GE;
91   case ir_binop_equal:
92   case ir_binop_all_equal: /* same as equal for scalars */
93      return BRW_CONDITIONAL_Z;
94   case ir_binop_nequal:
95   case ir_binop_any_nequal: /* same as nequal for scalars */
96      return BRW_CONDITIONAL_NZ;
97   default:
98      unreachable("not reached: bad operation for comparison");
99   }
100}
101
102uint32_t
103brw_math_function(enum opcode op)
104{
105   switch (op) {
106   case SHADER_OPCODE_RCP:
107      return BRW_MATH_FUNCTION_INV;
108   case SHADER_OPCODE_RSQ:
109      return BRW_MATH_FUNCTION_RSQ;
110   case SHADER_OPCODE_SQRT:
111      return BRW_MATH_FUNCTION_SQRT;
112   case SHADER_OPCODE_EXP2:
113      return BRW_MATH_FUNCTION_EXP;
114   case SHADER_OPCODE_LOG2:
115      return BRW_MATH_FUNCTION_LOG;
116   case SHADER_OPCODE_POW:
117      return BRW_MATH_FUNCTION_POW;
118   case SHADER_OPCODE_SIN:
119      return BRW_MATH_FUNCTION_SIN;
120   case SHADER_OPCODE_COS:
121      return BRW_MATH_FUNCTION_COS;
122   case SHADER_OPCODE_INT_QUOTIENT:
123      return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
124   case SHADER_OPCODE_INT_REMAINDER:
125      return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
126   default:
127      unreachable("not reached: unknown math function");
128   }
129}
130
131bool
132brw_texture_offset(const nir_tex_instr *tex, unsigned src,
133                   uint32_t *offset_bits_out)
134{
135   if (!nir_src_is_const(tex->src[src].src))
136      return false;
137
138   const unsigned num_components = nir_tex_instr_src_size(tex, src);
139
140   /* Combine all three offsets into a single unsigned dword:
141    *
142    *    bits 11:8 - U Offset (X component)
143    *    bits  7:4 - V Offset (Y component)
144    *    bits  3:0 - R Offset (Z component)
145    */
146   uint32_t offset_bits = 0;
147   for (unsigned i = 0; i < num_components; i++) {
148      int offset = nir_src_comp_as_int(tex->src[src].src, i);
149
150      /* offset out of bounds; caller will handle it. */
151      if (offset > 7 || offset < -8)
152         return false;
153
154      const unsigned shift = 4 * (2 - i);
155      offset_bits |= (offset << shift) & (0xF << shift);
156   }
157
158   *offset_bits_out = offset_bits;
159
160   return true;
161}
162
163const char *
164brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
165{
166   switch (op) {
167   case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
168      /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169       * start of a loop in the IR.
170       */
171      if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
172         return "do";
173
174      /* The following conversion opcodes doesn't exist on Gen8+, but we use
175       * then to mark that we want to do the conversion.
176       */
177      if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
178         return "f32to16";
179
180      if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
181         return "f16to32";
182
183      assert(brw_opcode_desc(devinfo, op)->name);
184      return brw_opcode_desc(devinfo, op)->name;
185   case FS_OPCODE_FB_WRITE:
186      return "fb_write";
187   case FS_OPCODE_FB_WRITE_LOGICAL:
188      return "fb_write_logical";
189   case FS_OPCODE_REP_FB_WRITE:
190      return "rep_fb_write";
191   case FS_OPCODE_FB_READ:
192      return "fb_read";
193   case FS_OPCODE_FB_READ_LOGICAL:
194      return "fb_read_logical";
195
196   case SHADER_OPCODE_RCP:
197      return "rcp";
198   case SHADER_OPCODE_RSQ:
199      return "rsq";
200   case SHADER_OPCODE_SQRT:
201      return "sqrt";
202   case SHADER_OPCODE_EXP2:
203      return "exp2";
204   case SHADER_OPCODE_LOG2:
205      return "log2";
206   case SHADER_OPCODE_POW:
207      return "pow";
208   case SHADER_OPCODE_INT_QUOTIENT:
209      return "int_quot";
210   case SHADER_OPCODE_INT_REMAINDER:
211      return "int_rem";
212   case SHADER_OPCODE_SIN:
213      return "sin";
214   case SHADER_OPCODE_COS:
215      return "cos";
216
217   case SHADER_OPCODE_SEND:
218      return "send";
219
220   case SHADER_OPCODE_TEX:
221      return "tex";
222   case SHADER_OPCODE_TEX_LOGICAL:
223      return "tex_logical";
224   case SHADER_OPCODE_TXD:
225      return "txd";
226   case SHADER_OPCODE_TXD_LOGICAL:
227      return "txd_logical";
228   case SHADER_OPCODE_TXF:
229      return "txf";
230   case SHADER_OPCODE_TXF_LOGICAL:
231      return "txf_logical";
232   case SHADER_OPCODE_TXF_LZ:
233      return "txf_lz";
234   case SHADER_OPCODE_TXL:
235      return "txl";
236   case SHADER_OPCODE_TXL_LOGICAL:
237      return "txl_logical";
238   case SHADER_OPCODE_TXL_LZ:
239      return "txl_lz";
240   case SHADER_OPCODE_TXS:
241      return "txs";
242   case SHADER_OPCODE_TXS_LOGICAL:
243      return "txs_logical";
244   case FS_OPCODE_TXB:
245      return "txb";
246   case FS_OPCODE_TXB_LOGICAL:
247      return "txb_logical";
248   case SHADER_OPCODE_TXF_CMS:
249      return "txf_cms";
250   case SHADER_OPCODE_TXF_CMS_LOGICAL:
251      return "txf_cms_logical";
252   case SHADER_OPCODE_TXF_CMS_W:
253      return "txf_cms_w";
254   case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
255      return "txf_cms_w_logical";
256   case SHADER_OPCODE_TXF_UMS:
257      return "txf_ums";
258   case SHADER_OPCODE_TXF_UMS_LOGICAL:
259      return "txf_ums_logical";
260   case SHADER_OPCODE_TXF_MCS:
261      return "txf_mcs";
262   case SHADER_OPCODE_TXF_MCS_LOGICAL:
263      return "txf_mcs_logical";
264   case SHADER_OPCODE_LOD:
265      return "lod";
266   case SHADER_OPCODE_LOD_LOGICAL:
267      return "lod_logical";
268   case SHADER_OPCODE_TG4:
269      return "tg4";
270   case SHADER_OPCODE_TG4_LOGICAL:
271      return "tg4_logical";
272   case SHADER_OPCODE_TG4_OFFSET:
273      return "tg4_offset";
274   case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
275      return "tg4_offset_logical";
276   case SHADER_OPCODE_SAMPLEINFO:
277      return "sampleinfo";
278   case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
279      return "sampleinfo_logical";
280
281   case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
282      return "image_size_logical";
283
284   case SHADER_OPCODE_SHADER_TIME_ADD:
285      return "shader_time_add";
286
287   case VEC4_OPCODE_UNTYPED_ATOMIC:
288      return "untyped_atomic";
289   case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
290      return "untyped_atomic_logical";
291   case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
292      return "untyped_atomic_float_logical";
293   case VEC4_OPCODE_UNTYPED_SURFACE_READ:
294      return "untyped_surface_read";
295   case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
296      return "untyped_surface_read_logical";
297   case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
298      return "untyped_surface_write";
299   case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
300      return "untyped_surface_write_logical";
301   case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
302      return "a64_untyped_read_logical";
303   case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
304      return "a64_untyped_write_logical";
305   case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
306      return "a64_byte_scattered_read_logical";
307   case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
308      return "a64_byte_scattered_write_logical";
309   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
310      return "a64_untyped_atomic_logical";
311   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
312      return "a64_untyped_atomic_int64_logical";
313   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
314      return "a64_untyped_atomic_float_logical";
315   case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
316      return "typed_atomic_logical";
317   case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
318      return "typed_surface_read_logical";
319   case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
320      return "typed_surface_write_logical";
321   case SHADER_OPCODE_MEMORY_FENCE:
322      return "memory_fence";
323   case SHADER_OPCODE_INTERLOCK:
324      /* For an interlock we actually issue a memory fence via sendc. */
325      return "interlock";
326
327   case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
328      return "byte_scattered_read_logical";
329   case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
330      return "byte_scattered_write_logical";
331
332   case SHADER_OPCODE_LOAD_PAYLOAD:
333      return "load_payload";
334   case FS_OPCODE_PACK:
335      return "pack";
336
337   case SHADER_OPCODE_GEN4_SCRATCH_READ:
338      return "gen4_scratch_read";
339   case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
340      return "gen4_scratch_write";
341   case SHADER_OPCODE_GEN7_SCRATCH_READ:
342      return "gen7_scratch_read";
343   case SHADER_OPCODE_URB_WRITE_SIMD8:
344      return "gen8_urb_write_simd8";
345   case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
346      return "gen8_urb_write_simd8_per_slot";
347   case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
348      return "gen8_urb_write_simd8_masked";
349   case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
350      return "gen8_urb_write_simd8_masked_per_slot";
351   case SHADER_OPCODE_URB_READ_SIMD8:
352      return "urb_read_simd8";
353   case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
354      return "urb_read_simd8_per_slot";
355
356   case SHADER_OPCODE_FIND_LIVE_CHANNEL:
357      return "find_live_channel";
358   case SHADER_OPCODE_BROADCAST:
359      return "broadcast";
360   case SHADER_OPCODE_SHUFFLE:
361      return "shuffle";
362   case SHADER_OPCODE_SEL_EXEC:
363      return "sel_exec";
364   case SHADER_OPCODE_QUAD_SWIZZLE:
365      return "quad_swizzle";
366   case SHADER_OPCODE_CLUSTER_BROADCAST:
367      return "cluster_broadcast";
368
369   case SHADER_OPCODE_GET_BUFFER_SIZE:
370      return "get_buffer_size";
371
372   case VEC4_OPCODE_MOV_BYTES:
373      return "mov_bytes";
374   case VEC4_OPCODE_PACK_BYTES:
375      return "pack_bytes";
376   case VEC4_OPCODE_UNPACK_UNIFORM:
377      return "unpack_uniform";
378   case VEC4_OPCODE_DOUBLE_TO_F32:
379      return "double_to_f32";
380   case VEC4_OPCODE_DOUBLE_TO_D32:
381      return "double_to_d32";
382   case VEC4_OPCODE_DOUBLE_TO_U32:
383      return "double_to_u32";
384   case VEC4_OPCODE_TO_DOUBLE:
385      return "single_to_double";
386   case VEC4_OPCODE_PICK_LOW_32BIT:
387      return "pick_low_32bit";
388   case VEC4_OPCODE_PICK_HIGH_32BIT:
389      return "pick_high_32bit";
390   case VEC4_OPCODE_SET_LOW_32BIT:
391      return "set_low_32bit";
392   case VEC4_OPCODE_SET_HIGH_32BIT:
393      return "set_high_32bit";
394
395   case FS_OPCODE_DDX_COARSE:
396      return "ddx_coarse";
397   case FS_OPCODE_DDX_FINE:
398      return "ddx_fine";
399   case FS_OPCODE_DDY_COARSE:
400      return "ddy_coarse";
401   case FS_OPCODE_DDY_FINE:
402      return "ddy_fine";
403
404   case FS_OPCODE_LINTERP:
405      return "linterp";
406
407   case FS_OPCODE_PIXEL_X:
408      return "pixel_x";
409   case FS_OPCODE_PIXEL_Y:
410      return "pixel_y";
411
412   case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
413      return "uniform_pull_const";
414   case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
415      return "uniform_pull_const_gen7";
416   case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
417      return "varying_pull_const_gen4";
418   case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
419      return "varying_pull_const_logical";
420
421   case FS_OPCODE_DISCARD_JUMP:
422      return "discard_jump";
423
424   case FS_OPCODE_SET_SAMPLE_ID:
425      return "set_sample_id";
426
427   case FS_OPCODE_PACK_HALF_2x16_SPLIT:
428      return "pack_half_2x16_split";
429
430   case FS_OPCODE_PLACEHOLDER_HALT:
431      return "placeholder_halt";
432
433   case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
434      return "interp_sample";
435   case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
436      return "interp_shared_offset";
437   case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
438      return "interp_per_slot_offset";
439
440   case VS_OPCODE_URB_WRITE:
441      return "vs_urb_write";
442   case VS_OPCODE_PULL_CONSTANT_LOAD:
443      return "pull_constant_load";
444   case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
445      return "pull_constant_load_gen7";
446
447   case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
448      return "set_simd4x2_header_gen9";
449
450   case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
451      return "unpack_flags_simd4x2";
452
453   case GS_OPCODE_URB_WRITE:
454      return "gs_urb_write";
455   case GS_OPCODE_URB_WRITE_ALLOCATE:
456      return "gs_urb_write_allocate";
457   case GS_OPCODE_THREAD_END:
458      return "gs_thread_end";
459   case GS_OPCODE_SET_WRITE_OFFSET:
460      return "set_write_offset";
461   case GS_OPCODE_SET_VERTEX_COUNT:
462      return "set_vertex_count";
463   case GS_OPCODE_SET_DWORD_2:
464      return "set_dword_2";
465   case GS_OPCODE_PREPARE_CHANNEL_MASKS:
466      return "prepare_channel_masks";
467   case GS_OPCODE_SET_CHANNEL_MASKS:
468      return "set_channel_masks";
469   case GS_OPCODE_GET_INSTANCE_ID:
470      return "get_instance_id";
471   case GS_OPCODE_FF_SYNC:
472      return "ff_sync";
473   case GS_OPCODE_SET_PRIMITIVE_ID:
474      return "set_primitive_id";
475   case GS_OPCODE_SVB_WRITE:
476      return "gs_svb_write";
477   case GS_OPCODE_SVB_SET_DST_INDEX:
478      return "gs_svb_set_dst_index";
479   case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
480      return "gs_ff_sync_set_primitives";
481   case CS_OPCODE_CS_TERMINATE:
482      return "cs_terminate";
483   case SHADER_OPCODE_BARRIER:
484      return "barrier";
485   case SHADER_OPCODE_MULH:
486      return "mulh";
487   case SHADER_OPCODE_MOV_INDIRECT:
488      return "mov_indirect";
489
490   case VEC4_OPCODE_URB_READ:
491      return "urb_read";
492   case TCS_OPCODE_GET_INSTANCE_ID:
493      return "tcs_get_instance_id";
494   case TCS_OPCODE_URB_WRITE:
495      return "tcs_urb_write";
496   case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
497      return "tcs_set_input_urb_offsets";
498   case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
499      return "tcs_set_output_urb_offsets";
500   case TCS_OPCODE_GET_PRIMITIVE_ID:
501      return "tcs_get_primitive_id";
502   case TCS_OPCODE_CREATE_BARRIER_HEADER:
503      return "tcs_create_barrier_header";
504   case TCS_OPCODE_SRC0_010_IS_ZERO:
505      return "tcs_src0<0,1,0>_is_zero";
506   case TCS_OPCODE_RELEASE_INPUT:
507      return "tcs_release_input";
508   case TCS_OPCODE_THREAD_END:
509      return "tcs_thread_end";
510   case TES_OPCODE_CREATE_INPUT_READ_HEADER:
511      return "tes_create_input_read_header";
512   case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
513      return "tes_add_indirect_urb_offset";
514   case TES_OPCODE_GET_PRIMITIVE_ID:
515      return "tes_get_primitive_id";
516
517   case SHADER_OPCODE_RND_MODE:
518      return "rnd_mode";
519   }
520
521   unreachable("not reached");
522}
523
524bool
525brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
526{
527   union {
528      unsigned ud;
529      int d;
530      float f;
531      double df;
532   } imm, sat_imm = { 0 };
533
534   const unsigned size = type_sz(type);
535
536   /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
537    * irrelevant, so just check the size of the type and copy from/to an
538    * appropriately sized field.
539    */
540   if (size < 8)
541      imm.ud = reg->ud;
542   else
543      imm.df = reg->df;
544
545   switch (type) {
546   case BRW_REGISTER_TYPE_UD:
547   case BRW_REGISTER_TYPE_D:
548   case BRW_REGISTER_TYPE_UW:
549   case BRW_REGISTER_TYPE_W:
550   case BRW_REGISTER_TYPE_UQ:
551   case BRW_REGISTER_TYPE_Q:
552      /* Nothing to do. */
553      return false;
554   case BRW_REGISTER_TYPE_F:
555      sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
556      break;
557   case BRW_REGISTER_TYPE_DF:
558      sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
559      break;
560   case BRW_REGISTER_TYPE_UB:
561   case BRW_REGISTER_TYPE_B:
562      unreachable("no UB/B immediates");
563   case BRW_REGISTER_TYPE_V:
564   case BRW_REGISTER_TYPE_UV:
565   case BRW_REGISTER_TYPE_VF:
566      unreachable("unimplemented: saturate vector immediate");
567   case BRW_REGISTER_TYPE_HF:
568      unreachable("unimplemented: saturate HF immediate");
569   case BRW_REGISTER_TYPE_NF:
570      unreachable("no NF immediates");
571   }
572
573   if (size < 8) {
574      if (imm.ud != sat_imm.ud) {
575         reg->ud = sat_imm.ud;
576         return true;
577      }
578   } else {
579      if (imm.df != sat_imm.df) {
580         reg->df = sat_imm.df;
581         return true;
582      }
583   }
584   return false;
585}
586
587bool
588brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
589{
590   switch (type) {
591   case BRW_REGISTER_TYPE_D:
592   case BRW_REGISTER_TYPE_UD:
593      reg->d = -reg->d;
594      return true;
595   case BRW_REGISTER_TYPE_W:
596   case BRW_REGISTER_TYPE_UW: {
597      uint16_t value = -(int16_t)reg->ud;
598      reg->ud = value | (uint32_t)value << 16;
599      return true;
600   }
601   case BRW_REGISTER_TYPE_F:
602      reg->f = -reg->f;
603      return true;
604   case BRW_REGISTER_TYPE_VF:
605      reg->ud ^= 0x80808080;
606      return true;
607   case BRW_REGISTER_TYPE_DF:
608      reg->df = -reg->df;
609      return true;
610   case BRW_REGISTER_TYPE_UQ:
611   case BRW_REGISTER_TYPE_Q:
612      reg->d64 = -reg->d64;
613      return true;
614   case BRW_REGISTER_TYPE_UB:
615   case BRW_REGISTER_TYPE_B:
616      unreachable("no UB/B immediates");
617   case BRW_REGISTER_TYPE_UV:
618   case BRW_REGISTER_TYPE_V:
619      assert(!"unimplemented: negate UV/V immediate");
620   case BRW_REGISTER_TYPE_HF:
621      reg->ud ^= 0x80008000;
622      return true;
623   case BRW_REGISTER_TYPE_NF:
624      unreachable("no NF immediates");
625   }
626
627   return false;
628}
629
630bool
631brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
632{
633   switch (type) {
634   case BRW_REGISTER_TYPE_D:
635      reg->d = abs(reg->d);
636      return true;
637   case BRW_REGISTER_TYPE_W: {
638      uint16_t value = abs((int16_t)reg->ud);
639      reg->ud = value | (uint32_t)value << 16;
640      return true;
641   }
642   case BRW_REGISTER_TYPE_F:
643      reg->f = fabsf(reg->f);
644      return true;
645   case BRW_REGISTER_TYPE_DF:
646      reg->df = fabs(reg->df);
647      return true;
648   case BRW_REGISTER_TYPE_VF:
649      reg->ud &= ~0x80808080;
650      return true;
651   case BRW_REGISTER_TYPE_Q:
652      reg->d64 = imaxabs(reg->d64);
653      return true;
654   case BRW_REGISTER_TYPE_UB:
655   case BRW_REGISTER_TYPE_B:
656      unreachable("no UB/B immediates");
657   case BRW_REGISTER_TYPE_UQ:
658   case BRW_REGISTER_TYPE_UD:
659   case BRW_REGISTER_TYPE_UW:
660   case BRW_REGISTER_TYPE_UV:
661      /* Presumably the absolute value modifier on an unsigned source is a
662       * nop, but it would be nice to confirm.
663       */
664      assert(!"unimplemented: abs unsigned immediate");
665   case BRW_REGISTER_TYPE_V:
666      assert(!"unimplemented: abs V immediate");
667   case BRW_REGISTER_TYPE_HF:
668      reg->ud &= ~0x80008000;
669      return true;
670   case BRW_REGISTER_TYPE_NF:
671      unreachable("no NF immediates");
672   }
673
674   return false;
675}
676
677backend_shader::backend_shader(const struct brw_compiler *compiler,
678                               void *log_data,
679                               void *mem_ctx,
680                               const nir_shader *shader,
681                               struct brw_stage_prog_data *stage_prog_data)
682   : compiler(compiler),
683     log_data(log_data),
684     devinfo(compiler->devinfo),
685     nir(shader),
686     stage_prog_data(stage_prog_data),
687     mem_ctx(mem_ctx),
688     cfg(NULL),
689     stage(shader->info.stage)
690{
691   debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
692   stage_name = _mesa_shader_stage_to_string(stage);
693   stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
694}
695
696backend_shader::~backend_shader()
697{
698}
699
700bool
701backend_reg::equals(const backend_reg &r) const
702{
703   return brw_regs_equal(this, &r) && offset == r.offset;
704}
705
706bool
707backend_reg::negative_equals(const backend_reg &r) const
708{
709   return brw_regs_negative_equal(this, &r) && offset == r.offset;
710}
711
712bool
713backend_reg::is_zero() const
714{
715   if (file != IMM)
716      return false;
717
718   assert(type_sz(type) > 1);
719
720   switch (type) {
721   case BRW_REGISTER_TYPE_HF:
722      assert((d & 0xffff) == ((d >> 16) & 0xffff));
723      return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
724   case BRW_REGISTER_TYPE_F:
725      return f == 0;
726   case BRW_REGISTER_TYPE_DF:
727      return df == 0;
728   case BRW_REGISTER_TYPE_W:
729   case BRW_REGISTER_TYPE_UW:
730      assert((d & 0xffff) == ((d >> 16) & 0xffff));
731      return (d & 0xffff) == 0;
732   case BRW_REGISTER_TYPE_D:
733   case BRW_REGISTER_TYPE_UD:
734      return d == 0;
735   case BRW_REGISTER_TYPE_UQ:
736   case BRW_REGISTER_TYPE_Q:
737      return u64 == 0;
738   default:
739      return false;
740   }
741}
742
743bool
744backend_reg::is_one() const
745{
746   if (file != IMM)
747      return false;
748
749   assert(type_sz(type) > 1);
750
751   switch (type) {
752   case BRW_REGISTER_TYPE_HF:
753      assert((d & 0xffff) == ((d >> 16) & 0xffff));
754      return (d & 0xffff) == 0x3c00;
755   case BRW_REGISTER_TYPE_F:
756      return f == 1.0f;
757   case BRW_REGISTER_TYPE_DF:
758      return df == 1.0;
759   case BRW_REGISTER_TYPE_W:
760   case BRW_REGISTER_TYPE_UW:
761      assert((d & 0xffff) == ((d >> 16) & 0xffff));
762      return (d & 0xffff) == 1;
763   case BRW_REGISTER_TYPE_D:
764   case BRW_REGISTER_TYPE_UD:
765      return d == 1;
766   case BRW_REGISTER_TYPE_UQ:
767   case BRW_REGISTER_TYPE_Q:
768      return u64 == 1;
769   default:
770      return false;
771   }
772}
773
774bool
775backend_reg::is_negative_one() const
776{
777   if (file != IMM)
778      return false;
779
780   assert(type_sz(type) > 1);
781
782   switch (type) {
783   case BRW_REGISTER_TYPE_HF:
784      assert((d & 0xffff) == ((d >> 16) & 0xffff));
785      return (d & 0xffff) == 0xbc00;
786   case BRW_REGISTER_TYPE_F:
787      return f == -1.0;
788   case BRW_REGISTER_TYPE_DF:
789      return df == -1.0;
790   case BRW_REGISTER_TYPE_W:
791      assert((d & 0xffff) == ((d >> 16) & 0xffff));
792      return (d & 0xffff) == 0xffff;
793   case BRW_REGISTER_TYPE_D:
794      return d == -1;
795   case BRW_REGISTER_TYPE_Q:
796      return d64 == -1;
797   default:
798      return false;
799   }
800}
801
802bool
803backend_reg::is_null() const
804{
805   return file == ARF && nr == BRW_ARF_NULL;
806}
807
808
809bool
810backend_reg::is_accumulator() const
811{
812   return file == ARF && nr == BRW_ARF_ACCUMULATOR;
813}
814
815bool
816backend_instruction::is_commutative() const
817{
818   switch (opcode) {
819   case BRW_OPCODE_AND:
820   case BRW_OPCODE_OR:
821   case BRW_OPCODE_XOR:
822   case BRW_OPCODE_ADD:
823   case BRW_OPCODE_MUL:
824   case SHADER_OPCODE_MULH:
825      return true;
826   case BRW_OPCODE_SEL:
827      /* MIN and MAX are commutative. */
828      if (conditional_mod == BRW_CONDITIONAL_GE ||
829          conditional_mod == BRW_CONDITIONAL_L) {
830         return true;
831      }
832      /* fallthrough */
833   default:
834      return false;
835   }
836}
837
838bool
839backend_instruction::is_3src(const struct gen_device_info *devinfo) const
840{
841   return ::is_3src(devinfo, opcode);
842}
843
844bool
845backend_instruction::is_tex() const
846{
847   return (opcode == SHADER_OPCODE_TEX ||
848           opcode == FS_OPCODE_TXB ||
849           opcode == SHADER_OPCODE_TXD ||
850           opcode == SHADER_OPCODE_TXF ||
851           opcode == SHADER_OPCODE_TXF_LZ ||
852           opcode == SHADER_OPCODE_TXF_CMS ||
853           opcode == SHADER_OPCODE_TXF_CMS_W ||
854           opcode == SHADER_OPCODE_TXF_UMS ||
855           opcode == SHADER_OPCODE_TXF_MCS ||
856           opcode == SHADER_OPCODE_TXL ||
857           opcode == SHADER_OPCODE_TXL_LZ ||
858           opcode == SHADER_OPCODE_TXS ||
859           opcode == SHADER_OPCODE_LOD ||
860           opcode == SHADER_OPCODE_TG4 ||
861           opcode == SHADER_OPCODE_TG4_OFFSET ||
862           opcode == SHADER_OPCODE_SAMPLEINFO);
863}
864
865bool
866backend_instruction::is_math() const
867{
868   return (opcode == SHADER_OPCODE_RCP ||
869           opcode == SHADER_OPCODE_RSQ ||
870           opcode == SHADER_OPCODE_SQRT ||
871           opcode == SHADER_OPCODE_EXP2 ||
872           opcode == SHADER_OPCODE_LOG2 ||
873           opcode == SHADER_OPCODE_SIN ||
874           opcode == SHADER_OPCODE_COS ||
875           opcode == SHADER_OPCODE_INT_QUOTIENT ||
876           opcode == SHADER_OPCODE_INT_REMAINDER ||
877           opcode == SHADER_OPCODE_POW);
878}
879
880bool
881backend_instruction::is_control_flow() const
882{
883   switch (opcode) {
884   case BRW_OPCODE_DO:
885   case BRW_OPCODE_WHILE:
886   case BRW_OPCODE_IF:
887   case BRW_OPCODE_ELSE:
888   case BRW_OPCODE_ENDIF:
889   case BRW_OPCODE_BREAK:
890   case BRW_OPCODE_CONTINUE:
891      return true;
892   default:
893      return false;
894   }
895}
896
897bool
898backend_instruction::can_do_source_mods() const
899{
900   switch (opcode) {
901   case BRW_OPCODE_ADDC:
902   case BRW_OPCODE_BFE:
903   case BRW_OPCODE_BFI1:
904   case BRW_OPCODE_BFI2:
905   case BRW_OPCODE_BFREV:
906   case BRW_OPCODE_CBIT:
907   case BRW_OPCODE_FBH:
908   case BRW_OPCODE_FBL:
909   case BRW_OPCODE_SUBB:
910   case SHADER_OPCODE_BROADCAST:
911   case SHADER_OPCODE_CLUSTER_BROADCAST:
912   case SHADER_OPCODE_MOV_INDIRECT:
913      return false;
914   default:
915      return true;
916   }
917}
918
919bool
920backend_instruction::can_do_saturate() const
921{
922   switch (opcode) {
923   case BRW_OPCODE_ADD:
924   case BRW_OPCODE_ASR:
925   case BRW_OPCODE_AVG:
926   case BRW_OPCODE_DP2:
927   case BRW_OPCODE_DP3:
928   case BRW_OPCODE_DP4:
929   case BRW_OPCODE_DPH:
930   case BRW_OPCODE_F16TO32:
931   case BRW_OPCODE_F32TO16:
932   case BRW_OPCODE_LINE:
933   case BRW_OPCODE_LRP:
934   case BRW_OPCODE_MAC:
935   case BRW_OPCODE_MAD:
936   case BRW_OPCODE_MATH:
937   case BRW_OPCODE_MOV:
938   case BRW_OPCODE_MUL:
939   case SHADER_OPCODE_MULH:
940   case BRW_OPCODE_PLN:
941   case BRW_OPCODE_RNDD:
942   case BRW_OPCODE_RNDE:
943   case BRW_OPCODE_RNDU:
944   case BRW_OPCODE_RNDZ:
945   case BRW_OPCODE_SEL:
946   case BRW_OPCODE_SHL:
947   case BRW_OPCODE_SHR:
948   case FS_OPCODE_LINTERP:
949   case SHADER_OPCODE_COS:
950   case SHADER_OPCODE_EXP2:
951   case SHADER_OPCODE_LOG2:
952   case SHADER_OPCODE_POW:
953   case SHADER_OPCODE_RCP:
954   case SHADER_OPCODE_RSQ:
955   case SHADER_OPCODE_SIN:
956   case SHADER_OPCODE_SQRT:
957      return true;
958   default:
959      return false;
960   }
961}
962
963bool
964backend_instruction::can_do_cmod() const
965{
966   switch (opcode) {
967   case BRW_OPCODE_ADD:
968   case BRW_OPCODE_ADDC:
969   case BRW_OPCODE_AND:
970   case BRW_OPCODE_ASR:
971   case BRW_OPCODE_AVG:
972   case BRW_OPCODE_CMP:
973   case BRW_OPCODE_CMPN:
974   case BRW_OPCODE_DP2:
975   case BRW_OPCODE_DP3:
976   case BRW_OPCODE_DP4:
977   case BRW_OPCODE_DPH:
978   case BRW_OPCODE_F16TO32:
979   case BRW_OPCODE_F32TO16:
980   case BRW_OPCODE_FRC:
981   case BRW_OPCODE_LINE:
982   case BRW_OPCODE_LRP:
983   case BRW_OPCODE_LZD:
984   case BRW_OPCODE_MAC:
985   case BRW_OPCODE_MACH:
986   case BRW_OPCODE_MAD:
987   case BRW_OPCODE_MOV:
988   case BRW_OPCODE_MUL:
989   case BRW_OPCODE_NOT:
990   case BRW_OPCODE_OR:
991   case BRW_OPCODE_PLN:
992   case BRW_OPCODE_RNDD:
993   case BRW_OPCODE_RNDE:
994   case BRW_OPCODE_RNDU:
995   case BRW_OPCODE_RNDZ:
996   case BRW_OPCODE_SAD2:
997   case BRW_OPCODE_SADA2:
998   case BRW_OPCODE_SHL:
999   case BRW_OPCODE_SHR:
1000   case BRW_OPCODE_SUBB:
1001   case BRW_OPCODE_XOR:
1002   case FS_OPCODE_LINTERP:
1003      return true;
1004   default:
1005      return false;
1006   }
1007}
1008
1009bool
1010backend_instruction::reads_accumulator_implicitly() const
1011{
1012   switch (opcode) {
1013   case BRW_OPCODE_MAC:
1014   case BRW_OPCODE_MACH:
1015   case BRW_OPCODE_SADA2:
1016      return true;
1017   default:
1018      return false;
1019   }
1020}
1021
1022bool
1023backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1024{
1025   return writes_accumulator ||
1026          (devinfo->gen < 6 &&
1027           ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1028            (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1029          (opcode == FS_OPCODE_LINTERP &&
1030           (!devinfo->has_pln || devinfo->gen <= 6));
1031}
1032
1033bool
1034backend_instruction::has_side_effects() const
1035{
1036   switch (opcode) {
1037   case SHADER_OPCODE_SEND:
1038      return send_has_side_effects;
1039
1040   case VEC4_OPCODE_UNTYPED_ATOMIC:
1041   case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1042   case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1043   case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1044   case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1045   case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1046   case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1047   case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1048   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1049   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1050   case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1051   case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1052   case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1053   case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1054   case SHADER_OPCODE_MEMORY_FENCE:
1055   case SHADER_OPCODE_INTERLOCK:
1056   case SHADER_OPCODE_URB_WRITE_SIMD8:
1057   case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1058   case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1059   case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1060   case FS_OPCODE_FB_WRITE:
1061   case FS_OPCODE_FB_WRITE_LOGICAL:
1062   case FS_OPCODE_REP_FB_WRITE:
1063   case SHADER_OPCODE_BARRIER:
1064   case TCS_OPCODE_URB_WRITE:
1065   case TCS_OPCODE_RELEASE_INPUT:
1066   case SHADER_OPCODE_RND_MODE:
1067      return true;
1068   default:
1069      return eot;
1070   }
1071}
1072
1073bool
1074backend_instruction::is_volatile() const
1075{
1076   switch (opcode) {
1077   case SHADER_OPCODE_SEND:
1078      return send_is_volatile;
1079
1080   case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1081   case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1082   case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1083   case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1084   case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1085   case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1086   case SHADER_OPCODE_URB_READ_SIMD8:
1087   case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1088   case VEC4_OPCODE_URB_READ:
1089      return true;
1090   default:
1091      return false;
1092   }
1093}
1094
1095#ifndef NDEBUG
1096static bool
1097inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1098{
1099   bool found = false;
1100   foreach_inst_in_block (backend_instruction, i, block) {
1101      if (inst == i) {
1102         found = true;
1103      }
1104   }
1105   return found;
1106}
1107#endif
1108
1109static void
1110adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1111{
1112   for (bblock_t *block_iter = start_block->next();
1113        block_iter;
1114        block_iter = block_iter->next()) {
1115      block_iter->start_ip += ip_adjustment;
1116      block_iter->end_ip += ip_adjustment;
1117   }
1118}
1119
1120void
1121backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1122{
1123   assert(this != inst);
1124
1125   if (!this->is_head_sentinel())
1126      assert(inst_is_in_block(block, this) || !"Instruction not in block");
1127
1128   block->end_ip++;
1129
1130   adjust_later_block_ips(block, 1);
1131
1132   exec_node::insert_after(inst);
1133}
1134
1135void
1136backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1137{
1138   assert(this != inst);
1139
1140   if (!this->is_tail_sentinel())
1141      assert(inst_is_in_block(block, this) || !"Instruction not in block");
1142
1143   block->end_ip++;
1144
1145   adjust_later_block_ips(block, 1);
1146
1147   exec_node::insert_before(inst);
1148}
1149
1150void
1151backend_instruction::insert_before(bblock_t *block, exec_list *list)
1152{
1153   assert(inst_is_in_block(block, this) || !"Instruction not in block");
1154
1155   unsigned num_inst = list->length();
1156
1157   block->end_ip += num_inst;
1158
1159   adjust_later_block_ips(block, num_inst);
1160
1161   exec_node::insert_before(list);
1162}
1163
1164void
1165backend_instruction::remove(bblock_t *block)
1166{
1167   assert(inst_is_in_block(block, this) || !"Instruction not in block");
1168
1169   adjust_later_block_ips(block, -1);
1170
1171   if (block->start_ip == block->end_ip) {
1172      block->cfg->remove_block(block);
1173   } else {
1174      block->end_ip--;
1175   }
1176
1177   exec_node::remove();
1178}
1179
1180void
1181backend_shader::dump_instructions()
1182{
1183   dump_instructions(NULL);
1184}
1185
1186void
1187backend_shader::dump_instructions(const char *name)
1188{
1189   FILE *file = stderr;
1190   if (name && geteuid() != 0) {
1191      file = fopen(name, "w");
1192      if (!file)
1193         file = stderr;
1194   }
1195
1196   if (cfg) {
1197      int ip = 0;
1198      foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1199         if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1200            fprintf(file, "%4d: ", ip++);
1201         dump_instruction(inst, file);
1202      }
1203   } else {
1204      int ip = 0;
1205      foreach_in_list(backend_instruction, inst, &instructions) {
1206         if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1207            fprintf(file, "%4d: ", ip++);
1208         dump_instruction(inst, file);
1209      }
1210   }
1211
1212   if (file != stderr) {
1213      fclose(file);
1214   }
1215}
1216
1217void
1218backend_shader::calculate_cfg()
1219{
1220   if (this->cfg)
1221      return;
1222   cfg = new(mem_ctx) cfg_t(&this->instructions);
1223}
1224
1225extern "C" const unsigned *
1226brw_compile_tes(const struct brw_compiler *compiler,
1227                void *log_data,
1228                void *mem_ctx,
1229                const struct brw_tes_prog_key *key,
1230                const struct brw_vue_map *input_vue_map,
1231                struct brw_tes_prog_data *prog_data,
1232                nir_shader *nir,
1233                struct gl_program *prog,
1234                int shader_time_index,
1235                char **error_str)
1236{
1237   const struct gen_device_info *devinfo = compiler->devinfo;
1238   const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1239   const unsigned *assembly;
1240
1241   nir->info.inputs_read = key->inputs_read;
1242   nir->info.patch_inputs_read = key->patch_inputs_read;
1243
1244   nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1245   brw_nir_lower_tes_inputs(nir, input_vue_map);
1246   brw_nir_lower_vue_outputs(nir);
1247   nir = brw_postprocess_nir(nir, compiler, is_scalar);
1248
1249   brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1250                       nir->info.outputs_written,
1251                       nir->info.separate_shader);
1252
1253   unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1254
1255   assert(output_size_bytes >= 1);
1256   if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1257      if (error_str)
1258         *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1259      return NULL;
1260   }
1261
1262   prog_data->base.clip_distance_mask =
1263      ((1 << nir->info.clip_distance_array_size) - 1);
1264   prog_data->base.cull_distance_mask =
1265      ((1 << nir->info.cull_distance_array_size) - 1) <<
1266      nir->info.clip_distance_array_size;
1267
1268   /* URB entry sizes are stored as a multiple of 64 bytes. */
1269   prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1270
1271   /* On Cannonlake software shall not program an allocation size that
1272    * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1273    */
1274   if (devinfo->gen == 10 &&
1275       prog_data->base.urb_entry_size % 3 == 0)
1276      prog_data->base.urb_entry_size++;
1277
1278   prog_data->base.urb_read_length = 0;
1279
1280   STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1281   STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1282                 TESS_SPACING_FRACTIONAL_ODD - 1);
1283   STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1284                 TESS_SPACING_FRACTIONAL_EVEN - 1);
1285
1286   prog_data->partitioning =
1287      (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1288
1289   switch (nir->info.tess.primitive_mode) {
1290   case GL_QUADS:
1291      prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1292      break;
1293   case GL_TRIANGLES:
1294      prog_data->domain = BRW_TESS_DOMAIN_TRI;
1295      break;
1296   case GL_ISOLINES:
1297      prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1298      break;
1299   default:
1300      unreachable("invalid domain shader primitive mode");
1301   }
1302
1303   if (nir->info.tess.point_mode) {
1304      prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1305   } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1306      prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1307   } else {
1308      /* Hardware winding order is backwards from OpenGL */
1309      prog_data->output_topology =
1310         nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1311                             : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1312   }
1313
1314   if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1315      fprintf(stderr, "TES Input ");
1316      brw_print_vue_map(stderr, input_vue_map);
1317      fprintf(stderr, "TES Output ");
1318      brw_print_vue_map(stderr, &prog_data->base.vue_map);
1319   }
1320
1321   if (is_scalar) {
1322      fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1323                   &prog_data->base.base, NULL, nir, 8,
1324                   shader_time_index, input_vue_map);
1325      if (!v.run_tes()) {
1326         if (error_str)
1327            *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1328         return NULL;
1329      }
1330
1331      prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1332      prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1333
1334      fs_generator g(compiler, log_data, mem_ctx,
1335                     &prog_data->base.base, v.promoted_constants, false,
1336                     MESA_SHADER_TESS_EVAL);
1337      if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1338         g.enable_debug(ralloc_asprintf(mem_ctx,
1339                                        "%s tessellation evaluation shader %s",
1340                                        nir->info.label ? nir->info.label
1341                                                        : "unnamed",
1342                                        nir->info.name));
1343      }
1344
1345      g.generate_code(v.cfg, 8);
1346
1347      assembly = g.get_assembly();
1348   } else {
1349      brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1350			      nir, mem_ctx, shader_time_index);
1351      if (!v.run()) {
1352	 if (error_str)
1353	    *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1354	 return NULL;
1355      }
1356
1357      if (unlikely(INTEL_DEBUG & DEBUG_TES))
1358	 v.dump_instructions();
1359
1360      assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1361                                            &prog_data->base, v.cfg);
1362   }
1363
1364   return assembly;
1365}
1366