1/*
2 * Copyright © 2008-2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Eric Anholt <eric@anholt.net>
25 *
26 */
27
28/**
29 * @file brw_bufmgr.h
30 *
31 * Public definitions of Intel-specific bufmgr functions.
32 */
33
34#ifndef INTEL_BUFMGR_H
35#define INTEL_BUFMGR_H
36
37#include <stdbool.h>
38#include <stdint.h>
39#include <stdio.h>
40#include <time.h>
41
42#include "util/u_atomic.h"
43#include "util/list.h"
44
45#if defined(__cplusplus)
46extern "C" {
47#endif
48
49struct gen_device_info;
50struct brw_context;
51
52/**
53 * Memory zones.  When allocating a buffer, you can request that it is
54 * placed into a specific region of the virtual address space (PPGTT).
55 *
56 * Most buffers can go anywhere (BRW_MEMZONE_OTHER).  Some buffers are
57 * accessed via an offset from a base address.  STATE_BASE_ADDRESS has
58 * a maximum 4GB size for each region, so we need to restrict those
59 * buffers to be within 4GB of the base.  Each memory zone corresponds
60 * to a particular base address.
61 *
62 * Currently, i965 partitions the address space into two regions:
63 *
64 * - Low 4GB
65 * - Full 48-bit address space
66 *
67 * Eventually, we hope to carve out 4GB of VMA for each base address.
68 */
69enum brw_memory_zone {
70   BRW_MEMZONE_LOW_4G,
71   BRW_MEMZONE_OTHER,
72
73   /* Shaders - Instruction State Base Address */
74   BRW_MEMZONE_SHADER  = BRW_MEMZONE_LOW_4G,
75
76   /* Scratch - General State Base Address */
77   BRW_MEMZONE_SCRATCH = BRW_MEMZONE_LOW_4G,
78
79   /* Surface State Base Address */
80   BRW_MEMZONE_SURFACE = BRW_MEMZONE_LOW_4G,
81
82   /* Dynamic State Base Address */
83   BRW_MEMZONE_DYNAMIC = BRW_MEMZONE_LOW_4G,
84};
85
86#define BRW_MEMZONE_COUNT (BRW_MEMZONE_OTHER + 1)
87
88struct brw_bo {
89   /**
90    * Size in bytes of the buffer object.
91    *
92    * The size may be larger than the size originally requested for the
93    * allocation, such as being aligned to page size.
94    */
95   uint64_t size;
96
97   /** Buffer manager context associated with this buffer object */
98   struct brw_bufmgr *bufmgr;
99
100   /** The GEM handle for this buffer object. */
101   uint32_t gem_handle;
102
103   /**
104    * Offset of the buffer inside the Graphics Translation Table.
105    *
106    * This is effectively our GPU address for the buffer and we use it
107    * as our base for all state pointers into the buffer. However, since the
108    * kernel may be forced to move it around during the course of the
109    * buffer's lifetime, we can only know where the buffer was on the last
110    * execbuf. We presume, and are usually right, that the buffer will not
111    * move and so we use that last offset for the next batch and by doing
112    * so we can avoid having the kernel perform a relocation fixup pass as
113    * our pointers inside the batch will be using the correct base offset.
114    *
115    * Since we do use it as a base address for the next batch of pointers,
116    * the kernel treats our offset as a request, and if possible will
117    * arrange the buffer to placed at that address (trying to balance
118    * the cost of buffer migration versus the cost of performing
119    * relocations). Furthermore, we can force the kernel to place the buffer,
120    * or report a failure if we specified a conflicting offset, at our chosen
121    * offset by specifying EXEC_OBJECT_PINNED.
122    *
123    * Note the GTT may be either per context, or shared globally across the
124    * system. On a shared system, our buffers have to contend for address
125    * space with both aperture mappings and framebuffers and so are more
126    * likely to be moved. On a full ppGTT system, each batch exists in its
127    * own GTT, and so each buffer may have their own offset within each
128    * context.
129    */
130   uint64_t gtt_offset;
131
132   /**
133    * The validation list index for this buffer, or -1 when not in a batch.
134    * Note that a single buffer may be in multiple batches (contexts), and
135    * this is a global field, which refers to the last batch using the BO.
136    * It should not be considered authoritative, but can be used to avoid a
137    * linear walk of the validation list in the common case by guessing that
138    * exec_bos[bo->index] == bo and confirming whether that's the case.
139    */
140   unsigned index;
141
142   /**
143    * Boolean of whether the GPU is definitely not accessing the buffer.
144    *
145    * This is only valid when reusable, since non-reusable
146    * buffers are those that have been shared with other
147    * processes, so we don't know their state.
148    */
149   bool idle;
150
151   int refcount;
152   const char *name;
153
154   uint64_t kflags;
155
156   /**
157    * Kenel-assigned global name for this object
158    *
159    * List contains both flink named and prime fd'd objects
160    */
161   unsigned int global_name;
162
163   /**
164    * Current tiling mode
165    */
166   uint32_t tiling_mode;
167   uint32_t swizzle_mode;
168   uint32_t stride;
169
170   time_t free_time;
171
172   /** Mapped address for the buffer, saved across map/unmap cycles */
173   void *map_cpu;
174   /** GTT virtual address for the buffer, saved across map/unmap cycles */
175   void *map_gtt;
176   /** WC CPU address for the buffer, saved across map/unmap cycles */
177   void *map_wc;
178
179   /** BO cache list */
180   struct list_head head;
181
182   /**
183    * Boolean of whether this buffer can be re-used
184    */
185   bool reusable;
186
187   /**
188    * Boolean of whether this buffer has been shared with an external client.
189    */
190   bool external;
191
192   /**
193    * Boolean of whether this buffer is cache coherent
194    */
195   bool cache_coherent;
196};
197
198#define BO_ALLOC_BUSY       (1<<0)
199#define BO_ALLOC_ZEROED     (1<<1)
200
201/**
202 * Allocate a buffer object.
203 *
204 * Buffer objects are not necessarily initially mapped into CPU virtual
205 * address space or graphics device aperture.  They must be mapped
206 * using brw_bo_map() to be used by the CPU.
207 */
208struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
209                            uint64_t size, enum brw_memory_zone memzone);
210
211/**
212 * Allocate a tiled buffer object.
213 *
214 * Alignment for tiled objects is set automatically; the 'flags'
215 * argument provides a hint about how the object will be used initially.
216 *
217 * Valid tiling formats are:
218 *  I915_TILING_NONE
219 *  I915_TILING_X
220 *  I915_TILING_Y
221 */
222struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
223                                  const char *name,
224                                  uint64_t size,
225                                  enum brw_memory_zone memzone,
226                                  uint32_t tiling_mode,
227                                  uint32_t pitch,
228                                  unsigned flags);
229
230/**
231 * Allocate a tiled buffer object.
232 *
233 * Alignment for tiled objects is set automatically; the 'flags'
234 * argument provides a hint about how the object will be used initially.
235 *
236 * Valid tiling formats are:
237 *  I915_TILING_NONE
238 *  I915_TILING_X
239 *  I915_TILING_Y
240 *
241 * Note the tiling format may be rejected; callers should check the
242 * 'tiling_mode' field on return, as well as the pitch value, which
243 * may have been rounded up to accommodate for tiling restrictions.
244 */
245struct brw_bo *brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr,
246                                     const char *name,
247                                     int x, int y, int cpp,
248                                     enum brw_memory_zone memzone,
249                                     uint32_t tiling_mode,
250                                     uint32_t *pitch,
251                                     unsigned flags);
252
253/** Takes a reference on a buffer object */
254static inline void
255brw_bo_reference(struct brw_bo *bo)
256{
257   p_atomic_inc(&bo->refcount);
258}
259
260/**
261 * Releases a reference on a buffer object, freeing the data if
262 * no references remain.
263 */
264void brw_bo_unreference(struct brw_bo *bo);
265
266/* Must match MapBufferRange interface (for convenience) */
267#define MAP_READ        GL_MAP_READ_BIT
268#define MAP_WRITE       GL_MAP_WRITE_BIT
269#define MAP_ASYNC       GL_MAP_UNSYNCHRONIZED_BIT
270#define MAP_PERSISTENT  GL_MAP_PERSISTENT_BIT
271#define MAP_COHERENT    GL_MAP_COHERENT_BIT
272/* internal */
273#define MAP_INTERNAL_MASK       (0xff << 24)
274#define MAP_RAW                 (0x01 << 24)
275
276/**
277 * Maps the buffer into userspace.
278 *
279 * This function will block waiting for any existing execution on the
280 * buffer to complete, first.  The resulting mapping is returned.
281 */
282MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct brw_bo *bo, unsigned flags);
283
284/**
285 * Reduces the refcount on the userspace mapping of the buffer
286 * object.
287 */
288static inline int brw_bo_unmap(UNUSED struct brw_bo *bo) { return 0; }
289
290/** Write data into an object. */
291int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,
292                   uint64_t size, const void *data);
293/**
294 * Waits for rendering to an object by the GPU to have completed.
295 *
296 * This is not required for any access to the BO by bo_map,
297 * bo_subdata, etc.  It is merely a way for the driver to implement
298 * glFinish.
299 */
300void brw_bo_wait_rendering(struct brw_bo *bo);
301
302/**
303 * Tears down the buffer manager instance.
304 */
305void brw_bufmgr_destroy(struct brw_bufmgr *bufmgr);
306
307/**
308 * Get the current tiling (and resulting swizzling) mode for the bo.
309 *
310 * \param buf Buffer to get tiling mode for
311 * \param tiling_mode returned tiling mode
312 * \param swizzle_mode returned swizzling mode
313 */
314int brw_bo_get_tiling(struct brw_bo *bo, uint32_t *tiling_mode,
315                      uint32_t *swizzle_mode);
316
317/**
318 * Create a visible name for a buffer which can be used by other apps
319 *
320 * \param buf Buffer to create a name for
321 * \param name Returned name
322 */
323int brw_bo_flink(struct brw_bo *bo, uint32_t *name);
324
325/**
326 * Returns 1 if mapping the buffer for write could cause the process
327 * to block, due to the object being active in the GPU.
328 */
329int brw_bo_busy(struct brw_bo *bo);
330
331/**
332 * Specify the volatility of the buffer.
333 * \param bo Buffer to create a name for
334 * \param madv The purgeable status
335 *
336 * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
337 * reclaimed under memory pressure. If you subsequently require the buffer,
338 * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
339 *
340 * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
341 * marked as I915_MADV_DONTNEED.
342 */
343int brw_bo_madvise(struct brw_bo *bo, int madv);
344
345/* drm_bacon_bufmgr_gem.c */
346struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd);
347struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
348                                           const char *name,
349                                           unsigned int handle);
350void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);
351
352int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
353
354uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
355
356int brw_hw_context_set_priority(struct brw_bufmgr *bufmgr,
357                                uint32_t ctx_id,
358                                int priority);
359
360void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id);
361
362int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
363struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
364                                            int prime_fd);
365struct brw_bo *brw_bo_gem_create_from_prime_tiled(struct brw_bufmgr *bufmgr,
366                                                  int prime_fd,
367                                                  uint32_t tiling_mode,
368                                                  uint32_t stride);
369
370uint32_t brw_bo_export_gem_handle(struct brw_bo *bo);
371
372int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
373                 uint64_t *result);
374
375bool brw_using_softpin(struct brw_bufmgr *bufmgr);
376
377/** @{ */
378
379#if defined(__cplusplus)
380}
381#endif
382#endif /* INTEL_BUFMGR_H */
383