v3d_drm.h revision 01e04c3f
101e04c3fSmrg/*
201e04c3fSmrg * Copyright © 2014-2018 Broadcom
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the next
1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg * Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2101e04c3fSmrg * IN THE SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#ifndef _V3D_DRM_H_
2501e04c3fSmrg#define _V3D_DRM_H_
2601e04c3fSmrg
2701e04c3fSmrg#include "drm.h"
2801e04c3fSmrg
2901e04c3fSmrg#if defined(__cplusplus)
3001e04c3fSmrgextern "C" {
3101e04c3fSmrg#endif
3201e04c3fSmrg
3301e04c3fSmrg#define DRM_V3D_SUBMIT_CL                         0x00
3401e04c3fSmrg#define DRM_V3D_WAIT_BO                           0x01
3501e04c3fSmrg#define DRM_V3D_CREATE_BO                         0x02
3601e04c3fSmrg#define DRM_V3D_MMAP_BO                           0x03
3701e04c3fSmrg#define DRM_V3D_GET_PARAM                         0x04
3801e04c3fSmrg#define DRM_V3D_GET_BO_OFFSET                     0x05
3901e04c3fSmrg
4001e04c3fSmrg#define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
4101e04c3fSmrg#define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
4201e04c3fSmrg#define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
4301e04c3fSmrg#define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
4401e04c3fSmrg#define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
4501e04c3fSmrg#define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
4601e04c3fSmrg
4701e04c3fSmrg/**
4801e04c3fSmrg * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
4901e04c3fSmrg * engine.
5001e04c3fSmrg *
5101e04c3fSmrg * This asks the kernel to have the GPU execute an optional binner
5201e04c3fSmrg * command list, and a render command list.
5301e04c3fSmrg */
5401e04c3fSmrgstruct drm_v3d_submit_cl {
5501e04c3fSmrg	/* Pointer to the binner command list.
5601e04c3fSmrg	 *
5701e04c3fSmrg	 * This is the first set of commands executed, which runs the
5801e04c3fSmrg	 * coordinate shader to determine where primitives land on the screen,
5901e04c3fSmrg	 * then writes out the state updates and draw calls necessary per tile
6001e04c3fSmrg	 * to the tile allocation BO.
6101e04c3fSmrg	 */
6201e04c3fSmrg	__u32 bcl_start;
6301e04c3fSmrg
6401e04c3fSmrg	 /** End address of the BCL (first byte after the BCL) */
6501e04c3fSmrg	__u32 bcl_end;
6601e04c3fSmrg
6701e04c3fSmrg	/* Offset of the render command list.
6801e04c3fSmrg	 *
6901e04c3fSmrg	 * This is the second set of commands executed, which will either
7001e04c3fSmrg	 * execute the tiles that have been set up by the BCL, or a fixed set
7101e04c3fSmrg	 * of tiles (in the case of RCL-only blits).
7201e04c3fSmrg	 */
7301e04c3fSmrg	__u32 rcl_start;
7401e04c3fSmrg
7501e04c3fSmrg	 /** End address of the RCL (first byte after the RCL) */
7601e04c3fSmrg	__u32 rcl_end;
7701e04c3fSmrg
7801e04c3fSmrg	/** An optional sync object to wait on before starting the BCL. */
7901e04c3fSmrg	__u32 in_sync_bcl;
8001e04c3fSmrg	/** An optional sync object to wait on before starting the RCL. */
8101e04c3fSmrg	__u32 in_sync_rcl;
8201e04c3fSmrg	/** An optional sync object to place the completion fence in. */
8301e04c3fSmrg	__u32 out_sync;
8401e04c3fSmrg
8501e04c3fSmrg	/* Offset of the tile alloc memory
8601e04c3fSmrg	 *
8701e04c3fSmrg	 * This is optional on V3D 3.3 (where the CL can set the value) but
8801e04c3fSmrg	 * required on V3D 4.1.
8901e04c3fSmrg	 */
9001e04c3fSmrg	__u32 qma;
9101e04c3fSmrg
9201e04c3fSmrg	/** Size of the tile alloc memory. */
9301e04c3fSmrg	__u32 qms;
9401e04c3fSmrg
9501e04c3fSmrg	/** Offset of the tile state data array. */
9601e04c3fSmrg	__u32 qts;
9701e04c3fSmrg
9801e04c3fSmrg	/* Pointer to a u32 array of the BOs that are referenced by the job.
9901e04c3fSmrg	 */
10001e04c3fSmrg	__u64 bo_handles;
10101e04c3fSmrg
10201e04c3fSmrg	/* Number of BO handles passed in (size is that times 4). */
10301e04c3fSmrg	__u32 bo_handle_count;
10401e04c3fSmrg
10501e04c3fSmrg	/* Pad, must be zero-filled. */
10601e04c3fSmrg	__u32 pad;
10701e04c3fSmrg};
10801e04c3fSmrg
10901e04c3fSmrg/**
11001e04c3fSmrg * struct drm_v3d_wait_bo - ioctl argument for waiting for
11101e04c3fSmrg * completion of the last DRM_V3D_SUBMIT_CL on a BO.
11201e04c3fSmrg *
11301e04c3fSmrg * This is useful for cases where multiple processes might be
11401e04c3fSmrg * rendering to a BO and you want to wait for all rendering to be
11501e04c3fSmrg * completed.
11601e04c3fSmrg */
11701e04c3fSmrgstruct drm_v3d_wait_bo {
11801e04c3fSmrg	__u32 handle;
11901e04c3fSmrg	__u32 pad;
12001e04c3fSmrg	__u64 timeout_ns;
12101e04c3fSmrg};
12201e04c3fSmrg
12301e04c3fSmrg/**
12401e04c3fSmrg * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
12501e04c3fSmrg *
12601e04c3fSmrg * There are currently no values for the flags argument, but it may be
12701e04c3fSmrg * used in a future extension.
12801e04c3fSmrg */
12901e04c3fSmrgstruct drm_v3d_create_bo {
13001e04c3fSmrg	__u32 size;
13101e04c3fSmrg	__u32 flags;
13201e04c3fSmrg	/** Returned GEM handle for the BO. */
13301e04c3fSmrg	__u32 handle;
13401e04c3fSmrg	/**
13501e04c3fSmrg	 * Returned offset for the BO in the V3D address space.  This offset
13601e04c3fSmrg	 * is private to the DRM fd and is valid for the lifetime of the GEM
13701e04c3fSmrg	 * handle.
13801e04c3fSmrg	 *
13901e04c3fSmrg	 * This offset value will always be nonzero, since various HW
14001e04c3fSmrg	 * units treat 0 specially.
14101e04c3fSmrg	 */
14201e04c3fSmrg	__u32 offset;
14301e04c3fSmrg};
14401e04c3fSmrg
14501e04c3fSmrg/**
14601e04c3fSmrg * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
14701e04c3fSmrg *
14801e04c3fSmrg * This doesn't actually perform an mmap.  Instead, it returns the
14901e04c3fSmrg * offset you need to use in an mmap on the DRM device node.  This
15001e04c3fSmrg * means that tools like valgrind end up knowing about the mapped
15101e04c3fSmrg * memory.
15201e04c3fSmrg *
15301e04c3fSmrg * There are currently no values for the flags argument, but it may be
15401e04c3fSmrg * used in a future extension.
15501e04c3fSmrg */
15601e04c3fSmrgstruct drm_v3d_mmap_bo {
15701e04c3fSmrg	/** Handle for the object being mapped. */
15801e04c3fSmrg	__u32 handle;
15901e04c3fSmrg	__u32 flags;
16001e04c3fSmrg	/** offset into the drm node to use for subsequent mmap call. */
16101e04c3fSmrg	__u64 offset;
16201e04c3fSmrg};
16301e04c3fSmrg
16401e04c3fSmrgenum drm_v3d_param {
16501e04c3fSmrg	DRM_V3D_PARAM_V3D_UIFCFG,
16601e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT1,
16701e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT2,
16801e04c3fSmrg	DRM_V3D_PARAM_V3D_HUB_IDENT3,
16901e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
17001e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
17101e04c3fSmrg	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
17201e04c3fSmrg};
17301e04c3fSmrg
17401e04c3fSmrgstruct drm_v3d_get_param {
17501e04c3fSmrg	__u32 param;
17601e04c3fSmrg	__u32 pad;
17701e04c3fSmrg	__u64 value;
17801e04c3fSmrg};
17901e04c3fSmrg
18001e04c3fSmrg/**
18101e04c3fSmrg * Returns the offset for the BO in the V3D address space for this DRM fd.
18201e04c3fSmrg * This is the same value returned by drm_v3d_create_bo, if that was called
18301e04c3fSmrg * from this DRM fd.
18401e04c3fSmrg */
18501e04c3fSmrgstruct drm_v3d_get_bo_offset {
18601e04c3fSmrg	__u32 handle;
18701e04c3fSmrg	__u32 offset;
18801e04c3fSmrg};
18901e04c3fSmrg
19001e04c3fSmrg#if defined(__cplusplus)
19101e04c3fSmrg}
19201e04c3fSmrg#endif
19301e04c3fSmrg
19401e04c3fSmrg#endif /* _V3D_DRM_H_ */
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