1/*
2 * Copyright © 2021 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27#ifndef AC_SURFACE_TEST_COMMON_H
28#define AC_SURFACE_TEST_COMMON_H
29
30#include "ac_gpu_info.h"
31#include "amdgfxregs.h"
32
33typedef void (*gpu_init_func)(struct radeon_info *info);
34
35static void init_vega10(struct radeon_info *info)
36{
37   info->family = CHIP_VEGA10;
38   info->chip_class = GFX9;
39   info->family_id = AMDGPU_FAMILY_AI;
40   info->chip_external_rev = 0x01;
41   info->use_display_dcc_unaligned = false;
42   info->use_display_dcc_with_retile_blit = false;
43   info->has_graphics = true;
44   info->tcc_cache_line_size = 64;
45   info->max_render_backends = 16;
46
47   info->gb_addr_config = 0x2a114042;
48}
49
50static void init_vega20(struct radeon_info *info)
51{
52   info->family = CHIP_VEGA20;
53   info->chip_class = GFX9;
54   info->family_id = AMDGPU_FAMILY_AI;
55   info->chip_external_rev = 0x30;
56   info->use_display_dcc_unaligned = false;
57   info->use_display_dcc_with_retile_blit = false;
58   info->has_graphics = true;
59   info->tcc_cache_line_size = 64;
60   info->max_render_backends = 16;
61
62   info->gb_addr_config = 0x2a114042;
63}
64
65
66static void init_raven(struct radeon_info *info)
67{
68   info->family = CHIP_RAVEN;
69   info->chip_class = GFX9;
70   info->family_id = AMDGPU_FAMILY_RV;
71   info->chip_external_rev = 0x01;
72   info->use_display_dcc_unaligned = false;
73   info->use_display_dcc_with_retile_blit = true;
74   info->has_graphics = true;
75   info->tcc_cache_line_size = 64;
76   info->max_render_backends = 2;
77
78   info->gb_addr_config = 0x24000042;
79}
80
81static void init_raven2(struct radeon_info *info)
82{
83   info->family = CHIP_RAVEN2;
84   info->chip_class = GFX9;
85   info->family_id = AMDGPU_FAMILY_RV;
86   info->chip_external_rev = 0x82;
87   info->use_display_dcc_unaligned = true;
88   info->use_display_dcc_with_retile_blit = false;
89   info->has_graphics = true;
90   info->tcc_cache_line_size = 64;
91   info->max_render_backends = 1;
92
93   info->gb_addr_config = 0x26013041;
94}
95
96static void init_navi10(struct radeon_info *info)
97{
98   info->family = CHIP_NAVI10;
99   info->chip_class = GFX10;
100   info->family_id = AMDGPU_FAMILY_NV;
101   info->chip_external_rev = 3;
102   info->use_display_dcc_unaligned = false;
103   info->use_display_dcc_with_retile_blit = false;
104   info->has_graphics = true;
105   info->tcc_cache_line_size = 128;
106   info->max_render_backends = 16;
107
108   info->gb_addr_config = 0x00100044;
109}
110
111static void init_navi14(struct radeon_info *info)
112{
113   info->family = CHIP_NAVI14;
114   info->chip_class = GFX10;
115   info->family_id = AMDGPU_FAMILY_NV;
116   info->chip_external_rev = 0x15;
117   info->use_display_dcc_unaligned = false;
118   info->use_display_dcc_with_retile_blit = false;
119   info->has_graphics = true;
120   info->tcc_cache_line_size = 128;
121   info->max_render_backends = 8;
122
123   info->gb_addr_config = 0x00000043;
124}
125
126static void init_sienna_cichlid(struct radeon_info *info)
127{
128   info->family = CHIP_SIENNA_CICHLID;
129   info->chip_class = GFX10_3;
130   info->family_id = AMDGPU_FAMILY_NV;
131   info->chip_external_rev = 0x28;
132   info->use_display_dcc_unaligned = false;
133   info->use_display_dcc_with_retile_blit = true;
134   info->has_graphics = true;
135   info->tcc_cache_line_size = 128;
136   info->has_rbplus = true;
137   info->rbplus_allowed = true;
138   info->max_render_backends = 16;
139
140   info->gb_addr_config = 0x00000444;
141}
142
143static void init_navy_flounder(struct radeon_info *info)
144{
145   info->family = CHIP_NAVY_FLOUNDER;
146   info->chip_class = GFX10_3;
147   info->family_id = AMDGPU_FAMILY_NV;
148   info->chip_external_rev = 0x32;
149   info->use_display_dcc_unaligned = false;
150   info->use_display_dcc_with_retile_blit = true;
151   info->has_graphics = true;
152   info->tcc_cache_line_size = 128;
153   info->has_rbplus = true;
154   info->rbplus_allowed = true;
155   info->max_render_backends = 8;
156
157   info->gb_addr_config = 0x00000344;
158}
159
160struct testcase {
161   const char *name;
162   gpu_init_func init;
163   int banks_or_pkrs;
164   int pipes;
165   int se;
166   int rb_per_se;
167};
168
169static struct testcase testcases[] = {
170   {"vega10", init_vega10, 4, 2, 2, 2},
171   {"vega10_diff_bank", init_vega10, 3, 2, 2, 2},
172   {"vega10_diff_rb", init_vega10, 4, 2, 2, 0},
173   {"vega10_diff_pipe", init_vega10, 4, 0, 2, 2},
174   {"vega10_diff_se", init_vega10, 4, 2, 1, 2},
175   {"vega20", init_vega20, 4, 2, 2, 2},
176   {"raven", init_raven, 0, 2, 0, 1},
177   {"raven2", init_raven2, 3, 1, 0, 1},
178   {"navi10", init_navi10, 0, 4, 1, 0},
179   {"navi10_diff_pipe", init_navi10, 0, 3, 1, 0},
180   {"navi10_diff_pkr", init_navi10, 1, 4, 1, 0},
181   {"navi14", init_navi14, 1, 3, 1, 0},
182   {"sienna_cichlid", init_sienna_cichlid},
183   {"navy_flounder", init_navy_flounder},
184};
185
186static struct radeon_info get_radeon_info(struct testcase *testcase)
187{
188   struct radeon_info info = {
189      .drm_major = 3,
190      .drm_minor = 30,
191   };
192
193   testcase->init(&info);
194
195   switch(info.chip_class) {
196   case GFX10_3:
197      break;
198   case GFX10:
199      info.gb_addr_config = (info.gb_addr_config &
200                             C_0098F8_NUM_PIPES &
201                             C_0098F8_NUM_PKRS) |
202                             S_0098F8_NUM_PIPES(testcase->pipes) |
203                             S_0098F8_NUM_PKRS(testcase->banks_or_pkrs);
204      break;
205   case GFX9:
206      info.gb_addr_config = (info.gb_addr_config &
207                             C_0098F8_NUM_PIPES &
208                             C_0098F8_NUM_BANKS &
209                             C_0098F8_NUM_SHADER_ENGINES_GFX9 &
210                             C_0098F8_NUM_RB_PER_SE) |
211                             S_0098F8_NUM_PIPES(testcase->pipes) |
212                             S_0098F8_NUM_BANKS(testcase->banks_or_pkrs) |
213                             S_0098F8_NUM_SHADER_ENGINES_GFX9(testcase->se) |
214                             S_0098F8_NUM_RB_PER_SE(testcase->rb_per_se);
215      break;
216   default:
217      unreachable("Unhandled generation");
218   }
219
220   return info;
221}
222
223#endif
224