ir3_cp.c revision 7e102996
1/* 2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Rob Clark <robclark@freedesktop.org> 25 */ 26 27#include <math.h> 28 29#include "ir3.h" 30#include "ir3_compiler.h" 31#include "ir3_shader.h" 32 33/* 34 * Copy Propagate: 35 */ 36 37struct ir3_cp_ctx { 38 struct ir3 *shader; 39 struct ir3_shader_variant *so; 40 unsigned immediate_idx; 41}; 42 43/* is it a type preserving mov, with ok flags? */ 44static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags) 45{ 46 if (is_same_type_mov(instr)) { 47 struct ir3_register *dst = instr->regs[0]; 48 struct ir3_register *src = instr->regs[1]; 49 struct ir3_instruction *src_instr = ssa(src); 50 51 /* only if mov src is SSA (not const/immed): */ 52 if (!src_instr) 53 return false; 54 55 /* no indirect: */ 56 if (dst->flags & IR3_REG_RELATIV) 57 return false; 58 if (src->flags & IR3_REG_RELATIV) 59 return false; 60 61 if (src->flags & IR3_REG_ARRAY) 62 return false; 63 64 if (!allow_flags) 65 if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG | 66 IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT)) 67 return false; 68 69 /* TODO: remove this hack: */ 70 if (src_instr->opc == OPC_META_FO) 71 return false; 72 73 return true; 74 } 75 return false; 76} 77 78static unsigned cp_flags(unsigned flags) 79{ 80 /* only considering these flags (at least for now): */ 81 flags &= (IR3_REG_CONST | IR3_REG_IMMED | 82 IR3_REG_FNEG | IR3_REG_FABS | 83 IR3_REG_SNEG | IR3_REG_SABS | 84 IR3_REG_BNOT | IR3_REG_RELATIV); 85 return flags; 86} 87 88static bool valid_flags(struct ir3_instruction *instr, unsigned n, 89 unsigned flags) 90{ 91 unsigned valid_flags; 92 93 if ((flags & IR3_REG_HIGH) && 94 (opc_cat(instr->opc) > 1) && 95 (instr->block->shader->compiler->gpu_id >= 600)) 96 return false; 97 98 flags = cp_flags(flags); 99 100 /* If destination is indirect, then source cannot be.. at least 101 * I don't think so.. 102 */ 103 if ((instr->regs[0]->flags & IR3_REG_RELATIV) && 104 (flags & IR3_REG_RELATIV)) 105 return false; 106 107 /* TODO it seems to *mostly* work to cp RELATIV, except we get some 108 * intermittent piglit variable-indexing fails. Newer blob driver 109 * doesn't seem to cp these. Possibly this is hw workaround? Not 110 * sure, but until that is understood better, lets just switch off 111 * cp for indirect src's: 112 */ 113 if (flags & IR3_REG_RELATIV) 114 return false; 115 116 switch (opc_cat(instr->opc)) { 117 case 1: 118 valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV; 119 if (flags & ~valid_flags) 120 return false; 121 break; 122 case 2: 123 valid_flags = ir3_cat2_absneg(instr->opc) | 124 IR3_REG_CONST | IR3_REG_RELATIV; 125 126 if (ir3_cat2_int(instr->opc)) 127 valid_flags |= IR3_REG_IMMED; 128 129 if (flags & ~valid_flags) 130 return false; 131 132 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) { 133 unsigned m = (n ^ 1) + 1; 134 /* cannot deal w/ const in both srcs: 135 * (note that some cat2 actually only have a single src) 136 */ 137 if (m < instr->regs_count) { 138 struct ir3_register *reg = instr->regs[m]; 139 if ((flags & IR3_REG_CONST) && (reg->flags & IR3_REG_CONST)) 140 return false; 141 if ((flags & IR3_REG_IMMED) && (reg->flags & IR3_REG_IMMED)) 142 return false; 143 } 144 /* cannot be const + ABS|NEG: */ 145 if (flags & (IR3_REG_FABS | IR3_REG_FNEG | 146 IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT)) 147 return false; 148 } 149 break; 150 case 3: 151 valid_flags = ir3_cat3_absneg(instr->opc) | 152 IR3_REG_CONST | IR3_REG_RELATIV; 153 154 if (flags & ~valid_flags) 155 return false; 156 157 if (flags & (IR3_REG_CONST | IR3_REG_RELATIV)) { 158 /* cannot deal w/ const/relativ in 2nd src: */ 159 if (n == 1) 160 return false; 161 } 162 163 if (flags & IR3_REG_CONST) { 164 /* cannot be const + ABS|NEG: */ 165 if (flags & (IR3_REG_FABS | IR3_REG_FNEG | 166 IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT)) 167 return false; 168 } 169 break; 170 case 4: 171 /* seems like blob compiler avoids const as src.. */ 172 /* TODO double check if this is still the case on a4xx */ 173 if (flags & (IR3_REG_CONST | IR3_REG_IMMED)) 174 return false; 175 if (flags & (IR3_REG_SABS | IR3_REG_SNEG)) 176 return false; 177 break; 178 case 5: 179 /* no flags allowed */ 180 if (flags) 181 return false; 182 break; 183 case 6: 184 valid_flags = IR3_REG_IMMED; 185 if (flags & ~valid_flags) 186 return false; 187 188 if (flags & IR3_REG_IMMED) { 189 /* doesn't seem like we can have immediate src for store 190 * instructions: 191 * 192 * TODO this restriction could also apply to load instructions, 193 * but for load instructions this arg is the address (and not 194 * really sure any good way to test a hard-coded immed addr src) 195 */ 196 if (is_store(instr) && (n == 1)) 197 return false; 198 199 if ((instr->opc == OPC_LDL) && (n != 1)) 200 return false; 201 202 if ((instr->opc == OPC_STL) && (n != 2)) 203 return false; 204 205 /* disallow CP into anything but the SSBO slot argument for 206 * atomics: 207 */ 208 if (is_atomic(instr->opc) && (n != 0)) 209 return false; 210 211 if (is_atomic(instr->opc) && !(instr->flags & IR3_INSTR_G)) 212 return false; 213 214 /* as with atomics, ldib on a6xx can only have immediate for 215 * SSBO slot argument 216 */ 217 if ((instr->opc == OPC_LDIB) && (n != 0)) 218 return false; 219 } 220 221 break; 222 } 223 224 return true; 225} 226 227/* propagate register flags from src to dst.. negates need special 228 * handling to cancel each other out. 229 */ 230static void combine_flags(unsigned *dstflags, struct ir3_instruction *src) 231{ 232 unsigned srcflags = src->regs[1]->flags; 233 234 /* if what we are combining into already has (abs) flags, 235 * we can drop (neg) from src: 236 */ 237 if (*dstflags & IR3_REG_FABS) 238 srcflags &= ~IR3_REG_FNEG; 239 if (*dstflags & IR3_REG_SABS) 240 srcflags &= ~IR3_REG_SNEG; 241 242 if (srcflags & IR3_REG_FABS) 243 *dstflags |= IR3_REG_FABS; 244 if (srcflags & IR3_REG_SABS) 245 *dstflags |= IR3_REG_SABS; 246 if (srcflags & IR3_REG_FNEG) 247 *dstflags ^= IR3_REG_FNEG; 248 if (srcflags & IR3_REG_SNEG) 249 *dstflags ^= IR3_REG_SNEG; 250 if (srcflags & IR3_REG_BNOT) 251 *dstflags ^= IR3_REG_BNOT; 252 253 *dstflags &= ~IR3_REG_SSA; 254 *dstflags |= srcflags & IR3_REG_SSA; 255 *dstflags |= srcflags & IR3_REG_CONST; 256 *dstflags |= srcflags & IR3_REG_IMMED; 257 *dstflags |= srcflags & IR3_REG_RELATIV; 258 *dstflags |= srcflags & IR3_REG_ARRAY; 259 *dstflags |= srcflags & IR3_REG_HIGH; 260 261 /* if src of the src is boolean we can drop the (abs) since we know 262 * the source value is already a postitive integer. This cleans 263 * up the absnegs that get inserted when converting between nir and 264 * native boolean (see ir3_b2n/n2b) 265 */ 266 struct ir3_instruction *srcsrc = ssa(src->regs[1]); 267 if (srcsrc && is_bool(srcsrc)) 268 *dstflags &= ~IR3_REG_SABS; 269} 270 271static struct ir3_register * 272lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags) 273{ 274 unsigned swiz, idx, i; 275 276 reg = ir3_reg_clone(ctx->shader, reg); 277 278 /* in some cases, there are restrictions on (abs)/(neg) plus const.. 279 * so just evaluate those and clear the flags: 280 */ 281 if (new_flags & IR3_REG_SABS) { 282 reg->iim_val = abs(reg->iim_val); 283 new_flags &= ~IR3_REG_SABS; 284 } 285 286 if (new_flags & IR3_REG_FABS) { 287 reg->fim_val = fabs(reg->fim_val); 288 new_flags &= ~IR3_REG_FABS; 289 } 290 291 if (new_flags & IR3_REG_SNEG) { 292 reg->iim_val = -reg->iim_val; 293 new_flags &= ~IR3_REG_SNEG; 294 } 295 296 if (new_flags & IR3_REG_FNEG) { 297 reg->fim_val = -reg->fim_val; 298 new_flags &= ~IR3_REG_FNEG; 299 } 300 301 /* Reallocate for 4 more elements whenever it's necessary */ 302 if (ctx->immediate_idx == ctx->so->immediates_size * 4) { 303 ctx->so->immediates_size += 4; 304 ctx->so->immediates = realloc (ctx->so->immediates, 305 ctx->so->immediates_size * sizeof (ctx->so->immediates[0])); 306 } 307 308 for (i = 0; i < ctx->immediate_idx; i++) { 309 swiz = i % 4; 310 idx = i / 4; 311 312 if (ctx->so->immediates[idx].val[swiz] == reg->uim_val) { 313 break; 314 } 315 } 316 317 if (i == ctx->immediate_idx) { 318 /* need to generate a new immediate: */ 319 swiz = i % 4; 320 idx = i / 4; 321 ctx->so->immediates[idx].val[swiz] = reg->uim_val; 322 ctx->so->immediates_count = idx + 1; 323 ctx->immediate_idx++; 324 } 325 326 new_flags &= ~IR3_REG_IMMED; 327 new_flags |= IR3_REG_CONST; 328 reg->flags = new_flags; 329 reg->num = i + (4 * ctx->so->constbase.immediate); 330 331 return reg; 332} 333 334static void 335unuse(struct ir3_instruction *instr) 336{ 337 debug_assert(instr->use_count > 0); 338 339 if (--instr->use_count == 0) { 340 struct ir3_block *block = instr->block; 341 342 instr->barrier_class = 0; 343 instr->barrier_conflict = 0; 344 345 /* we don't want to remove anything in keeps (which could 346 * be things like array store's) 347 */ 348 for (unsigned i = 0; i < block->keeps_count; i++) { 349 debug_assert(block->keeps[i] != instr); 350 } 351 } 352} 353 354/** 355 * Handle cp for a given src register. This additionally handles 356 * the cases of collapsing immedate/const (which replace the src 357 * register with a non-ssa src) or collapsing mov's from relative 358 * src (which needs to also fixup the address src reference by the 359 * instruction). 360 */ 361static void 362reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, 363 struct ir3_register *reg, unsigned n) 364{ 365 struct ir3_instruction *src = ssa(reg); 366 367 if (is_eligible_mov(src, true)) { 368 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */ 369 struct ir3_register *src_reg = src->regs[1]; 370 unsigned new_flags = reg->flags; 371 372 combine_flags(&new_flags, src); 373 374 if (valid_flags(instr, n, new_flags)) { 375 if (new_flags & IR3_REG_ARRAY) { 376 debug_assert(!(reg->flags & IR3_REG_ARRAY)); 377 reg->array = src_reg->array; 378 } 379 reg->flags = new_flags; 380 reg->instr = ssa(src_reg); 381 382 instr->barrier_class |= src->barrier_class; 383 instr->barrier_conflict |= src->barrier_conflict; 384 385 unuse(src); 386 reg->instr->use_count++; 387 } 388 389 } else if (is_same_type_mov(src) && 390 /* cannot collapse const/immed/etc into meta instrs: */ 391 !is_meta(instr)) { 392 /* immed/const/etc cases, which require some special handling: */ 393 struct ir3_register *src_reg = src->regs[1]; 394 unsigned new_flags = reg->flags; 395 396 combine_flags(&new_flags, src); 397 398 if (!valid_flags(instr, n, new_flags)) { 399 /* See if lowering an immediate to const would help. */ 400 if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) { 401 debug_assert(new_flags & IR3_REG_IMMED); 402 instr->regs[n + 1] = lower_immed(ctx, src_reg, new_flags); 403 return; 404 } 405 406 /* special case for "normal" mad instructions, we can 407 * try swapping the first two args if that fits better. 408 * 409 * the "plain" MAD's (ie. the ones that don't shift first 410 * src prior to multiply) can swap their first two srcs if 411 * src[0] is !CONST and src[1] is CONST: 412 */ 413 if ((n == 1) && is_mad(instr->opc) && 414 !(instr->regs[0 + 1]->flags & (IR3_REG_CONST | IR3_REG_RELATIV)) && 415 valid_flags(instr, 0, new_flags & ~IR3_REG_IMMED)) { 416 /* swap src[0] and src[1]: */ 417 struct ir3_register *tmp; 418 tmp = instr->regs[0 + 1]; 419 instr->regs[0 + 1] = instr->regs[1 + 1]; 420 instr->regs[1 + 1] = tmp; 421 422 n = 0; 423 } else { 424 return; 425 } 426 } 427 428 /* Here we handle the special case of mov from 429 * CONST and/or RELATIV. These need to be handled 430 * specially, because in the case of move from CONST 431 * there is no src ir3_instruction so we need to 432 * replace the ir3_register. And in the case of 433 * RELATIV we need to handle the address register 434 * dependency. 435 */ 436 if (src_reg->flags & IR3_REG_CONST) { 437 /* an instruction cannot reference two different 438 * address registers: 439 */ 440 if ((src_reg->flags & IR3_REG_RELATIV) && 441 conflicts(instr->address, reg->instr->address)) 442 return; 443 444 /* This seems to be a hw bug, or something where the timings 445 * just somehow don't work out. This restriction may only 446 * apply if the first src is also CONST. 447 */ 448 if ((opc_cat(instr->opc) == 3) && (n == 2) && 449 (src_reg->flags & IR3_REG_RELATIV) && 450 (src_reg->array.offset == 0)) 451 return; 452 453 src_reg = ir3_reg_clone(instr->block->shader, src_reg); 454 src_reg->flags = new_flags; 455 instr->regs[n+1] = src_reg; 456 457 if (src_reg->flags & IR3_REG_RELATIV) 458 ir3_instr_set_address(instr, reg->instr->address); 459 460 return; 461 } 462 463 if ((src_reg->flags & IR3_REG_RELATIV) && 464 !conflicts(instr->address, reg->instr->address)) { 465 src_reg = ir3_reg_clone(instr->block->shader, src_reg); 466 src_reg->flags = new_flags; 467 instr->regs[n+1] = src_reg; 468 ir3_instr_set_address(instr, reg->instr->address); 469 470 return; 471 } 472 473 /* NOTE: seems we can only do immed integers, so don't 474 * need to care about float. But we do need to handle 475 * abs/neg *before* checking that the immediate requires 476 * few enough bits to encode: 477 * 478 * TODO: do we need to do something to avoid accidentally 479 * catching a float immed? 480 */ 481 if (src_reg->flags & IR3_REG_IMMED) { 482 int32_t iim_val = src_reg->iim_val; 483 484 debug_assert((opc_cat(instr->opc) == 1) || 485 (opc_cat(instr->opc) == 6) || 486 ir3_cat2_int(instr->opc) || 487 (is_mad(instr->opc) && (n == 0))); 488 489 if (new_flags & IR3_REG_SABS) 490 iim_val = abs(iim_val); 491 492 if (new_flags & IR3_REG_SNEG) 493 iim_val = -iim_val; 494 495 if (new_flags & IR3_REG_BNOT) 496 iim_val = ~iim_val; 497 498 /* other than category 1 (mov) we can only encode up to 10 bits: */ 499 if ((instr->opc == OPC_MOV) || 500 !((iim_val & ~0x3ff) && (-iim_val & ~0x3ff))) { 501 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT); 502 src_reg = ir3_reg_clone(instr->block->shader, src_reg); 503 src_reg->flags = new_flags; 504 src_reg->iim_val = iim_val; 505 instr->regs[n+1] = src_reg; 506 } else if (valid_flags(instr, n, (new_flags & ~IR3_REG_IMMED) | IR3_REG_CONST)) { 507 /* See if lowering an immediate to const would help. */ 508 instr->regs[n+1] = lower_immed(ctx, src_reg, new_flags); 509 } 510 511 return; 512 } 513 } 514} 515 516/* Handle special case of eliminating output mov, and similar cases where 517 * there isn't a normal "consuming" instruction. In this case we cannot 518 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot 519 * be eliminated) 520 */ 521static struct ir3_instruction * 522eliminate_output_mov(struct ir3_instruction *instr) 523{ 524 if (is_eligible_mov(instr, false)) { 525 struct ir3_register *reg = instr->regs[1]; 526 if (!(reg->flags & IR3_REG_ARRAY)) { 527 struct ir3_instruction *src_instr = ssa(reg); 528 debug_assert(src_instr); 529 return src_instr; 530 } 531 } 532 return instr; 533} 534 535/** 536 * Find instruction src's which are mov's that can be collapsed, replacing 537 * the mov dst with the mov src 538 */ 539static void 540instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr) 541{ 542 struct ir3_register *reg; 543 544 if (instr->regs_count == 0) 545 return; 546 547 if (ir3_instr_check_mark(instr)) 548 return; 549 550 /* walk down the graph from each src: */ 551 foreach_src_n(reg, n, instr) { 552 struct ir3_instruction *src = ssa(reg); 553 554 if (!src) 555 continue; 556 557 instr_cp(ctx, src); 558 559 /* TODO non-indirect access we could figure out which register 560 * we actually want and allow cp.. 561 */ 562 if (reg->flags & IR3_REG_ARRAY) 563 continue; 564 565 /* Don't CP absneg into meta instructions, that won't end well: */ 566 if (is_meta(instr) && (src->opc != OPC_MOV)) 567 continue; 568 569 reg_cp(ctx, instr, reg, n); 570 } 571 572 if (instr->regs[0]->flags & IR3_REG_ARRAY) { 573 struct ir3_instruction *src = ssa(instr->regs[0]); 574 if (src) 575 instr_cp(ctx, src); 576 } 577 578 if (instr->address) { 579 instr_cp(ctx, instr->address); 580 ir3_instr_set_address(instr, eliminate_output_mov(instr->address)); 581 } 582 583 /* we can end up with extra cmps.s from frontend, which uses a 584 * 585 * cmps.s p0.x, cond, 0 586 * 587 * as a way to mov into the predicate register. But frequently 'cond' 588 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and 589 * just re-write the instruction writing predicate register to get rid 590 * of the double cmps. 591 */ 592 if ((instr->opc == OPC_CMPS_S) && 593 (instr->regs[0]->num == regid(REG_P0, 0)) && 594 ssa(instr->regs[1]) && 595 (instr->regs[2]->flags & IR3_REG_IMMED) && 596 (instr->regs[2]->iim_val == 0)) { 597 struct ir3_instruction *cond = ssa(instr->regs[1]); 598 switch (cond->opc) { 599 case OPC_CMPS_S: 600 case OPC_CMPS_F: 601 case OPC_CMPS_U: 602 instr->opc = cond->opc; 603 instr->flags = cond->flags; 604 instr->cat2 = cond->cat2; 605 instr->address = cond->address; 606 instr->regs[1] = cond->regs[1]; 607 instr->regs[2] = cond->regs[2]; 608 instr->barrier_class |= cond->barrier_class; 609 instr->barrier_conflict |= cond->barrier_conflict; 610 unuse(cond); 611 break; 612 default: 613 break; 614 } 615 } 616 617 /* Handle converting a sam.s2en (taking samp/tex idx params via 618 * register) into a normal sam (encoding immediate samp/tex idx) 619 * if they are immediate. This saves some instructions and regs 620 * in the common case where we know samp/tex at compile time: 621 */ 622 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) && 623 !(ir3_shader_debug & IR3_DBG_FORCES2EN)) { 624 /* The first src will be a fan-in (collect), if both of it's 625 * two sources are mov from imm, then we can 626 */ 627 struct ir3_instruction *samp_tex = ssa(instr->regs[1]); 628 629 debug_assert(samp_tex->opc == OPC_META_FI); 630 631 struct ir3_instruction *samp = ssa(samp_tex->regs[1]); 632 struct ir3_instruction *tex = ssa(samp_tex->regs[2]); 633 634 if ((samp->opc == OPC_MOV) && 635 (samp->regs[1]->flags & IR3_REG_IMMED) && 636 (tex->opc == OPC_MOV) && 637 (tex->regs[1]->flags & IR3_REG_IMMED)) { 638 instr->flags &= ~IR3_INSTR_S2EN; 639 instr->cat5.samp = samp->regs[1]->iim_val; 640 instr->cat5.tex = tex->regs[1]->iim_val; 641 instr->regs[1]->instr = NULL; 642 } 643 } 644} 645 646void 647ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so) 648{ 649 struct ir3_cp_ctx ctx = { 650 .shader = ir, 651 .so = so, 652 }; 653 654 /* This is a bit annoying, and probably wouldn't be necessary if we 655 * tracked a reverse link from producing instruction to consumer. 656 * But we need to know when we've eliminated the last consumer of 657 * a mov, so we need to do a pass to first count consumers of a 658 * mov. 659 */ 660 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { 661 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { 662 struct ir3_instruction *src; 663 664 /* by the way, we don't account for false-dep's, so the CP 665 * pass should always happen before false-dep's are inserted 666 */ 667 debug_assert(instr->deps_count == 0); 668 669 foreach_ssa_src(src, instr) { 670 src->use_count++; 671 } 672 } 673 } 674 675 ir3_clear_mark(ir); 676 677 for (unsigned i = 0; i < ir->noutputs; i++) { 678 if (ir->outputs[i]) { 679 instr_cp(&ctx, ir->outputs[i]); 680 ir->outputs[i] = eliminate_output_mov(ir->outputs[i]); 681 } 682 } 683 684 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { 685 if (block->condition) { 686 instr_cp(&ctx, block->condition); 687 block->condition = eliminate_output_mov(block->condition); 688 } 689 690 for (unsigned i = 0; i < block->keeps_count; i++) { 691 instr_cp(&ctx, block->keeps[i]); 692 block->keeps[i] = eliminate_output_mov(block->keeps[i]); 693 } 694 } 695} 696