1/*
2 * Copyright © 2021 Google, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24#ifndef TU_PERFETTO_H_
25#define TU_PERFETTO_H_
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31#ifdef HAVE_PERFETTO
32
33/**
34 * Render-stage id's
35 */
36enum tu_stage_id {
37   SURFACE_STAGE_ID, /* Surface is a sort of meta-stage for render-target info */
38   BINNING_STAGE_ID,
39   GMEM_STAGE_ID,
40   BYPASS_STAGE_ID,
41   BLIT_STAGE_ID,
42   COMPUTE_STAGE_ID,
43   CLEAR_SYSMEM_STAGE_ID,
44   CLEAR_GMEM_STAGE_ID,
45   GMEM_LOAD_STAGE_ID,
46   GMEM_STORE_STAGE_ID,
47   SYSMEM_RESOLVE_STAGE_ID,
48   // TODO add the rest
49
50   NUM_STAGES
51};
52
53static const struct {
54   const char *name;
55   const char *desc;
56} stages[] = {
57   [SURFACE_STAGE_ID] = {"Surface"},
58   [BINNING_STAGE_ID] = {"Binning", "Perform Visibility pass and determine target bins"},
59   [GMEM_STAGE_ID]    = {"Render", "Rendering to GMEM"},
60   [BYPASS_STAGE_ID]  = {"Render", "Rendering to system memory"},
61   [BLIT_STAGE_ID]    = {"Blit", "Performing a Blit operation"},
62   [COMPUTE_STAGE_ID] = {"Compute", "Compute job"},
63   [CLEAR_SYSMEM_STAGE_ID] = {"Clear Sysmem", ""},
64   [CLEAR_GMEM_STAGE_ID] = {"Clear GMEM", "Per-tile (GMEM) clear"},
65   [GMEM_LOAD_STAGE_ID] = {"GMEM Load", "Per tile system memory to GMEM load"},
66   [GMEM_STORE_STAGE_ID] = {"GMEM Store", "Per tile GMEM to system memory store"},
67   [SYSMEM_RESOLVE_STAGE_ID] = {"SysMem Resolve", "System memory MSAA resolve"},
68   // TODO add the rest
69};
70
71/**
72 * Queue-id's
73 */
74enum {
75   DEFAULT_HW_QUEUE_ID,
76};
77
78static const struct {
79   const char *name;
80   const char *desc;
81} queues[] = {
82   [DEFAULT_HW_QUEUE_ID] = {"GPU Queue 0", "Default Adreno Hardware Queue"},
83};
84
85struct tu_perfetto_state {
86   uint64_t start_ts[NUM_STAGES];
87};
88
89void tu_perfetto_init(void);
90
91struct tu_device;
92void tu_perfetto_submit(struct tu_device *dev, uint32_t submission_id);
93
94/* Helpers */
95
96struct tu_perfetto_state *
97tu_device_get_perfetto_state(struct tu_device *dev);
98
99int
100tu_device_get_timestamp(struct tu_device *dev,
101                        uint64_t *ts);
102
103uint64_t
104tu_device_ticks_to_ns(struct tu_device *dev, uint64_t ts);
105
106struct tu_u_trace_flush_data;
107uint32_t
108tu_u_trace_flush_data_get_submit_id(const struct tu_u_trace_flush_data *data);
109
110#endif
111
112#ifdef __cplusplus
113}
114#endif
115
116#endif /* TU_PERFETTO_H_ */
117