etnaviv_screen.c revision 01e04c3f
1/* 2 * Copyright (c) 2012-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Wladimir J. van der Laan <laanwj@gmail.com> 25 * Christian Gmeiner <christian.gmeiner@gmail.com> 26 */ 27 28#include "etnaviv_screen.h" 29 30#include "hw/common.xml.h" 31 32#include "etnaviv_compiler.h" 33#include "etnaviv_context.h" 34#include "etnaviv_debug.h" 35#include "etnaviv_fence.h" 36#include "etnaviv_format.h" 37#include "etnaviv_query.h" 38#include "etnaviv_resource.h" 39#include "etnaviv_translate.h" 40 41#include "util/os_time.h" 42#include "util/u_math.h" 43#include "util/u_memory.h" 44#include "util/u_screen.h" 45#include "util/u_string.h" 46 47#include "state_tracker/drm_driver.h" 48 49#include <drm_fourcc.h> 50 51#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor)) 52#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) 53#define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2) 54 55static const struct debug_named_value debug_options[] = { 56 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, 57 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, 58 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"}, 59 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"}, 60 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"}, 61 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"}, 62 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"}, 63 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"}, 64 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"}, 65 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"}, 66 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"}, 67 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"}, 68 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"}, 69 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, 70 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, 71 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, 72 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, 73 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"}, 74 DEBUG_NAMED_VALUE_END 75}; 76 77DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0) 78int etna_mesa_debug = 0; 79 80static void 81etna_screen_destroy(struct pipe_screen *pscreen) 82{ 83 struct etna_screen *screen = etna_screen(pscreen); 84 85 if (screen->perfmon) 86 etna_perfmon_del(screen->perfmon); 87 88 if (screen->pipe) 89 etna_pipe_del(screen->pipe); 90 91 if (screen->gpu) 92 etna_gpu_del(screen->gpu); 93 94 if (screen->ro) 95 FREE(screen->ro); 96 97 if (screen->dev) 98 etna_device_del(screen->dev); 99 100 FREE(screen); 101} 102 103static const char * 104etna_screen_get_name(struct pipe_screen *pscreen) 105{ 106 struct etna_screen *priv = etna_screen(pscreen); 107 static char buffer[128]; 108 109 util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model, 110 priv->revision); 111 112 return buffer; 113} 114 115static const char * 116etna_screen_get_vendor(struct pipe_screen *pscreen) 117{ 118 return "etnaviv"; 119} 120 121static const char * 122etna_screen_get_device_vendor(struct pipe_screen *pscreen) 123{ 124 return "Vivante"; 125} 126 127static int 128etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 129{ 130 struct etna_screen *screen = etna_screen(pscreen); 131 132 switch (param) { 133 /* Supported features (boolean caps). */ 134 case PIPE_CAP_ANISOTROPIC_FILTER: 135 case PIPE_CAP_POINT_SPRITE: 136 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 137 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 138 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 139 case PIPE_CAP_SM3: 140 case PIPE_CAP_TEXTURE_BARRIER: 141 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 142 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 143 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 144 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 145 case PIPE_CAP_TGSI_TEXCOORD: 146 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 147 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 148 return 1; 149 case PIPE_CAP_NATIVE_FENCE_FD: 150 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; 151 152 /* Memory */ 153 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 154 return 256; 155 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 156 return 4; /* XXX could easily be supported */ 157 case PIPE_CAP_GLSL_FEATURE_LEVEL: 158 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 159 return 120; 160 161 case PIPE_CAP_NPOT_TEXTURES: 162 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, 163 NON_POWER_OF_TWO); */ 164 165 case PIPE_CAP_TEXTURE_SWIZZLE: 166 case PIPE_CAP_PRIMITIVE_RESTART: 167 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 168 169 case PIPE_CAP_ENDIANNESS: 170 return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature 171 ENDIANNESS_CONFIG) */ 172 173 /* Unsupported features. */ 174 case PIPE_CAP_SEAMLESS_CUBE_MAP: 175 case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */ 176 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */ 177 case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */ 178 case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */ 179 case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */ 180 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */ 181 case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */ 182 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */ 183 case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */ 184 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */ 185 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: /* only mirrored repeat */ 186 case PIPE_CAP_INDEP_BLEND_ENABLE: 187 case PIPE_CAP_INDEP_BLEND_FUNC: 188 case PIPE_CAP_DEPTH_CLIP_DISABLE: 189 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 190 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 191 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 192 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 193 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */ 194 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 195 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 196 case PIPE_CAP_USER_VERTEX_BUFFERS: 197 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 199 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: 200 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */ 201 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 202 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 203 case PIPE_CAP_TEXTURE_GATHER_SM5: 204 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 205 case PIPE_CAP_FAKE_SW_MSAA: 206 case PIPE_CAP_TEXTURE_QUERY_LOD: 207 case PIPE_CAP_SAMPLE_SHADING: 208 case PIPE_CAP_TEXTURE_GATHER_OFFSETS: 209 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 210 case PIPE_CAP_DRAW_INDIRECT: 211 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 212 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 213 case PIPE_CAP_SAMPLER_VIEW_TARGET: 214 case PIPE_CAP_CLIP_HALFZ: 215 case PIPE_CAP_VERTEXID_NOBASE: 216 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 217 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 218 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 219 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 220 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 221 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 222 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 223 case PIPE_CAP_DEPTH_BOUNDS_TEST: 224 case PIPE_CAP_TGSI_TXQS: 225 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 226 case PIPE_CAP_SHAREABLE_SHADERS: 227 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 228 case PIPE_CAP_CLEAR_TEXTURE: 229 case PIPE_CAP_DRAW_PARAMETERS: 230 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 231 case PIPE_CAP_MULTI_DRAW_INDIRECT: 232 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 233 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 234 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 235 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 236 case PIPE_CAP_INVALIDATE_BUFFER: 237 case PIPE_CAP_GENERATE_MIPMAP: 238 case PIPE_CAP_STRING_MARKER: 239 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 240 case PIPE_CAP_QUERY_BUFFER_OBJECT: 241 case PIPE_CAP_QUERY_MEMORY_INFO: 242 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 243 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 244 case PIPE_CAP_CULL_DISTANCE: 245 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: 246 case PIPE_CAP_TGSI_VOTE: 247 case PIPE_CAP_MAX_WINDOW_RECTANGLES: 248 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: 249 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: 250 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 251 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 252 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: 253 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: 254 case PIPE_CAP_TGSI_FS_FBFETCH: 255 case PIPE_CAP_TGSI_MUL_ZERO_WINS: 256 case PIPE_CAP_DOUBLES: 257 case PIPE_CAP_INT64: 258 case PIPE_CAP_INT64_DIVMOD: 259 case PIPE_CAP_TGSI_TEX_TXF_LZ: 260 case PIPE_CAP_TGSI_CLOCK: 261 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: 262 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: 263 case PIPE_CAP_TGSI_BALLOT: 264 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 265 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: 266 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: 267 case PIPE_CAP_POST_DEPTH_COVERAGE: 268 case PIPE_CAP_BINDLESS_TEXTURE: 269 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: 270 case PIPE_CAP_QUERY_SO_OVERFLOW: 271 case PIPE_CAP_MEMOBJ: 272 case PIPE_CAP_LOAD_CONSTBUF: 273 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: 274 case PIPE_CAP_TILE_RASTER_ORDER: 275 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: 276 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: 277 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 278 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 279 case PIPE_CAP_FENCE_SIGNAL: 280 case PIPE_CAP_CONSTBUF0_FLAGS: 281 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: 282 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: 283 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: 284 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: 285 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: 286 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: 287 case PIPE_CAP_PACKED_UNIFORMS: 288 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: 289 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: 290 return 0; 291 292 case PIPE_CAP_MAX_GS_INVOCATIONS: 293 return 32; 294 295 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: 296 return 1 << 27; 297 298 /* Stream output. */ 299 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 300 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 301 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 302 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 303 return 0; 304 305 /* Geometry shader output, unsupported. */ 306 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 307 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 308 case PIPE_CAP_MAX_VERTEX_STREAMS: 309 return 0; 310 311 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: 312 return 128; 313 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET: 314 return 255; 315 316 /* Texturing. */ 317 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 318 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 319 { 320 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size); 321 assert(log2_max_tex_size > 0); 322 return log2_max_tex_size; 323 } 324 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */ 325 return 5; 326 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 327 return 0; 328 case PIPE_CAP_CUBE_MAP_ARRAY: 329 return 0; 330 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 331 case PIPE_CAP_MIN_TEXEL_OFFSET: 332 return -8; 333 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 334 case PIPE_CAP_MAX_TEXEL_OFFSET: 335 return 7; 336 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: 337 return 0; 338 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 339 return 65536; 340 341 /* Render targets. */ 342 case PIPE_CAP_MAX_RENDER_TARGETS: 343 return 1; 344 345 /* Viewports and scissors. */ 346 case PIPE_CAP_MAX_VIEWPORTS: 347 return 1; 348 349 /* Timer queries. */ 350 case PIPE_CAP_QUERY_TIME_ELAPSED: 351 return 0; 352 case PIPE_CAP_OCCLUSION_QUERY: 353 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 354 case PIPE_CAP_QUERY_TIMESTAMP: 355 return 1; 356 case PIPE_CAP_QUERY_PIPELINE_STATISTICS: 357 return 0; 358 359 /* Preferences */ 360 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 361 return 0; 362 363 case PIPE_CAP_PCI_GROUP: 364 case PIPE_CAP_PCI_BUS: 365 case PIPE_CAP_PCI_DEVICE: 366 case PIPE_CAP_PCI_FUNCTION: 367 return 0; 368 case PIPE_CAP_VENDOR_ID: 369 case PIPE_CAP_DEVICE_ID: 370 return 0xFFFFFFFF; 371 case PIPE_CAP_ACCELERATED: 372 return 1; 373 case PIPE_CAP_VIDEO_MEMORY: 374 return 0; 375 case PIPE_CAP_UMA: 376 return 1; 377 default: 378 return u_pipe_screen_get_param_defaults(pscreen, param); 379 } 380} 381 382static float 383etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 384{ 385 struct etna_screen *screen = etna_screen(pscreen); 386 387 switch (param) { 388 case PIPE_CAPF_MAX_LINE_WIDTH: 389 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 390 case PIPE_CAPF_MAX_POINT_WIDTH: 391 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 392 return 8192.0f; 393 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 394 return 16.0f; 395 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 396 return util_last_bit(screen->specs.max_texture_size); 397 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 398 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 399 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 400 return 0.0f; 401 } 402 403 debug_printf("unknown paramf %d", param); 404 return 0; 405} 406 407static int 408etna_screen_get_shader_param(struct pipe_screen *pscreen, 409 enum pipe_shader_type shader, 410 enum pipe_shader_cap param) 411{ 412 struct etna_screen *screen = etna_screen(pscreen); 413 414 switch (shader) { 415 case PIPE_SHADER_FRAGMENT: 416 case PIPE_SHADER_VERTEX: 417 break; 418 case PIPE_SHADER_COMPUTE: 419 case PIPE_SHADER_GEOMETRY: 420 case PIPE_SHADER_TESS_CTRL: 421 case PIPE_SHADER_TESS_EVAL: 422 return 0; 423 default: 424 DBG("unknown shader type %d", shader); 425 return 0; 426 } 427 428 switch (param) { 429 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 430 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 431 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 432 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 433 return ETNA_MAX_TOKENS; 434 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 435 return ETNA_MAX_DEPTH; /* XXX */ 436 case PIPE_SHADER_CAP_MAX_INPUTS: 437 /* Maximum number of inputs for the vertex shader is the number 438 * of vertex elements - each element defines one vertex shader 439 * input register. For the fragment shader, this is the number 440 * of varyings. */ 441 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings 442 : screen->specs.vertex_max_elements; 443 case PIPE_SHADER_CAP_MAX_OUTPUTS: 444 return 16; /* see VIVS_VS_OUTPUT */ 445 case PIPE_SHADER_CAP_MAX_TEMPS: 446 return 64; /* Max native temporaries. */ 447 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 448 return 1; 449 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 450 return 1; 451 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 452 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 453 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 454 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 455 return 1; 456 case PIPE_SHADER_CAP_SUBROUTINES: 457 return 0; 458 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 459 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 460 case PIPE_SHADER_CAP_INTEGERS: 461 case PIPE_SHADER_CAP_INT64_ATOMICS: 462 case PIPE_SHADER_CAP_FP16: 463 return 0; 464 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 465 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 466 return shader == PIPE_SHADER_FRAGMENT 467 ? screen->specs.fragment_sampler_count 468 : screen->specs.vertex_sampler_count; 469 case PIPE_SHADER_CAP_PREFERRED_IR: 470 return PIPE_SHADER_IR_TGSI; 471 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 472 return 4096; 473 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 474 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 475 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 476 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 477 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 478 return false; 479 case PIPE_SHADER_CAP_SUPPORTED_IRS: 480 return 0; 481 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 482 return 32; 483 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 484 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 485 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 486 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 487 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 488 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 489 case PIPE_SHADER_CAP_SCALAR_ISA: 490 return 0; 491 } 492 493 debug_printf("unknown shader param %d", param); 494 return 0; 495} 496 497static uint64_t 498etna_screen_get_timestamp(struct pipe_screen *pscreen) 499{ 500 return os_time_get_nano(); 501} 502 503static bool 504gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt, 505 enum pipe_format format) 506{ 507 bool supported = true; 508 509 if (fmt == TEXTURE_FORMAT_ETC1) 510 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION); 511 512 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5) 513 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION); 514 515 if (util_format_is_srgb(format)) 516 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 517 518 if (fmt & EXT_FORMAT) { 519 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 520 521 /* ETC1 is checked above, as it has its own feature bit. ETC2 is 522 * supported with HALTI0, however that implementation is buggy in hardware. 523 * The blob driver does per-block patching to work around this. As this 524 * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000) 525 * only. 526 */ 527 if (util_format_is_etc(format)) 528 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1); 529 } 530 531 if (fmt & ASTC_FORMAT) { 532 supported = screen->specs.tex_astc; 533 } 534 535 if (!supported) 536 return false; 537 538 if (texture_format_needs_swiz(format)) 539 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0); 540 541 return true; 542} 543 544static boolean 545etna_screen_is_format_supported(struct pipe_screen *pscreen, 546 enum pipe_format format, 547 enum pipe_texture_target target, 548 unsigned sample_count, 549 unsigned storage_sample_count, 550 unsigned usage) 551{ 552 struct etna_screen *screen = etna_screen(pscreen); 553 unsigned allowed = 0; 554 555 if (target != PIPE_BUFFER && 556 target != PIPE_TEXTURE_1D && 557 target != PIPE_TEXTURE_2D && 558 target != PIPE_TEXTURE_3D && 559 target != PIPE_TEXTURE_CUBE && 560 target != PIPE_TEXTURE_RECT) 561 return FALSE; 562 563 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count)) 564 return false; 565 566 if (usage & PIPE_BIND_RENDER_TARGET) { 567 /* if render target, must be RS-supported format */ 568 if (translate_rs_format(format) != ETNA_NO_MATCH) { 569 /* Validate MSAA; number of samples must be allowed, and render target 570 * must have MSAA'able format. */ 571 if (sample_count > 1) { 572 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) && 573 translate_msaa_format(format) != ETNA_NO_MATCH) { 574 allowed |= PIPE_BIND_RENDER_TARGET; 575 } 576 } else { 577 allowed |= PIPE_BIND_RENDER_TARGET; 578 } 579 } 580 } 581 582 if (usage & PIPE_BIND_DEPTH_STENCIL) { 583 if (translate_depth_format(format) != ETNA_NO_MATCH) 584 allowed |= PIPE_BIND_DEPTH_STENCIL; 585 } 586 587 if (usage & PIPE_BIND_SAMPLER_VIEW) { 588 uint32_t fmt = translate_texture_format(format); 589 590 if (!gpu_supports_texure_format(screen, fmt, format)) 591 fmt = ETNA_NO_MATCH; 592 593 if (sample_count < 2 && fmt != ETNA_NO_MATCH) 594 allowed |= PIPE_BIND_SAMPLER_VIEW; 595 } 596 597 if (usage & PIPE_BIND_VERTEX_BUFFER) { 598 if (translate_vertex_format_type(format) != ETNA_NO_MATCH) 599 allowed |= PIPE_BIND_VERTEX_BUFFER; 600 } 601 602 if (usage & PIPE_BIND_INDEX_BUFFER) { 603 /* must be supported index format */ 604 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT || 605 (format == PIPE_FORMAT_I32_UINT && 606 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) { 607 allowed |= PIPE_BIND_INDEX_BUFFER; 608 } 609 } 610 611 /* Always allowed */ 612 allowed |= 613 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED); 614 615 if (usage != allowed) { 616 DBG("not supported: format=%s, target=%d, sample_count=%d, " 617 "usage=%x, allowed=%x", 618 util_format_name(format), target, sample_count, usage, allowed); 619 } 620 621 return usage == allowed; 622} 623 624const uint64_t supported_modifiers[] = { 625 DRM_FORMAT_MOD_LINEAR, 626 DRM_FORMAT_MOD_VIVANTE_TILED, 627 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED, 628 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED, 629 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED, 630}; 631 632static void 633etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen, 634 enum pipe_format format, int max, 635 uint64_t *modifiers, 636 unsigned int *external_only, int *count) 637{ 638 struct etna_screen *screen = etna_screen(pscreen); 639 int i, num_modifiers = 0; 640 641 if (max > ARRAY_SIZE(supported_modifiers)) 642 max = ARRAY_SIZE(supported_modifiers); 643 644 if (!max) { 645 modifiers = NULL; 646 max = ARRAY_SIZE(supported_modifiers); 647 } 648 649 for (i = 0; num_modifiers < max; i++) { 650 /* don't advertise split tiled formats on single pipe/buffer GPUs */ 651 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) && 652 i >= 3) 653 break; 654 655 if (modifiers) 656 modifiers[num_modifiers] = supported_modifiers[i]; 657 if (external_only) 658 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0; 659 num_modifiers++; 660 } 661 662 *count = num_modifiers; 663} 664 665static boolean 666etna_get_specs(struct etna_screen *screen) 667{ 668 uint64_t val; 669 uint32_t instruction_count; 670 671 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { 672 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); 673 goto fail; 674 } 675 instruction_count = val; 676 677 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, 678 &val)) { 679 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); 680 goto fail; 681 } 682 screen->specs.vertex_output_buffer_size = val; 683 684 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { 685 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); 686 goto fail; 687 } 688 screen->specs.vertex_cache_size = val; 689 690 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { 691 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); 692 goto fail; 693 } 694 screen->specs.shader_core_count = val; 695 696 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { 697 DBG("could not get ETNA_GPU_STREAM_COUNT"); 698 goto fail; 699 } 700 screen->specs.stream_count = val; 701 702 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { 703 DBG("could not get ETNA_GPU_REGISTER_MAX"); 704 goto fail; 705 } 706 screen->specs.max_registers = val; 707 708 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { 709 DBG("could not get ETNA_GPU_PIXEL_PIPES"); 710 goto fail; 711 } 712 screen->specs.pixel_pipes = val; 713 714 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { 715 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); 716 goto fail; 717 } 718 if (val == 0) { 719 fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); 720 val = 168; 721 } 722 screen->specs.num_constants = val; 723 724 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific 725 * description of the differences. */ 726 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) 727 screen->specs.halti = 5; /* New GC7000/GC8x00 */ 728 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) 729 screen->specs.halti = 4; /* Old GC7000/GC7400 */ 730 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) 731 screen->specs.halti = 3; /* None? */ 732 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) 733 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ 734 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) 735 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ 736 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) 737 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ 738 else 739 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ 740 if (screen->specs.halti >= 0) 741 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); 742 else 743 DBG("etnaviv: GPU arch: pre-HALTI"); 744 745 screen->specs.can_supertile = 746 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); 747 screen->specs.bits_per_tile = 748 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; 749 screen->specs.ts_clear_value = 750 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 751 : 0x11111111; 752 753 /* vertex and fragment samplers live in one address space */ 754 screen->specs.vertex_sampler_offset = 8; 755 screen->specs.fragment_sampler_count = 8; 756 screen->specs.vertex_sampler_count = 4; 757 screen->specs.vs_need_z_div = 758 screen->model < 0x1000 && screen->model != 0x880; 759 screen->specs.has_sin_cos_sqrt = 760 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); 761 screen->specs.has_sign_floor_ceil = 762 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); 763 screen->specs.has_shader_range_registers = 764 screen->model >= 0x1000 || screen->model == 0x880; 765 screen->specs.npot_tex_any_wrap = 766 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); 767 screen->specs.has_new_transcendentals = 768 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); 769 screen->specs.has_halti2_instructions = 770 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); 771 772 if (screen->specs.halti >= 5) { 773 /* GC7000 - this core must load shaders from memory. */ 774 screen->specs.vs_offset = 0; 775 screen->specs.ps_offset = 0; 776 screen->specs.max_instructions = 0; /* Do not program shaders manually */ 777 screen->specs.has_icache = true; 778 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { 779 /* GC3000 - this core is capable of loading shaders from 780 * memory. It can also run shaders from registers, as a fallback, but 781 * "max_instructions" does not have the correct value. It has place for 782 * 2*256 instructions just like GC2000, but the offsets are slightly 783 * different. 784 */ 785 screen->specs.vs_offset = 0xC000; 786 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses 787 * this mirror for writing PS instructions, probably safest to do the 788 * same. 789 */ 790 screen->specs.ps_offset = 0x8000 + 0x1000; 791 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ 792 screen->specs.has_icache = true; 793 } else { 794 if (instruction_count > 256) { /* unified instruction memory? */ 795 screen->specs.vs_offset = 0xC000; 796 screen->specs.ps_offset = 0xD000; /* like vivante driver */ 797 screen->specs.max_instructions = 256; 798 } else { 799 screen->specs.vs_offset = 0x4000; 800 screen->specs.ps_offset = 0x6000; 801 screen->specs.max_instructions = instruction_count / 2; 802 } 803 screen->specs.has_icache = false; 804 } 805 806 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { 807 screen->specs.max_varyings = 12; 808 screen->specs.vertex_max_elements = 16; 809 } else { 810 screen->specs.max_varyings = 8; 811 /* Etna_viv documentation seems confused over the correct value 812 * here so choose the lower to be safe: HALTI0 says 16 i.s.o. 813 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ 814 screen->specs.vertex_max_elements = 10; 815 } 816 817 /* Etna_viv documentation does not indicate where varyings above 8 are 818 * stored. Moreover, if we are passed more than 8 varyings, we will 819 * walk off the end of some arrays. Limit the maximum number of varyings. */ 820 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) 821 screen->specs.max_varyings = ETNA_NUM_VARYINGS; 822 823 /* from QueryShaderCaps in kernel driver */ 824 if (screen->model < chipModel_GC4000) { 825 screen->specs.max_vs_uniforms = 168; 826 screen->specs.max_ps_uniforms = 64; 827 } else { 828 screen->specs.max_vs_uniforms = 256; 829 screen->specs.max_ps_uniforms = 256; 830 } 831 832 if (screen->specs.halti >= 5) { 833 screen->specs.has_unified_uniforms = true; 834 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); 835 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); 836 } else if (screen->specs.halti >= 1) { 837 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess 838 */ 839 screen->specs.has_unified_uniforms = true; 840 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); 841 /* hardcode PS uniforms to start after end of VS uniforms - 842 * for more flexibility this offset could be variable based on the 843 * shader. 844 */ 845 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); 846 } else { 847 screen->specs.has_unified_uniforms = false; 848 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); 849 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); 850 } 851 852 screen->specs.max_texture_size = 853 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; 854 screen->specs.max_rendertarget_size = 855 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; 856 857 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); 858 if (screen->specs.single_buffer) 859 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); 860 861 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); 862 863 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); 864 865 return true; 866 867fail: 868 return false; 869} 870 871struct etna_bo * 872etna_screen_bo_from_handle(struct pipe_screen *pscreen, 873 struct winsys_handle *whandle, unsigned *out_stride) 874{ 875 struct etna_screen *screen = etna_screen(pscreen); 876 struct etna_bo *bo; 877 878 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { 879 bo = etna_bo_from_name(screen->dev, whandle->handle); 880 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { 881 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle); 882 } else { 883 DBG("Attempt to import unsupported handle type %d", whandle->type); 884 return NULL; 885 } 886 887 if (!bo) { 888 DBG("ref name 0x%08x failed", whandle->handle); 889 return NULL; 890 } 891 892 *out_stride = whandle->stride; 893 894 return bo; 895} 896 897struct pipe_screen * 898etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, 899 struct renderonly *ro) 900{ 901 struct etna_screen *screen = CALLOC_STRUCT(etna_screen); 902 struct pipe_screen *pscreen; 903 drmVersionPtr version; 904 uint64_t val; 905 906 if (!screen) 907 return NULL; 908 909 pscreen = &screen->base; 910 screen->dev = dev; 911 screen->gpu = gpu; 912 screen->ro = renderonly_dup(ro); 913 screen->refcnt = 1; 914 915 if (!screen->ro) { 916 DBG("could not create renderonly object"); 917 goto fail; 918 } 919 920 version = drmGetVersion(screen->ro->gpu_fd); 921 screen->drm_version = ETNA_DRM_VERSION(version->version_major, 922 version->version_minor); 923 drmFreeVersion(version); 924 925 etna_mesa_debug = debug_get_option_etna_mesa_debug(); 926 927 /* Disable autodisable for correct rendering with TS */ 928 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; 929 930 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); 931 if (!screen->pipe) { 932 DBG("could not create 3d pipe"); 933 goto fail; 934 } 935 936 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { 937 DBG("could not get ETNA_GPU_MODEL"); 938 goto fail; 939 } 940 screen->model = val; 941 942 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { 943 DBG("could not get ETNA_GPU_REVISION"); 944 goto fail; 945 } 946 screen->revision = val; 947 948 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { 949 DBG("could not get ETNA_GPU_FEATURES_0"); 950 goto fail; 951 } 952 screen->features[0] = val; 953 954 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { 955 DBG("could not get ETNA_GPU_FEATURES_1"); 956 goto fail; 957 } 958 screen->features[1] = val; 959 960 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { 961 DBG("could not get ETNA_GPU_FEATURES_2"); 962 goto fail; 963 } 964 screen->features[2] = val; 965 966 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { 967 DBG("could not get ETNA_GPU_FEATURES_3"); 968 goto fail; 969 } 970 screen->features[3] = val; 971 972 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { 973 DBG("could not get ETNA_GPU_FEATURES_4"); 974 goto fail; 975 } 976 screen->features[4] = val; 977 978 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { 979 DBG("could not get ETNA_GPU_FEATURES_5"); 980 goto fail; 981 } 982 screen->features[5] = val; 983 984 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { 985 DBG("could not get ETNA_GPU_FEATURES_6"); 986 goto fail; 987 } 988 screen->features[6] = val; 989 990 if (!etna_get_specs(screen)) 991 goto fail; 992 993 /* apply debug options that disable individual features */ 994 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) 995 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; 996 if (DBG_ENABLED(ETNA_DBG_NO_TS)) 997 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; 998 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) 999 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; 1000 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) 1001 screen->specs.can_supertile = 0; 1002 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) 1003 screen->specs.single_buffer = 0; 1004 1005 pscreen->destroy = etna_screen_destroy; 1006 pscreen->get_param = etna_screen_get_param; 1007 pscreen->get_paramf = etna_screen_get_paramf; 1008 pscreen->get_shader_param = etna_screen_get_shader_param; 1009 1010 pscreen->get_name = etna_screen_get_name; 1011 pscreen->get_vendor = etna_screen_get_vendor; 1012 pscreen->get_device_vendor = etna_screen_get_device_vendor; 1013 1014 pscreen->get_timestamp = etna_screen_get_timestamp; 1015 pscreen->context_create = etna_context_create; 1016 pscreen->is_format_supported = etna_screen_is_format_supported; 1017 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; 1018 1019 etna_fence_screen_init(pscreen); 1020 etna_query_screen_init(pscreen); 1021 etna_resource_screen_init(pscreen); 1022 1023 util_dynarray_init(&screen->supported_pm_queries, NULL); 1024 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); 1025 1026 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) 1027 etna_pm_query_setup(screen); 1028 1029 return pscreen; 1030 1031fail: 1032 etna_screen_destroy(pscreen); 1033 return NULL; 1034} 1035