1/* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 23/** 24 * @file iris_screen.c 25 * 26 * Screen related driver hooks and capability lists. 27 * 28 * A program may use multiple rendering contexts (iris_context), but 29 * they all share a common screen (iris_screen). Global driver state 30 * can be stored in the screen; it may be accessed by multiple threads. 31 */ 32 33#include <stdio.h> 34#include <errno.h> 35#include <sys/ioctl.h> 36#include "pipe/p_defines.h" 37#include "pipe/p_state.h" 38#include "pipe/p_context.h" 39#include "pipe/p_screen.h" 40#include "util/debug.h" 41#include "util/u_cpu_detect.h" 42#include "util/u_inlines.h" 43#include "util/format/u_format.h" 44#include "util/u_transfer_helper.h" 45#include "util/u_upload_mgr.h" 46#include "util/ralloc.h" 47#include "util/xmlconfig.h" 48#include "drm-uapi/i915_drm.h" 49#include "iris_context.h" 50#include "iris_defines.h" 51#include "iris_fence.h" 52#include "iris_pipe.h" 53#include "iris_resource.h" 54#include "iris_screen.h" 55#include "compiler/glsl_types.h" 56#include "intel/compiler/brw_compiler.h" 57#include "intel/common/intel_gem.h" 58#include "intel/common/intel_l3_config.h" 59#include "intel/common/intel_uuid.h" 60#include "iris_monitor.h" 61 62#define genX_call(devinfo, func, ...) \ 63 switch ((devinfo)->verx10) { \ 64 case 125: \ 65 gfx125_##func(__VA_ARGS__); \ 66 break; \ 67 case 120: \ 68 gfx12_##func(__VA_ARGS__); \ 69 break; \ 70 case 110: \ 71 gfx11_##func(__VA_ARGS__); \ 72 break; \ 73 case 90: \ 74 gfx9_##func(__VA_ARGS__); \ 75 break; \ 76 case 80: \ 77 gfx8_##func(__VA_ARGS__); \ 78 break; \ 79 default: \ 80 unreachable("Unknown hardware generation"); \ 81 } 82 83static void 84iris_flush_frontbuffer(struct pipe_screen *_screen, 85 struct pipe_context *_pipe, 86 struct pipe_resource *resource, 87 unsigned level, unsigned layer, 88 void *context_private, struct pipe_box *box) 89{ 90} 91 92static const char * 93iris_get_vendor(struct pipe_screen *pscreen) 94{ 95 return "Intel"; 96} 97 98static const char * 99iris_get_device_vendor(struct pipe_screen *pscreen) 100{ 101 return "Intel"; 102} 103 104static void 105iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid) 106{ 107 struct iris_screen *screen = (struct iris_screen *)pscreen; 108 const struct isl_device *isldev = &screen->isl_dev; 109 110 intel_uuid_compute_device_id((uint8_t *)uuid, isldev, PIPE_UUID_SIZE); 111} 112 113static void 114iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid) 115{ 116 struct iris_screen *screen = (struct iris_screen *)pscreen; 117 const struct intel_device_info *devinfo = &screen->devinfo; 118 119 intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE); 120} 121 122static bool 123iris_enable_clover() 124{ 125 static int enable = -1; 126 if (enable < 0) 127 enable = env_var_as_boolean("IRIS_ENABLE_CLOVER", false); 128 return enable; 129} 130 131static void 132iris_warn_clover() 133{ 134 static bool warned = false; 135 if (warned) 136 return; 137 138 warned = true; 139 fprintf(stderr, "WARNING: OpenCL support via iris+clover is incomplete.\n" 140 "For a complete and conformant OpenCL implementation, use\n" 141 "https://github.com/intel/compute-runtime instead\n"); 142} 143 144static const char * 145iris_get_name(struct pipe_screen *pscreen) 146{ 147 struct iris_screen *screen = (struct iris_screen *)pscreen; 148 const struct intel_device_info *devinfo = &screen->devinfo; 149 static char buf[128]; 150 151 snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name); 152 return buf; 153} 154 155static int 156iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 157{ 158 struct iris_screen *screen = (struct iris_screen *)pscreen; 159 const struct intel_device_info *devinfo = &screen->devinfo; 160 161 switch (param) { 162 case PIPE_CAP_NPOT_TEXTURES: 163 case PIPE_CAP_ANISOTROPIC_FILTER: 164 case PIPE_CAP_POINT_SPRITE: 165 case PIPE_CAP_OCCLUSION_QUERY: 166 case PIPE_CAP_QUERY_TIME_ELAPSED: 167 case PIPE_CAP_TEXTURE_SWIZZLE: 168 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: 169 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 170 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: 171 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: 172 case PIPE_CAP_VERTEX_SHADER_SATURATE: 173 case PIPE_CAP_PRIMITIVE_RESTART: 174 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: 175 case PIPE_CAP_INDEP_BLEND_ENABLE: 176 case PIPE_CAP_INDEP_BLEND_FUNC: 177 case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND: 178 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 179 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 180 case PIPE_CAP_DEPTH_CLIP_DISABLE: 181 case PIPE_CAP_TGSI_INSTANCEID: 182 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 183 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 184 case PIPE_CAP_SEAMLESS_CUBE_MAP: 185 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 186 case PIPE_CAP_CONDITIONAL_RENDER: 187 case PIPE_CAP_TEXTURE_BARRIER: 188 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 189 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 190 case PIPE_CAP_COMPUTE: 191 case PIPE_CAP_START_INSTANCE: 192 case PIPE_CAP_QUERY_TIMESTAMP: 193 case PIPE_CAP_TEXTURE_MULTISAMPLE: 194 case PIPE_CAP_CUBE_MAP_ARRAY: 195 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: 196 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE: 197 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: 198 case PIPE_CAP_TEXTURE_QUERY_LOD: 199 case PIPE_CAP_SAMPLE_SHADING: 200 case PIPE_CAP_FORCE_PERSAMPLE_INTERP: 201 case PIPE_CAP_DRAW_INDIRECT: 202 case PIPE_CAP_MULTI_DRAW_INDIRECT: 203 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: 204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: 205 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: 206 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: 207 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: 208 case PIPE_CAP_TGSI_PACK_HALF_FLOAT: 209 case PIPE_CAP_ACCELERATED: 210 case PIPE_CAP_UMA: 211 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: 212 case PIPE_CAP_CLIP_HALFZ: 213 case PIPE_CAP_TGSI_TEXCOORD: 214 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: 215 case PIPE_CAP_DOUBLES: 216 case PIPE_CAP_INT64: 217 case PIPE_CAP_INT64_DIVMOD: 218 case PIPE_CAP_SAMPLER_VIEW_TARGET: 219 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: 220 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: 221 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: 222 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: 223 case PIPE_CAP_CULL_DISTANCE: 224 case PIPE_CAP_PACKED_UNIFORMS: 225 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: 226 case PIPE_CAP_TEXTURE_FLOAT_LINEAR: 227 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: 228 case PIPE_CAP_POLYGON_OFFSET_CLAMP: 229 case PIPE_CAP_QUERY_SO_OVERFLOW: 230 case PIPE_CAP_QUERY_BUFFER_OBJECT: 231 case PIPE_CAP_TGSI_TEX_TXF_LZ: 232 case PIPE_CAP_TGSI_TXQS: 233 case PIPE_CAP_TGSI_CLOCK: 234 case PIPE_CAP_TGSI_BALLOT: 235 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: 236 case PIPE_CAP_CLEAR_TEXTURE: 237 case PIPE_CAP_CLEAR_SCISSORED: 238 case PIPE_CAP_TGSI_VOTE: 239 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: 240 case PIPE_CAP_TEXTURE_GATHER_SM5: 241 case PIPE_CAP_TGSI_ARRAY_COMPONENTS: 242 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS: 243 case PIPE_CAP_LOAD_CONSTBUF: 244 case PIPE_CAP_NIR_COMPACT_ARRAYS: 245 case PIPE_CAP_DRAW_PARAMETERS: 246 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: 247 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: 248 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES: 249 case PIPE_CAP_INVALIDATE_BUFFER: 250 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: 251 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: 252 case PIPE_CAP_TEXTURE_SHADOW_LOD: 253 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL: 254 case PIPE_CAP_GL_SPIRV: 255 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS: 256 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION: 257 case PIPE_CAP_NATIVE_FENCE_FD: 258 case PIPE_CAP_MEMOBJ: 259 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: 260 case PIPE_CAP_FENCE_SIGNAL: 261 return true; 262 case PIPE_CAP_FBFETCH: 263 return BRW_MAX_DRAW_BUFFERS; 264 case PIPE_CAP_FBFETCH_COHERENT: 265 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE: 266 case PIPE_CAP_POST_DEPTH_COVERAGE: 267 case PIPE_CAP_SHADER_STENCIL_EXPORT: 268 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: 269 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK: 270 case PIPE_CAP_ATOMIC_FLOAT_MINMAX: 271 return devinfo->ver >= 9; 272 case PIPE_CAP_DEPTH_BOUNDS_TEST: 273 return devinfo->ver >= 12; 274 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 275 return 1; 276 case PIPE_CAP_MAX_RENDER_TARGETS: 277 return BRW_MAX_DRAW_BUFFERS; 278 case PIPE_CAP_MAX_TEXTURE_2D_SIZE: 279 return 16384; 280 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 281 return IRIS_MAX_MIPLEVELS; /* 16384x16384 */ 282 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 283 return 12; /* 2048x2048 */ 284 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 285 return 4; 286 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 287 return 2048; 288 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 289 return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS; 290 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 291 return BRW_MAX_SOL_BINDINGS; 292 case PIPE_CAP_GLSL_FEATURE_LEVEL: 293 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: 294 return 460; 295 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 296 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */ 297 return 32; 298 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: 299 return IRIS_MAP_BUFFER_ALIGNMENT; 300 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: 301 return 4; 302 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: 303 return 1 << 27; 304 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: 305 return 16; // XXX: u_screen says 256 is the minimum value... 306 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: 307 return true; 308 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: 309 return IRIS_MAX_TEXTURE_BUFFER_SIZE; 310 case PIPE_CAP_MAX_VIEWPORTS: 311 return 16; 312 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: 313 return 256; 314 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: 315 return 1024; 316 case PIPE_CAP_MAX_GS_INVOCATIONS: 317 return 32; 318 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: 319 return 4; 320 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: 321 return -32; 322 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: 323 return 31; 324 case PIPE_CAP_MAX_VERTEX_STREAMS: 325 return 4; 326 case PIPE_CAP_VENDOR_ID: 327 return 0x8086; 328 case PIPE_CAP_DEVICE_ID: 329 return screen->pci_id; 330 case PIPE_CAP_VIDEO_MEMORY: { 331 /* Once a batch uses more than 75% of the maximum mappable size, we 332 * assume that there's some fragmentation, and we start doing extra 333 * flushing, etc. That's the big cliff apps will care about. 334 */ 335 const unsigned gpu_mappable_megabytes = 336 (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024); 337 338 const long system_memory_pages = sysconf(_SC_PHYS_PAGES); 339 const long system_page_size = sysconf(_SC_PAGE_SIZE); 340 341 if (system_memory_pages <= 0 || system_page_size <= 0) 342 return -1; 343 344 const uint64_t system_memory_bytes = 345 (uint64_t) system_memory_pages * (uint64_t) system_page_size; 346 347 const unsigned system_memory_megabytes = 348 (unsigned) (system_memory_bytes / (1024 * 1024)); 349 350 return MIN2(system_memory_megabytes, gpu_mappable_megabytes); 351 } 352 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: 353 case PIPE_CAP_MAX_VARYINGS: 354 return 32; 355 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: 356 /* AMD_pinned_memory assumes the flexibility of using client memory 357 * for any buffer (incl. vertex buffers) which rules out the prospect 358 * of using snooped buffers, as using snooped buffers without 359 * cogniscience is likely to be detrimental to performance and require 360 * extensive checking in the driver for correctness, e.g. to prevent 361 * illegal snoop <-> snoop transfers. 362 */ 363 return devinfo->has_llc; 364 case PIPE_CAP_THROTTLE: 365 return screen->driconf.disable_throttling ? 0 : 1; 366 367 case PIPE_CAP_CONTEXT_PRIORITY_MASK: 368 return PIPE_CONTEXT_PRIORITY_LOW | 369 PIPE_CONTEXT_PRIORITY_MEDIUM | 370 PIPE_CONTEXT_PRIORITY_HIGH; 371 372 case PIPE_CAP_FRONTEND_NOOP: 373 return true; 374 375 // XXX: don't hardcode 00:00:02.0 PCI here 376 case PIPE_CAP_PCI_GROUP: 377 return 0; 378 case PIPE_CAP_PCI_BUS: 379 return 0; 380 case PIPE_CAP_PCI_DEVICE: 381 return 2; 382 case PIPE_CAP_PCI_FUNCTION: 383 return 0; 384 385 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: 386 case PIPE_CAP_INTEGER_MULTIPLY_32X16: 387 return true; 388 389 case PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH: 390 /* Internal details of VF cache make this optimization harmful on GFX 391 * version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached 392 * separately. 393 */ 394 return devinfo->ver >= 11; 395 396 default: 397 return u_pipe_screen_get_param_defaults(pscreen, param); 398 } 399 return 0; 400} 401 402static float 403iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 404{ 405 switch (param) { 406 case PIPE_CAPF_MAX_LINE_WIDTH: 407 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 408 return 7.375f; 409 410 case PIPE_CAPF_MAX_POINT_WIDTH: 411 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 412 return 255.0f; 413 414 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 415 return 16.0f; 416 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 417 return 15.0f; 418 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: 419 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: 420 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: 421 return 0.0f; 422 default: 423 unreachable("unknown param"); 424 } 425} 426 427static int 428iris_get_shader_param(struct pipe_screen *pscreen, 429 enum pipe_shader_type p_stage, 430 enum pipe_shader_cap param) 431{ 432 gl_shader_stage stage = stage_from_pipe(p_stage); 433 434 /* this is probably not totally correct.. but it's a start: */ 435 switch (param) { 436 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 437 return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384; 438 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 439 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 440 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 441 return stage == MESA_SHADER_FRAGMENT ? 1024 : 0; 442 443 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 444 return UINT_MAX; 445 446 case PIPE_SHADER_CAP_MAX_INPUTS: 447 return stage == MESA_SHADER_VERTEX ? 16 : 32; 448 case PIPE_SHADER_CAP_MAX_OUTPUTS: 449 return 32; 450 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: 451 return 16 * 1024 * sizeof(float); 452 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 453 return 16; 454 case PIPE_SHADER_CAP_MAX_TEMPS: 455 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */ 456 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 457 return 0; 458 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 459 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 460 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 461 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 462 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects, 463 * which we don't want. Our compiler backend will check brw_compiler's 464 * options and call nir_lower_indirect_derefs appropriately anyway. 465 */ 466 return true; 467 case PIPE_SHADER_CAP_SUBROUTINES: 468 return 0; 469 case PIPE_SHADER_CAP_INTEGERS: 470 return 1; 471 case PIPE_SHADER_CAP_INT64_ATOMICS: 472 case PIPE_SHADER_CAP_FP16: 473 case PIPE_SHADER_CAP_FP16_DERIVATIVES: 474 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: 475 case PIPE_SHADER_CAP_INT16: 476 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: 477 return 0; 478 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 479 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: 480 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: 481 return IRIS_MAX_TEXTURE_SAMPLERS; 482 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: 483 return IRIS_MAX_ABOS + IRIS_MAX_SSBOS; 484 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: 485 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: 486 return 0; 487 case PIPE_SHADER_CAP_PREFERRED_IR: 488 return PIPE_SHADER_IR_NIR; 489 case PIPE_SHADER_CAP_SUPPORTED_IRS: { 490 int irs = 1 << PIPE_SHADER_IR_NIR; 491 if (iris_enable_clover()) 492 irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED; 493 return irs; 494 } 495 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: 496 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: 497 return 1; 498 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: 499 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: 500 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: 501 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: 502 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: 503 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: 504 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: 505 return 0; 506 default: 507 unreachable("unknown shader param"); 508 } 509} 510 511static int 512iris_get_compute_param(struct pipe_screen *pscreen, 513 enum pipe_shader_ir ir_type, 514 enum pipe_compute_cap param, 515 void *ret) 516{ 517 struct iris_screen *screen = (struct iris_screen *)pscreen; 518 const struct intel_device_info *devinfo = &screen->devinfo; 519 520 const uint32_t max_invocations = 32 * devinfo->max_cs_workgroup_threads; 521 522#define RET(x) do { \ 523 if (ret) \ 524 memcpy(ret, x, sizeof(x)); \ 525 return sizeof(x); \ 526} while (0) 527 528 switch (param) { 529 case PIPE_COMPUTE_CAP_ADDRESS_BITS: 530 /* This gets queried on clover device init and is never queried by the 531 * OpenGL state tracker. 532 */ 533 iris_warn_clover(); 534 RET((uint32_t []){ 64 }); 535 536 case PIPE_COMPUTE_CAP_IR_TARGET: 537 if (ret) 538 strcpy(ret, "gen"); 539 return 4; 540 541 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 542 RET((uint64_t []) { 3 }); 543 544 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 545 RET(((uint64_t []) { 65535, 65535, 65535 })); 546 547 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 548 /* MaxComputeWorkGroupSize[0..2] */ 549 RET(((uint64_t []) {max_invocations, max_invocations, max_invocations})); 550 551 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 552 /* MaxComputeWorkGroupInvocations */ 553 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: 554 /* MaxComputeVariableGroupInvocations */ 555 RET((uint64_t []) { max_invocations }); 556 557 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 558 /* MaxComputeSharedMemorySize */ 559 RET((uint64_t []) { 64 * 1024 }); 560 561 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: 562 RET((uint32_t []) { 1 }); 563 564 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: 565 RET((uint32_t []) { BRW_SUBGROUP_SIZE }); 566 567 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: 568 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 569 RET((uint64_t []) { 1 << 30 }); /* TODO */ 570 571 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: 572 RET((uint32_t []) { 400 }); /* TODO */ 573 574 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: { 575 RET((uint32_t []) { intel_device_info_subslice_total(devinfo) }); 576 } 577 578 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: 579 /* MaxComputeSharedMemorySize */ 580 RET((uint64_t []) { 64 * 1024 }); 581 582 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 583 /* We could probably allow more; this is the OpenCL minimum */ 584 RET((uint64_t []) { 1024 }); 585 586 default: 587 unreachable("unknown compute param"); 588 } 589} 590 591static uint64_t 592iris_get_timestamp(struct pipe_screen *pscreen) 593{ 594 struct iris_screen *screen = (struct iris_screen *) pscreen; 595 const unsigned TIMESTAMP = 0x2358; 596 uint64_t result; 597 598 iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result); 599 600 result = intel_device_info_timebase_scale(&screen->devinfo, result); 601 result &= (1ull << TIMESTAMP_BITS) - 1; 602 603 return result; 604} 605 606void 607iris_screen_destroy(struct iris_screen *screen) 608{ 609 iris_destroy_screen_measure(screen); 610 util_queue_destroy(&screen->shader_compiler_queue); 611 glsl_type_singleton_decref(); 612 iris_bo_unreference(screen->workaround_bo); 613 u_transfer_helper_destroy(screen->base.transfer_helper); 614 iris_bufmgr_unref(screen->bufmgr); 615 disk_cache_destroy(screen->disk_cache); 616 close(screen->winsys_fd); 617 ralloc_free(screen); 618} 619 620static void 621iris_screen_unref(struct pipe_screen *pscreen) 622{ 623 iris_pscreen_unref(pscreen); 624} 625 626static void 627iris_query_memory_info(struct pipe_screen *pscreen, 628 struct pipe_memory_info *info) 629{ 630} 631 632static const void * 633iris_get_compiler_options(struct pipe_screen *pscreen, 634 enum pipe_shader_ir ir, 635 enum pipe_shader_type pstage) 636{ 637 struct iris_screen *screen = (struct iris_screen *) pscreen; 638 gl_shader_stage stage = stage_from_pipe(pstage); 639 assert(ir == PIPE_SHADER_IR_NIR); 640 641 return screen->compiler->glsl_compiler_options[stage].NirOptions; 642} 643 644static struct disk_cache * 645iris_get_disk_shader_cache(struct pipe_screen *pscreen) 646{ 647 struct iris_screen *screen = (struct iris_screen *) pscreen; 648 return screen->disk_cache; 649} 650 651static int 652iris_getparam(int fd, int param, int *value) 653{ 654 struct drm_i915_getparam gp = { .param = param, .value = value }; 655 656 if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) 657 return -errno; 658 659 return 0; 660} 661 662static int 663iris_getparam_integer(int fd, int param) 664{ 665 int value = -1; 666 667 if (iris_getparam(fd, param, &value) == 0) 668 return value; 669 670 return -1; 671} 672 673static const struct intel_l3_config * 674iris_get_default_l3_config(const struct intel_device_info *devinfo, 675 bool compute) 676{ 677 bool wants_dc_cache = true; 678 bool has_slm = compute; 679 const struct intel_l3_weights w = 680 intel_get_default_l3_weights(devinfo, wants_dc_cache, has_slm); 681 return intel_get_l3_config(devinfo, w); 682} 683 684static void 685iris_shader_debug_log(void *data, unsigned *id, const char *fmt, ...) 686{ 687 struct pipe_debug_callback *dbg = data; 688 va_list args; 689 690 if (!dbg->debug_message) 691 return; 692 693 va_start(args, fmt); 694 dbg->debug_message(dbg->data, id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args); 695 va_end(args); 696} 697 698static void 699iris_shader_perf_log(void *data, unsigned *id, const char *fmt, ...) 700{ 701 struct pipe_debug_callback *dbg = data; 702 va_list args; 703 va_start(args, fmt); 704 705 if (INTEL_DEBUG(DEBUG_PERF)) { 706 va_list args_copy; 707 va_copy(args_copy, args); 708 vfprintf(stderr, fmt, args_copy); 709 va_end(args_copy); 710 } 711 712 if (dbg->debug_message) { 713 dbg->debug_message(dbg->data, id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); 714 } 715 716 va_end(args); 717} 718 719static void 720iris_detect_kernel_features(struct iris_screen *screen) 721{ 722 /* Kernel 5.2+ */ 723 if (intel_gem_supports_syncobj_wait(screen->fd)) 724 screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT; 725} 726 727static bool 728iris_init_identifier_bo(struct iris_screen *screen) 729{ 730 void *bo_map; 731 732 bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE); 733 if (!bo_map) 734 return false; 735 736 assert(iris_bo_is_real(screen->workaround_bo)); 737 738 screen->workaround_bo->real.kflags |= 739 EXEC_OBJECT_CAPTURE | EXEC_OBJECT_ASYNC; 740 screen->workaround_address = (struct iris_address) { 741 .bo = screen->workaround_bo, 742 .offset = ALIGN( 743 intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8), 744 }; 745 746 iris_bo_unmap(screen->workaround_bo); 747 748 return true; 749} 750 751struct pipe_screen * 752iris_screen_create(int fd, const struct pipe_screen_config *config) 753{ 754 /* Here are the i915 features we need for Iris (in chronological order) : 755 * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10) 756 * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10) 757 * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13) 758 * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14) 759 * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16) 760 * 761 * Checking the last feature availability will include all previous ones. 762 */ 763 if (iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION) <= 0) { 764 debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n"); 765 return NULL; 766 } 767 768 struct iris_screen *screen = rzalloc(NULL, struct iris_screen); 769 if (!screen) 770 return NULL; 771 772 if (!intel_get_device_info_from_fd(fd, &screen->devinfo)) 773 return NULL; 774 screen->pci_id = screen->devinfo.chipset_id; 775 776 p_atomic_set(&screen->refcount, 1); 777 778 if (screen->devinfo.ver < 8 || screen->devinfo.is_cherryview) 779 return NULL; 780 781 driParseConfigFiles(config->options, config->options_info, 0, "iris", 782 NULL, NULL, NULL, 0, NULL, 0); 783 784 bool bo_reuse = false; 785 int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse"); 786 switch (bo_reuse_mode) { 787 case DRI_CONF_BO_REUSE_DISABLED: 788 break; 789 case DRI_CONF_BO_REUSE_ALL: 790 bo_reuse = true; 791 break; 792 } 793 794 screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse); 795 if (!screen->bufmgr) 796 return NULL; 797 798 screen->fd = iris_bufmgr_get_fd(screen->bufmgr); 799 screen->winsys_fd = fd; 800 801 screen->id = iris_bufmgr_create_screen_id(screen->bufmgr); 802 803 screen->workaround_bo = 804 iris_bo_alloc(screen->bufmgr, "workaround", 4096, 1, 805 IRIS_MEMZONE_OTHER, BO_ALLOC_NO_SUBALLOC); 806 if (!screen->workaround_bo) 807 return NULL; 808 809 if (!iris_init_identifier_bo(screen)) 810 return NULL; 811 812 brw_process_intel_debug_variable(); 813 814 screen->driconf.dual_color_blend_by_location = 815 driQueryOptionb(config->options, "dual_color_blend_by_location"); 816 screen->driconf.disable_throttling = 817 driQueryOptionb(config->options, "disable_throttling"); 818 screen->driconf.always_flush_cache = 819 driQueryOptionb(config->options, "always_flush_cache"); 820 screen->driconf.sync_compile = 821 driQueryOptionb(config->options, "sync_compile"); 822 823 screen->precompile = env_var_as_boolean("shader_precompile", true); 824 825 isl_device_init(&screen->isl_dev, &screen->devinfo, false); 826 827 screen->compiler = brw_compiler_create(screen, &screen->devinfo); 828 screen->compiler->shader_debug_log = iris_shader_debug_log; 829 screen->compiler->shader_perf_log = iris_shader_perf_log; 830 screen->compiler->supports_pull_constants = false; 831 screen->compiler->supports_shader_constants = true; 832 screen->compiler->compact_params = false; 833 screen->compiler->indirect_ubos_use_sampler = screen->devinfo.ver < 12; 834 835 screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false); 836 screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true); 837 838 iris_disk_cache_init(screen); 839 840 slab_create_parent(&screen->transfer_pool, 841 sizeof(struct iris_transfer), 64); 842 843 iris_detect_kernel_features(screen); 844 845 struct pipe_screen *pscreen = &screen->base; 846 847 iris_init_screen_fence_functions(pscreen); 848 iris_init_screen_resource_functions(pscreen); 849 iris_init_screen_measure(screen); 850 851 pscreen->destroy = iris_screen_unref; 852 pscreen->get_name = iris_get_name; 853 pscreen->get_vendor = iris_get_vendor; 854 pscreen->get_device_vendor = iris_get_device_vendor; 855 pscreen->get_param = iris_get_param; 856 pscreen->get_shader_param = iris_get_shader_param; 857 pscreen->get_compute_param = iris_get_compute_param; 858 pscreen->get_paramf = iris_get_paramf; 859 pscreen->get_compiler_options = iris_get_compiler_options; 860 pscreen->get_device_uuid = iris_get_device_uuid; 861 pscreen->get_driver_uuid = iris_get_driver_uuid; 862 pscreen->get_disk_shader_cache = iris_get_disk_shader_cache; 863 pscreen->is_format_supported = iris_is_format_supported; 864 pscreen->context_create = iris_create_context; 865 pscreen->flush_frontbuffer = iris_flush_frontbuffer; 866 pscreen->get_timestamp = iris_get_timestamp; 867 pscreen->query_memory_info = iris_query_memory_info; 868 pscreen->get_driver_query_group_info = iris_get_monitor_group_info; 869 pscreen->get_driver_query_info = iris_get_monitor_info; 870 iris_init_screen_program_functions(pscreen); 871 872 genX_call(&screen->devinfo, init_screen_state, screen); 873 874 glsl_type_singleton_init_or_ref(); 875 876 /* FINISHME: Big core vs little core (for CPUs that have both kinds of 877 * cores) and, possibly, thread vs core should be considered here too. 878 */ 879 unsigned compiler_threads = 1; 880 const struct util_cpu_caps_t *caps = util_get_cpu_caps(); 881 unsigned hw_threads = caps->nr_cpus; 882 883 if (hw_threads >= 12) { 884 compiler_threads = hw_threads * 3 / 4; 885 } else if (hw_threads >= 6) { 886 compiler_threads = hw_threads - 2; 887 } else if (hw_threads >= 2) { 888 compiler_threads = hw_threads - 1; 889 } 890 891 if (!util_queue_init(&screen->shader_compiler_queue, 892 "sh", 64, compiler_threads, 893 UTIL_QUEUE_INIT_RESIZE_IF_FULL | 894 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY, 895 NULL)) { 896 iris_screen_destroy(screen); 897 return NULL; 898 } 899 900 return pscreen; 901} 902