iris_screen.c revision 9f464c52 
1/*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23/**
24 * @file iris_screen.c
25 *
26 * Screen related driver hooks and capability lists.
27 *
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen).  Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
31 */
32
33#include <stdio.h>
34#include <errno.h>
35#include <sys/ioctl.h>
36#include "pipe/p_defines.h"
37#include "pipe/p_state.h"
38#include "pipe/p_context.h"
39#include "pipe/p_screen.h"
40#include "util/debug.h"
41#include "util/u_inlines.h"
42#include "util/u_format.h"
43#include "util/u_transfer_helper.h"
44#include "util/u_upload_mgr.h"
45#include "util/ralloc.h"
46#include "util/xmlconfig.h"
47#include "drm-uapi/i915_drm.h"
48#include "iris_context.h"
49#include "iris_defines.h"
50#include "iris_fence.h"
51#include "iris_pipe.h"
52#include "iris_resource.h"
53#include "iris_screen.h"
54#include "intel/compiler/brw_compiler.h"
55
56static void
57iris_flush_frontbuffer(struct pipe_screen *_screen,
58                       struct pipe_resource *resource,
59                       unsigned level, unsigned layer,
60                       void *context_private, struct pipe_box *box)
61{
62}
63
64static const char *
65iris_get_vendor(struct pipe_screen *pscreen)
66{
67   return "Intel";
68}
69
70static const char *
71iris_get_device_vendor(struct pipe_screen *pscreen)
72{
73   return "Intel";
74}
75
76static const char *
77iris_get_name(struct pipe_screen *pscreen)
78{
79   struct iris_screen *screen = (struct iris_screen *)pscreen;
80   static char buf[128];
81   const char *chipset;
82
83   switch (screen->pci_id) {
84#undef CHIPSET
85#define CHIPSET(id, symbol, str) case id: chipset = str; break;
86#include "pci_ids/i965_pci_ids.h"
87   default:
88      chipset = "Unknown Intel Chipset";
89      break;
90   }
91
92   snprintf(buf, sizeof(buf), "Mesa %s", chipset);
93   return buf;
94}
95
96static int
97iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
98{
99   struct iris_screen *screen = (struct iris_screen *)pscreen;
100   const struct gen_device_info *devinfo = &screen->devinfo;
101
102   switch (param) {
103   case PIPE_CAP_NPOT_TEXTURES:
104   case PIPE_CAP_ANISOTROPIC_FILTER:
105   case PIPE_CAP_POINT_SPRITE:
106   case PIPE_CAP_OCCLUSION_QUERY:
107   case PIPE_CAP_QUERY_TIME_ELAPSED:
108   case PIPE_CAP_TEXTURE_SWIZZLE:
109   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
110   case PIPE_CAP_BLEND_EQUATION_SEPARATE:
111   case PIPE_CAP_SM3:
112   case PIPE_CAP_PRIMITIVE_RESTART:
113   case PIPE_CAP_INDEP_BLEND_ENABLE:
114   case PIPE_CAP_INDEP_BLEND_FUNC:
115   case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
116   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
117   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
118   case PIPE_CAP_DEPTH_CLIP_DISABLE:
119   case PIPE_CAP_TGSI_INSTANCEID:
120   case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
121   case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
122   case PIPE_CAP_SEAMLESS_CUBE_MAP:
123   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
124   case PIPE_CAP_CONDITIONAL_RENDER:
125   case PIPE_CAP_TEXTURE_BARRIER:
126   case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
127   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
128   case PIPE_CAP_COMPUTE:
129   case PIPE_CAP_START_INSTANCE:
130   case PIPE_CAP_QUERY_TIMESTAMP:
131   case PIPE_CAP_TEXTURE_MULTISAMPLE:
132   case PIPE_CAP_CUBE_MAP_ARRAY:
133   case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
134   case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
135   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
136   case PIPE_CAP_TEXTURE_QUERY_LOD:
137   case PIPE_CAP_SAMPLE_SHADING:
138   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
139   case PIPE_CAP_DRAW_INDIRECT:
140   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
141   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
142   case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
143   case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
144   case PIPE_CAP_ACCELERATED:
145   case PIPE_CAP_UMA:
146   case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
147   case PIPE_CAP_CLIP_HALFZ:
148   case PIPE_CAP_TGSI_TEXCOORD:
149   case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
150   case PIPE_CAP_DOUBLES:
151   case PIPE_CAP_INT64:
152   case PIPE_CAP_INT64_DIVMOD:
153   case PIPE_CAP_SAMPLER_VIEW_TARGET:
154   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
155   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
156   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
157   case PIPE_CAP_CULL_DISTANCE:
158   case PIPE_CAP_PACKED_UNIFORMS:
159   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
160   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
161   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
162   case PIPE_CAP_POLYGON_OFFSET_CLAMP:
163   case PIPE_CAP_QUERY_SO_OVERFLOW:
164   case PIPE_CAP_QUERY_BUFFER_OBJECT:
165   case PIPE_CAP_TGSI_TEX_TXF_LZ:
166   case PIPE_CAP_TGSI_TXQS:
167   case PIPE_CAP_TGSI_CLOCK:
168   case PIPE_CAP_TGSI_BALLOT:
169   case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
170   case PIPE_CAP_CLEAR_TEXTURE:
171   case PIPE_CAP_TGSI_VOTE:
172   case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
173   case PIPE_CAP_TEXTURE_GATHER_SM5:
174   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
175   case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
176   case PIPE_CAP_LOAD_CONSTBUF:
177   case PIPE_CAP_NIR_COMPACT_ARRAYS:
178   case PIPE_CAP_DRAW_PARAMETERS:
179   case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
180   case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
181   case PIPE_CAP_INVALIDATE_BUFFER:
182   case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
183      return true;
184   case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
185   case PIPE_CAP_TGSI_FS_FBFETCH:
186   case PIPE_CAP_POST_DEPTH_COVERAGE:
187   case PIPE_CAP_SHADER_STENCIL_EXPORT:
188   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
189      return devinfo->gen >= 9;
190   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
191      return 1;
192   case PIPE_CAP_MAX_RENDER_TARGETS:
193      return BRW_MAX_DRAW_BUFFERS;
194   case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
195   case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
196      return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
197   case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
198      return 12; /* 2048x2048 */
199   case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
200      return 4;
201   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
202      return 2048;
203   case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
204      return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
205   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
206      return BRW_MAX_SOL_BINDINGS;
207   case PIPE_CAP_GLSL_FEATURE_LEVEL:
208      return 460;
209   case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
210      return 140;
211   case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
212      /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
213      return 32;
214   case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
215      return IRIS_MAP_BUFFER_ALIGNMENT;
216   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
217      /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
218       * GPU writing the same SSBO on non-coherent systems (Atom CPUs).  With
219       * UBOs, the GPU never writes, so there's no problem.  For an SSBO, the
220       * GPU and the CPU can be updating disjoint regions of the buffer
221       * simultaneously and that will break if the regions overlap the same
222       * cacheline.
223       */
224      return 64;
225   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
226      return 1 << 27;
227   case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
228      return 16; // XXX: u_screen says 256 is the minimum value...
229   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
230      return true; // XXX: ?????
231   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
232      return IRIS_MAX_TEXTURE_BUFFER_SIZE;
233   case PIPE_CAP_MAX_VIEWPORTS:
234      return 16;
235   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
236      return 256;
237   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
238      return 1024;
239   case PIPE_CAP_MAX_GS_INVOCATIONS:
240      return 32;
241   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
242      return 4;
243   case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
244      return -32;
245   case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
246      return 31;
247   case PIPE_CAP_MAX_VERTEX_STREAMS:
248      return 4;
249   case PIPE_CAP_VENDOR_ID:
250      return 0x8086;
251   case PIPE_CAP_DEVICE_ID:
252      return screen->pci_id;
253   case PIPE_CAP_VIDEO_MEMORY:
254      return INT_MAX; // XXX: bogus
255   case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
256   case PIPE_CAP_MAX_VARYINGS:
257      return 32;
258   case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
259      /* AMD_pinned_memory assumes the flexibility of using client memory
260       * for any buffer (incl. vertex buffers) which rules out the prospect
261       * of using snooped buffers, as using snooped buffers without
262       * cogniscience is likely to be detrimental to performance and require
263       * extensive checking in the driver for correctness, e.g. to prevent
264       * illegal snoop <-> snoop transfers.
265       */
266      return devinfo->has_llc;
267
268   case PIPE_CAP_CONTEXT_PRIORITY_MASK:
269      return PIPE_CONTEXT_PRIORITY_LOW |
270             PIPE_CONTEXT_PRIORITY_MEDIUM |
271             PIPE_CONTEXT_PRIORITY_HIGH;
272
273   // XXX: don't hardcode 00:00:02.0 PCI here
274   case PIPE_CAP_PCI_GROUP:
275      return 0;
276   case PIPE_CAP_PCI_BUS:
277      return 0;
278   case PIPE_CAP_PCI_DEVICE:
279      return 2;
280   case PIPE_CAP_PCI_FUNCTION:
281      return 0;
282
283   default:
284      return u_pipe_screen_get_param_defaults(pscreen, param);
285   }
286   return 0;
287}
288
289static float
290iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
291{
292   switch (param) {
293   case PIPE_CAPF_MAX_LINE_WIDTH:
294   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
295      return 7.375f;
296
297   case PIPE_CAPF_MAX_POINT_WIDTH:
298   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
299      return 255.0f;
300
301   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
302      return 16.0f;
303   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
304      return 15.0f;
305   case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
306   case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
307   case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
308      return 0.0f;
309   default:
310      unreachable("unknown param");
311   }
312}
313
314static int
315iris_get_shader_param(struct pipe_screen *pscreen,
316                      enum pipe_shader_type p_stage,
317                      enum pipe_shader_cap param)
318{
319   gl_shader_stage stage = stage_from_pipe(p_stage);
320
321   /* this is probably not totally correct.. but it's a start: */
322   switch (param) {
323   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
324      return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
325   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
326   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
327   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
328      return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
329
330   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
331      return UINT_MAX;
332
333   case PIPE_SHADER_CAP_MAX_INPUTS:
334      return stage == MESA_SHADER_VERTEX ? 16 : 32;
335   case PIPE_SHADER_CAP_MAX_OUTPUTS:
336      return 32;
337   case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
338      return 16 * 1024 * sizeof(float);
339   case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
340      return 16;
341   case PIPE_SHADER_CAP_MAX_TEMPS:
342      return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
343   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
344      return 0;
345   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
346   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
347   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
348   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
349      /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
350       * which we don't want.  Our compiler backend will check brw_compiler's
351       * options and call nir_lower_indirect_derefs appropriately anyway.
352       */
353      return true;
354   case PIPE_SHADER_CAP_SUBROUTINES:
355      return 0;
356   case PIPE_SHADER_CAP_INTEGERS:
357   case PIPE_SHADER_CAP_SCALAR_ISA:
358      return 1;
359   case PIPE_SHADER_CAP_INT64_ATOMICS:
360   case PIPE_SHADER_CAP_FP16:
361      return 0;
362   case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
363   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
364   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
365      return IRIS_MAX_TEXTURE_SAMPLERS;
366   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
367      return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
368   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
369   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
370      return 0;
371   case PIPE_SHADER_CAP_PREFERRED_IR:
372      return PIPE_SHADER_IR_NIR;
373   case PIPE_SHADER_CAP_SUPPORTED_IRS:
374      return 1 << PIPE_SHADER_IR_NIR;
375   case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
376      return 32;
377   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
378   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
379   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
380   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
381   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
382   case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
383   case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
384   case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
385      return 0;
386   default:
387      unreachable("unknown shader param");
388   }
389}
390
391static int
392iris_get_compute_param(struct pipe_screen *pscreen,
393                       enum pipe_shader_ir ir_type,
394                       enum pipe_compute_cap param,
395                       void *ret)
396{
397   struct iris_screen *screen = (struct iris_screen *)pscreen;
398   const struct gen_device_info *devinfo = &screen->devinfo;
399
400   const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
401   const uint32_t max_invocations = 32 * max_threads;
402
403#define RET(x) do {                  \
404   if (ret)                          \
405      memcpy(ret, x, sizeof(x));     \
406   return sizeof(x);                 \
407} while (0)
408
409   switch (param) {
410   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
411      RET((uint32_t []){ 32 });
412
413   case PIPE_COMPUTE_CAP_IR_TARGET:
414      if (ret)
415         strcpy(ret, "gen");
416      return 4;
417
418   case PIPE_COMPUTE_CAP_GRID_DIMENSION:
419      RET((uint64_t []) { 3 });
420
421   case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
422      RET(((uint64_t []) { 65535, 65535, 65535 }));
423
424   case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
425      /* MaxComputeWorkGroupSize[0..2] */
426      RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
427
428   case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
429      /* MaxComputeWorkGroupInvocations */
430      RET((uint64_t []) { max_invocations });
431
432   case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
433      /* MaxComputeSharedMemorySize */
434      RET((uint64_t []) { 64 * 1024 });
435
436   case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
437      RET((uint32_t []) { 1 });
438
439   case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
440      RET((uint32_t []) { BRW_SUBGROUP_SIZE });
441
442   case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
443   case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
444   case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
445   case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
446   case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
447   case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
448   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
449      // XXX: I think these are for Clover...
450      return 0;
451
452   default:
453      unreachable("unknown compute param");
454   }
455}
456
457static uint64_t
458iris_get_timestamp(struct pipe_screen *pscreen)
459{
460   struct iris_screen *screen = (struct iris_screen *) pscreen;
461   const unsigned TIMESTAMP = 0x2358;
462   uint64_t result;
463
464   iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
465
466   result = iris_timebase_scale(&screen->devinfo, result);
467   result &= (1ull << TIMESTAMP_BITS) - 1;
468
469   return result;
470}
471
472static void
473iris_destroy_screen(struct pipe_screen *pscreen)
474{
475   struct iris_screen *screen = (struct iris_screen *) pscreen;
476   iris_bo_unreference(screen->workaround_bo);
477   u_transfer_helper_destroy(pscreen->transfer_helper);
478   iris_bufmgr_destroy(screen->bufmgr);
479   ralloc_free(screen);
480}
481
482static void
483iris_query_memory_info(struct pipe_screen *pscreen,
484                       struct pipe_memory_info *info)
485{
486}
487
488static const void *
489iris_get_compiler_options(struct pipe_screen *pscreen,
490                          enum pipe_shader_ir ir,
491                          enum pipe_shader_type pstage)
492{
493   struct iris_screen *screen = (struct iris_screen *) pscreen;
494   gl_shader_stage stage = stage_from_pipe(pstage);
495   assert(ir == PIPE_SHADER_IR_NIR);
496
497   return screen->compiler->glsl_compiler_options[stage].NirOptions;
498}
499
500static int
501iris_getparam(struct iris_screen *screen, int param, int *value)
502{
503   struct drm_i915_getparam gp = { .param = param, .value = value };
504
505   if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
506      return -errno;
507
508   return 0;
509}
510
511static int
512iris_getparam_integer(struct iris_screen *screen, int param)
513{
514   int value = -1;
515
516   if (iris_getparam(screen, param, &value) == 0)
517      return value;
518
519   return -1;
520}
521
522static void
523iris_shader_debug_log(void *data, const char *fmt, ...)
524{
525   struct pipe_debug_callback *dbg = data;
526   unsigned id = 0;
527   va_list args;
528
529   if (!dbg->debug_message)
530      return;
531
532   va_start(args, fmt);
533   dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
534   va_end(args);
535}
536
537static void
538iris_shader_perf_log(void *data, const char *fmt, ...)
539{
540   struct pipe_debug_callback *dbg = data;
541   unsigned id = 0;
542   va_list args;
543   va_start(args, fmt);
544
545   if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
546      va_list args_copy;
547      va_copy(args_copy, args);
548      vfprintf(stderr, fmt, args_copy);
549      va_end(args_copy);
550   }
551
552   if (dbg->debug_message) {
553      dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
554   }
555
556   va_end(args);
557}
558
559struct pipe_screen *
560iris_screen_create(int fd, const struct pipe_screen_config *config)
561{
562   struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
563   if (!screen)
564      return NULL;
565
566   screen->fd = fd;
567   screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
568
569   if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
570      return NULL;
571
572   if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
573      return NULL;
574
575   screen->devinfo.timestamp_frequency =
576      iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
577
578   if (getenv("INTEL_NO_HW") != NULL)
579      screen->no_hw = true;
580
581   screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
582   if (!screen->bufmgr)
583      return NULL;
584
585   screen->workaround_bo =
586      iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
587   if (!screen->workaround_bo)
588      return NULL;
589
590   brw_process_intel_debug_variable();
591
592   screen->driconf.dual_color_blend_by_location =
593      driQueryOptionb(config->options, "dual_color_blend_by_location");
594
595   screen->precompile = env_var_as_boolean("shader_precompile", true);
596
597   isl_device_init(&screen->isl_dev, &screen->devinfo, false);
598
599   screen->compiler = brw_compiler_create(screen, &screen->devinfo);
600   screen->compiler->shader_debug_log = iris_shader_debug_log;
601   screen->compiler->shader_perf_log = iris_shader_perf_log;
602   screen->compiler->supports_pull_constants = false;
603
604   slab_create_parent(&screen->transfer_pool,
605                      sizeof(struct iris_transfer), 64);
606
607   screen->subslice_total =
608      iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
609   assert(screen->subslice_total >= 1);
610
611   struct pipe_screen *pscreen = &screen->base;
612
613   iris_init_screen_fence_functions(pscreen);
614   iris_init_screen_resource_functions(pscreen);
615
616   pscreen->destroy = iris_destroy_screen;
617   pscreen->get_name = iris_get_name;
618   pscreen->get_vendor = iris_get_vendor;
619   pscreen->get_device_vendor = iris_get_device_vendor;
620   pscreen->get_param = iris_get_param;
621   pscreen->get_shader_param = iris_get_shader_param;
622   pscreen->get_compute_param = iris_get_compute_param;
623   pscreen->get_paramf = iris_get_paramf;
624   pscreen->get_compiler_options = iris_get_compiler_options;
625   pscreen->is_format_supported = iris_is_format_supported;
626   pscreen->context_create = iris_create_context;
627   pscreen->flush_frontbuffer = iris_flush_frontbuffer;
628   pscreen->get_timestamp = iris_get_timestamp;
629   pscreen->query_memory_info = iris_query_memory_info;
630
631   return pscreen;
632}
633