1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26#include <xf86drm.h>
27#include <nouveau_drm.h>
28#include "util/format/u_format.h"
29#include "util/format/u_format_s3tc.h"
30#include "util/u_screen.h"
31
32#include "nv_object.xml.h"
33#include "nv_m2mf.xml.h"
34#include "nv30/nv30-40_3d.xml.h"
35#include "nv30/nv01_2d.xml.h"
36
37#include "nouveau_fence.h"
38#include "nv30/nv30_screen.h"
39#include "nv30/nv30_context.h"
40#include "nv30/nv30_resource.h"
41#include "nv30/nv30_format.h"
42
43#define RANKINE_0397_CHIPSET 0x00000003
44#define RANKINE_0497_CHIPSET 0x000001e0
45#define RANKINE_0697_CHIPSET 0x00000010
46#define CURIE_4097_CHIPSET   0x00000baf
47#define CURIE_4497_CHIPSET   0x00005450
48#define CURIE_4497_CHIPSET6X 0x00000088
49
50static int
51nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
52{
53   struct nv30_screen *screen = nv30_screen(pscreen);
54   struct nouveau_object *eng3d = screen->eng3d;
55   struct nouveau_device *dev = nouveau_screen(pscreen)->device;
56
57   switch (param) {
58   /* non-boolean capabilities */
59   case PIPE_CAP_MAX_RENDER_TARGETS:
60      return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
61   case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
62      return 4096;
63   case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
64      return 10;
65   case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
66      return 13;
67   case PIPE_CAP_GLSL_FEATURE_LEVEL:
68   case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
69      return 120;
70   case PIPE_CAP_ENDIANNESS:
71      return PIPE_ENDIAN_LITTLE;
72   case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
73      return 16;
74   case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
75      return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
76   case PIPE_CAP_MAX_VIEWPORTS:
77      return 1;
78   case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
79      return 2048;
80   case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
81      return 8 * 1024 * 1024;
82   case PIPE_CAP_MAX_VARYINGS:
83      return 8;
84
85   /* supported capabilities */
86   case PIPE_CAP_ANISOTROPIC_FILTER:
87   case PIPE_CAP_POINT_SPRITE:
88   case PIPE_CAP_OCCLUSION_QUERY:
89   case PIPE_CAP_QUERY_TIME_ELAPSED:
90   case PIPE_CAP_QUERY_TIMESTAMP:
91   case PIPE_CAP_TEXTURE_SWIZZLE:
92   case PIPE_CAP_DEPTH_CLIP_DISABLE:
93   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
94   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
95   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
97   case PIPE_CAP_TGSI_TEXCOORD:
98   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99   case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
100   case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
101   case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
102   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
103   case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104      return 1;
105   /* nv35 capabilities */
106   case PIPE_CAP_DEPTH_BOUNDS_TEST:
107      return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
108   case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
109   case PIPE_CAP_SUPPORTED_PRIM_MODES:
110      return BITFIELD_MASK(PIPE_PRIM_MAX);
111   /* nv4x capabilities */
112   case PIPE_CAP_BLEND_EQUATION_SEPARATE:
113   case PIPE_CAP_NPOT_TEXTURES:
114   case PIPE_CAP_CONDITIONAL_RENDER:
115   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
116   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
117   case PIPE_CAP_PRIMITIVE_RESTART:
118   case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
119      return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
120   /* unsupported */
121   case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
122   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
123   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
124   case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
125   case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
126   case PIPE_CAP_VERTEX_SHADER_SATURATE:
127   case PIPE_CAP_INDEP_BLEND_ENABLE:
128   case PIPE_CAP_INDEP_BLEND_FUNC:
129   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
130   case PIPE_CAP_SHADER_STENCIL_EXPORT:
131   case PIPE_CAP_TGSI_INSTANCEID:
132   case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
133   case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
134   case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
135   case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
136   case PIPE_CAP_MIN_TEXEL_OFFSET:
137   case PIPE_CAP_MAX_TEXEL_OFFSET:
138   case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
139   case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
140   case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
141   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
142   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
143   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
144   case PIPE_CAP_MAX_VERTEX_STREAMS:
145   case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
146   case PIPE_CAP_TEXTURE_BARRIER:
147   case PIPE_CAP_SEAMLESS_CUBE_MAP:
148   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
149   case PIPE_CAP_CUBE_MAP_ARRAY:
150   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
151   case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
152   case PIPE_CAP_VERTEX_COLOR_CLAMPED:
153   case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
154   case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
155   case PIPE_CAP_START_INSTANCE:
156   case PIPE_CAP_TEXTURE_MULTISAMPLE:
157   case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
158   case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
159   case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
160   case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
161   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
162   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
163   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
164   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
165   case PIPE_CAP_TEXTURE_GATHER_SM5:
166   case PIPE_CAP_FAKE_SW_MSAA:
167   case PIPE_CAP_TEXTURE_QUERY_LOD:
168   case PIPE_CAP_SAMPLE_SHADING:
169   case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
170   case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
171   case PIPE_CAP_USER_VERTEX_BUFFERS:
172   case PIPE_CAP_COMPUTE:
173   case PIPE_CAP_DRAW_INDIRECT:
174   case PIPE_CAP_MULTI_DRAW_INDIRECT:
175   case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
176   case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
177   case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
178   case PIPE_CAP_SAMPLER_VIEW_TARGET:
179   case PIPE_CAP_CLIP_HALFZ:
180   case PIPE_CAP_VERTEXID_NOBASE:
181   case PIPE_CAP_POLYGON_OFFSET_CLAMP:
182   case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
183   case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
184   case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
185   case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
186   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
187   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
188   case PIPE_CAP_TGSI_TXQS:
189   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
190   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
191   case PIPE_CAP_SHAREABLE_SHADERS:
192   case PIPE_CAP_CLEAR_TEXTURE:
193   case PIPE_CAP_DRAW_PARAMETERS:
194   case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
195   case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
196   case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
197   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
198   case PIPE_CAP_INVALIDATE_BUFFER:
199   case PIPE_CAP_GENERATE_MIPMAP:
200   case PIPE_CAP_STRING_MARKER:
201   case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
202   case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
203   case PIPE_CAP_QUERY_BUFFER_OBJECT:
204   case PIPE_CAP_QUERY_MEMORY_INFO:
205   case PIPE_CAP_PCI_GROUP:
206   case PIPE_CAP_PCI_BUS:
207   case PIPE_CAP_PCI_DEVICE:
208   case PIPE_CAP_PCI_FUNCTION:
209   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
210   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
211   case PIPE_CAP_CULL_DISTANCE:
212   case PIPE_CAP_TGSI_VOTE:
213   case PIPE_CAP_MAX_WINDOW_RECTANGLES:
214   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
215   case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
216   case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
217   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
218   case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
219   case PIPE_CAP_NATIVE_FENCE_FD:
220   case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
221   case PIPE_CAP_FBFETCH:
222   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
223   case PIPE_CAP_DOUBLES:
224   case PIPE_CAP_INT64:
225   case PIPE_CAP_INT64_DIVMOD:
226   case PIPE_CAP_TGSI_TEX_TXF_LZ:
227   case PIPE_CAP_TGSI_CLOCK:
228   case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
229   case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
230   case PIPE_CAP_TGSI_BALLOT:
231   case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
232   case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
233   case PIPE_CAP_POST_DEPTH_COVERAGE:
234   case PIPE_CAP_BINDLESS_TEXTURE:
235   case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
236   case PIPE_CAP_QUERY_SO_OVERFLOW:
237   case PIPE_CAP_MEMOBJ:
238   case PIPE_CAP_LOAD_CONSTBUF:
239   case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
240   case PIPE_CAP_TILE_RASTER_ORDER:
241   case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
242   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
243   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
244   case PIPE_CAP_CONTEXT_PRIORITY_MASK:
245   case PIPE_CAP_FENCE_SIGNAL:
246   case PIPE_CAP_CONSTBUF0_FLAGS:
247   case PIPE_CAP_PACKED_UNIFORMS:
248   case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
249   case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
250   case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
251   case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
252   case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
253   case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
254   case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
255   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
256   case PIPE_CAP_TGSI_DIV:
257   case PIPE_CAP_TGSI_ATOMINC_WRAP:
258      return 0;
259
260   case PIPE_CAP_MAX_GS_INVOCATIONS:
261      return 32;
262   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
263      return 1 << 27;
264   case PIPE_CAP_VENDOR_ID:
265      return 0x10de;
266   case PIPE_CAP_DEVICE_ID: {
267      uint64_t device_id;
268      if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
269         NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
270         return -1;
271      }
272      return device_id;
273   }
274   case PIPE_CAP_ACCELERATED:
275      return 1;
276   case PIPE_CAP_VIDEO_MEMORY:
277      return dev->vram_size >> 20;
278   case PIPE_CAP_UMA:
279      return 0;
280   default:
281      return u_pipe_screen_get_param_defaults(pscreen, param);
282   }
283}
284
285static float
286nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
287{
288   struct nv30_screen *screen = nv30_screen(pscreen);
289   struct nouveau_object *eng3d = screen->eng3d;
290
291   switch (param) {
292   case PIPE_CAPF_MAX_LINE_WIDTH:
293   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
294      return 10.0;
295   case PIPE_CAPF_MAX_POINT_WIDTH:
296   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
297      return 64.0;
298   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
299      return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
300   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
301      return 15.0;
302   case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
303   case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
304   case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
305      return 0.0;
306   default:
307      debug_printf("unknown paramf %d\n", param);
308      return 0;
309   }
310}
311
312static int
313nv30_screen_get_shader_param(struct pipe_screen *pscreen,
314                             enum pipe_shader_type shader,
315                             enum pipe_shader_cap param)
316{
317   struct nv30_screen *screen = nv30_screen(pscreen);
318   struct nouveau_object *eng3d = screen->eng3d;
319
320   switch (shader) {
321   case PIPE_SHADER_VERTEX:
322      switch (param) {
323      case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
324      case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
325         return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
326      case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
327      case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
328         return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
329      case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
330         return 0;
331      case PIPE_SHADER_CAP_MAX_INPUTS:
332      case PIPE_SHADER_CAP_MAX_OUTPUTS:
333         return 16;
334      case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
335         return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
336      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
337         return 1;
338      case PIPE_SHADER_CAP_MAX_TEMPS:
339         return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
340      case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
341         return 32;
342      case PIPE_SHADER_CAP_PREFERRED_IR:
343         return PIPE_SHADER_IR_TGSI;
344      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
345      case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
346         return 0;
347      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
348      case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
349      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
350      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
351      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
352      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
353      case PIPE_SHADER_CAP_SUBROUTINES:
354      case PIPE_SHADER_CAP_INTEGERS:
355      case PIPE_SHADER_CAP_INT64_ATOMICS:
356      case PIPE_SHADER_CAP_FP16:
357      case PIPE_SHADER_CAP_FP16_DERIVATIVES:
358      case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
359      case PIPE_SHADER_CAP_INT16:
360      case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
361      case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
362      case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
363      case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
364      case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
365      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
366      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
367      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
368      case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
369      case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
370      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
371      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
372         return 0;
373      case PIPE_SHADER_CAP_SUPPORTED_IRS:
374         return 1 << PIPE_SHADER_IR_TGSI;
375      default:
376         debug_printf("unknown vertex shader param %d\n", param);
377         return 0;
378      }
379      break;
380   case PIPE_SHADER_FRAGMENT:
381      switch (param) {
382      case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
383      case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
384      case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
385      case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
386         return 4096;
387      case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
388         return 0;
389      case PIPE_SHADER_CAP_MAX_INPUTS:
390         return 8; /* should be possible to do 10 with nv4x */
391      case PIPE_SHADER_CAP_MAX_OUTPUTS:
392         return 4;
393      case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
394         return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
395      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
396         return 1;
397      case PIPE_SHADER_CAP_MAX_TEMPS:
398         return 32;
399      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
400      case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
401         return 16;
402      case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
403         return 32;
404      case PIPE_SHADER_CAP_PREFERRED_IR:
405         return PIPE_SHADER_IR_TGSI;
406      case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
407      case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
408      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
409      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
410      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
411      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
412      case PIPE_SHADER_CAP_SUBROUTINES:
413      case PIPE_SHADER_CAP_INTEGERS:
414      case PIPE_SHADER_CAP_FP16:
415      case PIPE_SHADER_CAP_FP16_DERIVATIVES:
416      case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
417      case PIPE_SHADER_CAP_INT16:
418      case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
419      case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
420      case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
421      case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
422      case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
423      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
424      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
425      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
426      case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
427      case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
428      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
429      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
430         return 0;
431      case PIPE_SHADER_CAP_SUPPORTED_IRS:
432         return 1 << PIPE_SHADER_IR_TGSI;
433      default:
434         debug_printf("unknown fragment shader param %d\n", param);
435         return 0;
436      }
437      break;
438   default:
439      return 0;
440   }
441}
442
443static bool
444nv30_screen_is_format_supported(struct pipe_screen *pscreen,
445                                enum pipe_format format,
446                                enum pipe_texture_target target,
447                                unsigned sample_count,
448                                unsigned storage_sample_count,
449                                unsigned bindings)
450{
451   if (sample_count > nv30_screen(pscreen)->max_sample_count)
452      return false;
453
454   if (!(0x00000017 & (1 << sample_count)))
455      return false;
456
457   if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
458      return false;
459
460   /* No way to render to a swizzled 3d texture. We don't necessarily know if
461    * it's swizzled or not here, but we have to assume anyways.
462    */
463   if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
464      return false;
465
466   /* shared is always supported */
467   bindings &= ~PIPE_BIND_SHARED;
468
469   if (bindings & PIPE_BIND_INDEX_BUFFER) {
470      if (format != PIPE_FORMAT_R8_UINT &&
471          format != PIPE_FORMAT_R16_UINT &&
472          format != PIPE_FORMAT_R32_UINT)
473         return false;
474      bindings &= ~PIPE_BIND_INDEX_BUFFER;
475   }
476
477   return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
478}
479
480static void
481nv30_screen_fence_emit(struct pipe_screen *pscreen, uint32_t *sequence)
482{
483   struct nv30_screen *screen = nv30_screen(pscreen);
484   struct nouveau_pushbuf *push = screen->base.pushbuf;
485
486   *sequence = ++screen->base.fence.sequence;
487
488   assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
489   PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
490              (2 /* size */ << 18) | (7 /* subchan */ << 13));
491   PUSH_DATA (push, 0);
492   PUSH_DATA (push, *sequence);
493}
494
495static uint32_t
496nv30_screen_fence_update(struct pipe_screen *pscreen)
497{
498   struct nv30_screen *screen = nv30_screen(pscreen);
499   struct nv04_notify *fence = screen->fence->data;
500   return *(uint32_t *)((char *)screen->notify->map + fence->offset);
501}
502
503static void
504nv30_screen_destroy(struct pipe_screen *pscreen)
505{
506   struct nv30_screen *screen = nv30_screen(pscreen);
507
508   if (!nouveau_drm_screen_unref(&screen->base))
509      return;
510
511   nouveau_fence_cleanup(&screen->base);
512
513   nouveau_bo_ref(NULL, &screen->notify);
514
515   nouveau_heap_destroy(&screen->query_heap);
516   nouveau_heap_destroy(&screen->vp_exec_heap);
517   nouveau_heap_destroy(&screen->vp_data_heap);
518
519   nouveau_object_del(&screen->query);
520   nouveau_object_del(&screen->fence);
521   nouveau_object_del(&screen->ntfy);
522
523   nouveau_object_del(&screen->sifm);
524   nouveau_object_del(&screen->swzsurf);
525   nouveau_object_del(&screen->surf2d);
526   nouveau_object_del(&screen->m2mf);
527   nouveau_object_del(&screen->eng3d);
528   nouveau_object_del(&screen->null);
529
530   nouveau_screen_fini(&screen->base);
531   FREE(screen);
532}
533
534#define FAIL_SCREEN_INIT(str, err)                    \
535   do {                                               \
536      NOUVEAU_ERR(str, err);                          \
537      screen->base.base.context_create = NULL;        \
538      return &screen->base;                           \
539   } while(0)
540
541struct nouveau_screen *
542nv30_screen_create(struct nouveau_device *dev)
543{
544   struct nv30_screen *screen;
545   struct pipe_screen *pscreen;
546   struct nouveau_pushbuf *push;
547   struct nv04_fifo *fifo;
548   unsigned oclass = 0;
549   int ret, i;
550
551   switch (dev->chipset & 0xf0) {
552   case 0x30:
553      if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
554         oclass = NV30_3D_CLASS;
555      else
556      if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
557         oclass = NV34_3D_CLASS;
558      else
559      if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
560         oclass = NV35_3D_CLASS;
561      break;
562   case 0x40:
563      if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
564         oclass = NV40_3D_CLASS;
565      else
566      if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
567         oclass = NV44_3D_CLASS;
568      break;
569   case 0x60:
570      if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
571         oclass = NV44_3D_CLASS;
572      break;
573   default:
574      break;
575   }
576
577   if (!oclass) {
578      NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
579      return NULL;
580   }
581
582   screen = CALLOC_STRUCT(nv30_screen);
583   if (!screen)
584      return NULL;
585
586   pscreen = &screen->base.base;
587   pscreen->destroy = nv30_screen_destroy;
588
589   /*
590    * Some modern apps try to use msaa without keeping in mind the
591    * restrictions on videomem of older cards. Resulting in dmesg saying:
592    * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
593    * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
594    * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
595    *
596    * Because we are running out of video memory, after which the program
597    * using the msaa visual freezes, and eventually the entire system freezes.
598    *
599    * To work around this we do not allow msaa visauls by default and allow
600    * the user to override this via NV30_MAX_MSAA.
601    */
602   screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
603   if (screen->max_sample_count > 4)
604      screen->max_sample_count = 4;
605
606   pscreen->get_param = nv30_screen_get_param;
607   pscreen->get_paramf = nv30_screen_get_paramf;
608   pscreen->get_shader_param = nv30_screen_get_shader_param;
609   pscreen->context_create = nv30_context_create;
610   pscreen->is_format_supported = nv30_screen_is_format_supported;
611   nv30_resource_screen_init(pscreen);
612   nouveau_screen_init_vdec(&screen->base);
613
614   screen->base.fence.emit = nv30_screen_fence_emit;
615   screen->base.fence.update = nv30_screen_fence_update;
616
617   ret = nouveau_screen_init(&screen->base, dev);
618   if (ret)
619      FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
620
621   screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
622   screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
623   if (oclass == NV40_3D_CLASS) {
624      screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
625      screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
626   }
627
628   fifo = screen->base.channel->data;
629   push = screen->base.pushbuf;
630   push->rsvd_kick = 16;
631
632   ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
633                            NULL, 0, &screen->null);
634   if (ret)
635      FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
636
637   /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
638    * this means that the address pointed at by the DMA object must
639    * be 4KiB aligned, which means this object needs to be the first
640    * one allocated on the channel.
641    */
642   ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
643                            NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
644                            .length = 32 }, sizeof(struct nv04_notify),
645                            &screen->fence);
646   if (ret)
647      FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
648
649   /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
650   ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
651                            NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
652                            .length = 32 }, sizeof(struct nv04_notify),
653                            &screen->ntfy);
654   if (ret)
655      FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
656
657   /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
658    * the remainder of the "notifier block" assigned by the kernel for
659    * use as query objects
660    */
661   ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
662                            NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
663                            .length = 4096 - 128 }, sizeof(struct nv04_notify),
664                            &screen->query);
665   if (ret)
666      FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
667
668   ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
669   if (ret)
670      FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
671
672   list_inithead(&screen->queries);
673
674   /* Vertex program resources (code/data), currently 6 of the constant
675    * slots are reserved to implement user clipping planes
676    */
677   if (oclass < NV40_3D_CLASS) {
678      nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
679      nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
680   } else {
681      nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
682      nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
683   }
684
685   ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
686   if (ret == 0)
687      ret = nouveau_bo_map(screen->notify, 0, screen->base.client);
688   if (ret)
689      FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
690
691   ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
692                            NULL, 0, &screen->eng3d);
693   if (ret)
694      FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
695
696   BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
697   PUSH_DATA (push, screen->eng3d->handle);
698   BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
699   PUSH_DATA (push, screen->ntfy->handle);
700   PUSH_DATA (push, fifo->vram);     /* TEXTURE0 */
701   PUSH_DATA (push, fifo->gart);     /* TEXTURE1 */
702   PUSH_DATA (push, fifo->vram);     /* COLOR1 */
703   PUSH_DATA (push, screen->null->handle);  /* UNK190 */
704   PUSH_DATA (push, fifo->vram);     /* COLOR0 */
705   PUSH_DATA (push, fifo->vram);     /* ZETA */
706   PUSH_DATA (push, fifo->vram);     /* VTXBUF0 */
707   PUSH_DATA (push, fifo->gart);     /* VTXBUF1 */
708   PUSH_DATA (push, screen->fence->handle);  /* FENCE */
709   PUSH_DATA (push, screen->query->handle);  /* QUERY - intr 0x80 if nullobj */
710   PUSH_DATA (push, screen->null->handle);  /* UNK1AC */
711   PUSH_DATA (push, screen->null->handle);  /* UNK1B0 */
712   if (screen->eng3d->oclass < NV40_3D_CLASS) {
713      BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
714      PUSH_DATA (push, 0x00100000);
715      BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
716      PUSH_DATA (push, 3);
717
718      BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
719      PUSH_DATA (push, 0);
720      BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
721      PUSH_DATA (push, fui(0.0));
722      PUSH_DATA (push, fui(0.0));
723      PUSH_DATA (push, fui(1.0));
724      BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
725      for (i = 0; i < 16; i++)
726         PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
727
728      BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
729      PUSH_DATA (push, 0);
730   } else {
731      BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
732      PUSH_DATA (push, fifo->vram);
733      PUSH_DATA (push, fifo->vram);  /* COLOR3 */
734
735      BEGIN_NV04(push, SUBC_3D(0x1450), 1);
736      PUSH_DATA (push, 0x00000004);
737
738      BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
739      PUSH_DATA (push, 0x00000010);
740      PUSH_DATA (push, 0x01000100);
741      PUSH_DATA (push, 0xff800006);
742
743      /* vtxprog output routing */
744      BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
745      PUSH_DATA (push, 0x06144321);
746      BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
747      PUSH_DATA (push, 0xedcba987);
748      PUSH_DATA (push, 0x0000006f);
749      BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
750      PUSH_DATA (push, 0x00171615);
751      BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
752      PUSH_DATA (push, 0x001b1a19);
753
754      BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
755      PUSH_DATA (push, 0x0020ffff);
756      BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
757      PUSH_DATA (push, 0x01d300d4);
758
759      BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
760      PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
761   }
762
763   ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
764                            NULL, 0, &screen->m2mf);
765   if (ret)
766      FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
767
768   BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
769   PUSH_DATA (push, screen->m2mf->handle);
770   BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
771   PUSH_DATA (push, screen->ntfy->handle);
772
773   ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
774                            NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
775   if (ret)
776      FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
777
778   BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
779   PUSH_DATA (push, screen->surf2d->handle);
780   BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
781   PUSH_DATA (push, screen->ntfy->handle);
782
783   if (dev->chipset < 0x40)
784      oclass = NV30_SURFACE_SWZ_CLASS;
785   else
786      oclass = NV40_SURFACE_SWZ_CLASS;
787
788   ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
789                            NULL, 0, &screen->swzsurf);
790   if (ret)
791      FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
792
793   BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
794   PUSH_DATA (push, screen->swzsurf->handle);
795   BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
796   PUSH_DATA (push, screen->ntfy->handle);
797
798   if (dev->chipset < 0x40)
799      oclass = NV30_SIFM_CLASS;
800   else
801      oclass = NV40_SIFM_CLASS;
802
803   ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
804                            NULL, 0, &screen->sifm);
805   if (ret)
806      FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
807
808   BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
809   PUSH_DATA (push, screen->sifm->handle);
810   BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
811   PUSH_DATA (push, screen->ntfy->handle);
812   BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
813   PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
814
815   nouveau_pushbuf_kick(push, push->channel);
816
817   nouveau_fence_new(&screen->base, &screen->base.fence.current);
818   return &screen->base;
819}
820